JP2748746B2 - Phase locked oscillator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked oscillator which is frequently used in a device for processing multiplexed digital signals, and more particularly to a high-speed clock signal and a low-speed clock signal which is phase-locked to this signal. The present invention relates to a phase-locked oscillator that generates a low-speed clock signal having a predetermined phase relationship with a high-speed clock signal synchronized with an input high-speed clock and a low-speed clock signal input.

[0002]

2. Description of the Related Art A multiplexed digital signal usually has a frame structure. For this reason, in a multiplex conversion device or the like that processes such a signal, a high-speed clock signal for identifying individual pulses of the multiplexed signal inside the device and a low-speed clock signal for processing the multiplexed signal in frame units are used. Is required.

Further, in order to efficiently perform signal processing between connected devices, it is not only necessary that the frequency of input / output signals of a multiplex conversion device or the like be strictly equal,
The frame phase also needs to be a predetermined phase. For this reason, the station is provided with a clock supply device that supplies a station reference clock for defining a reference frequency and a frame phase, and each multiplex conversion device or the like inputs this station reference clock and sets the clock in the device. The necessary frequencies and phases of various clocks are determined.

In general, a station reference clock is a composite signal in which a low-speed clock signal for defining a reference frame phase is superimposed on a high-speed clock signal, and a multiplex converter or the like inputs this composite signal and internally outputs the high-speed clock signal. After being separated into low-speed clock signals and various low-speed clock signals, the clock signals are converted into various clock signals required internally by a phase-locked oscillator.

FIG. 6 shows a first conventional example. In the conventional example shown in FIG. 6, a first input terminal 1 for inputting a high-speed clock signal is provided.
00 and a second input terminal 1 for inputting a low-speed clock signal.
01, a phase comparator 10 that compares the phase of the high-speed clock signal input from the first input terminal 100 with the phase of the high-speed clock signal generated by the voltage controlled oscillator 40 and generates a voltage corresponding to the phase difference between the two signals; The voltage generated by the phase comparator 10 is used as a control voltage to generate a high-speed clock signal based on the voltage. The voltage-controlled oscillator 40 generates a high-speed clock signal.
A frequency dividing circuit 51 for generating a predetermined low-speed clock signal by synchronizing the phase with the low-speed clock signal input from the first input terminal 1; a first output terminal 200 for outputting the high-speed clock signal generated by the voltage controlled oscillator 40; A second output terminal 201 for outputting a low-speed clock signal generated by the circuit 51;

Next, the operation of the first conventional example will be described.

When a high-speed clock signal is input from the first input terminal 100, the phase comparator 10 compares the phase of the high-speed clock signal with the phase of the high-speed clock signal generated by the voltage controlled oscillator 40, and compares the phase difference. The corresponding voltage is output. The voltage-controlled oscillator 40 generates a high-speed clock signal having a phase difference of 0 based on the control voltage from the phase comparator 10. The frequency dividing circuit 51 divides the frequency of the high-speed clock signal generated by the voltage-controlled oscillator 40 so as to synchronize the phase with the low-speed clock signal input from the second input terminal 101, and outputs the frequency as a low-speed clock signal.

FIG. 7 shows a second conventional example. In the conventional example of FIG. 7, a second input terminal 101 for inputting a low-speed clock signal is used.
And a phase comparator that compares the phase of the low-speed clock signal input from the second input terminal 101 with the phase of the low-speed clock signal generated by the frequency dividing circuit 50 and generates two different logic levels according to the phase relationship between the two signals. 20, an integrator 21 for integrating the output signal of the phase comparator 20 to generate a control voltage for the voltage controlled oscillator 40, and a voltage for generating a high-speed clock signal based on the voltage generated by the integrator 21 as a control voltage. A control oscillator 40, a frequency dividing circuit 50 for converting an output signal of the voltage controlled oscillator 40 into a low speed clock signal having the same frequency as the input low speed clock signal, and a high speed clock signal generated by the voltage controlled oscillator 40 It has a first output terminal 200 for outputting, and a second output terminal 201 for outputting a low-speed clock signal generated by the frequency dividing circuit 51.

Next, the operation of the second conventional example will be described.

When a low-speed clock signal is input from the second input terminal 101, the phase comparator 20 compares the phase of the low-speed clock signal with the phase of the low-speed clock signal generated by the frequency dividing circuit 50, and compares the phases. Either of two different logic levels "1" and "-1" is generated according to the phase difference.
The integrator 21 integrates the output signal of the phase comparator 20 and outputs an average voltage. In the voltage controlled oscillator 40, the output voltage of the integrator 21 is used as a control voltage, and a signal of the maximum frequency is output as "1" and a signal of the minimum frequency is output as a high-speed clock signal when it is "-1". In the frequency dividing circuit 50, the high-speed clock signal from the voltage controlled oscillator 40 is frequency-divided and output as a low-speed clock signal having the same frequency as the input low-speed clock signal.

That is, in the phase locked oscillator according to the second conventional example, only a low-speed clock signal is input, and a low-speed clock signal and a high-speed clock signal that are phase-synchronized with the low-speed clock signal are generated.

[0012]

However, in the first conventional example, since the low-speed clock signal is generated outside the phase-locked loop, when the externally input low-speed clock signal is disturbed, There is an inconvenience that the immediately output low-speed clock signal is greatly affected. That is, when the input high-speed clock signal is disturbed, the influence on the output clock signal can be reduced by appropriately determining the characteristics of the phase-locked oscillator, but when the input low-speed clock signal is disturbed. However, even if the disturbance is instantaneous, the output phase control of the frequency divider circuit is performed immediately, and the phase of the output low-speed clock signal fluctuates instantaneously. However, there is an inconvenience that serious erroneous operation is caused to the multiplex conversion device or the like.

In the second prior art, the above problem is solved because the high-speed clock signal is not directly input and only the low-speed clock signal is used as the phase comparison input. However, it is necessary to minimize the steady-state phase error in order to reliably identify individual pulses of the multiplexed signal,
This makes the phase comparison characteristics of the phase comparator extremely sharp,
It was necessary to use a special phase-locked oscillator having a complete integration element as a loop filter. However, such a special phase-locked oscillator has an infinite DC loop gain, so its steady-state characteristics are unstable, and it is not only possible to suppress unnecessary phase fluctuations, i.e., jitter contained in the input clock, but also in extreme cases. There was a drawback that jitter occurred on its own.

[0014]

SUMMARY OF THE INVENTION It is an object of the present invention to improve the disadvantages of the prior art. In particular, a high-speed clock signal and a low-speed clock signal synchronized with the high-speed clock signal are input from the outside, and the two types of clock signals are phase-shifted. In a phase-locked oscillator that generates synchronized high-speed clock signals and low-speed clock signals, even if there is disturbance in the externally input clock, the output clock has little effect and generates a stable output clock without unnecessary phase fluctuations It is an object of the present invention to provide a phase-locked oscillator capable of performing the following.

[0015]

Therefore, according to the present invention, there is provided a first input terminal for inputting a high-speed clock signal having a period t,
A second input terminal for inputting a low-speed clock signal having a period T, a high-speed clock signal input from the first input terminal, and a high-speed clock signal generated by a voltage-controlled oscillator are compared with each other. A first phase comparator for generating a voltage, a low-speed clock signal generated by a frequency dividing circuit, and a high-speed clock signal generated by a voltage-controlled oscillator are inputted, and the position of one of the low-speed clock signal pulses is changed to "t". / 2 "
The pulse width converted into a signal in which the pulse having the pulse width of (“T / 2” − “t / 2”) and the pulse having the pulse width of “(T / 2” + “t / 2”) are alternately arranged A conversion circuit;
A second phase comparator that compares the phase of the output signal of the pulse width conversion circuit with the low-speed clock signal input from the second input terminal and generates two different logic levels according to the phase relationship between the two signals; An integrator for integrating an output signal of the second phase comparator and generating an average voltage of an output logic level;
A voltage adder that adds the output voltage of the phase comparator and the output voltage of the integrator to generate a control voltage for the voltage-controlled oscillator, and generates a high-speed clock signal based on the voltage generated by the voltage adder as a control voltage. Voltage-controlled oscillator, a frequency dividing circuit for dividing a high-speed clock signal generated by the voltage-controlled oscillator to generate a predetermined low-speed clock signal, and a first output for outputting a high-speed clock signal generated by the voltage-controlled oscillator A terminal and a second output terminal for outputting the low-speed clock signal generated by the frequency dividing circuit are provided. This aims to achieve the above-mentioned object.

[0016]

A high-speed clock signal having a period t and a low-speed clock signal having a period T are inputted from outside.

(1) The phase difference between the output signal of the pulse width conversion circuit and the externally input low-speed clock signal is "t / 2"
Above or below "-t / 2":

Since the falling point of the output signal of the pulse width conversion circuit changes by "t / 2" in comparison with the low-speed clock signal from the frequency dividing circuit at a period of 2T, the output signal of the pulse width conversion circuit is output. If the phase difference between the clock signal and the externally input low-speed clock signal is greater than or equal to "t / 2" or less than or equal to "-t / 2", the output of the second phase comparator always has the logic level "1" or " -1 ", and the output voltage of the integrator 21 becomes" 1 "or" -1 ". Therefore, the control voltage generated from the voltage adder is "1" or "-1" regardless of the output voltage of the first phase comparator. When the voltage output from the integrator is "1", the voltage-controlled oscillator uses the signal of the minimum frequency when the voltage is "-1" of the maximum frequency and synchronizes the phase with the input high-speed clock signal as a high-speed clock signal. Occur. The frequency divider divides the frequency of the high-speed clock signal output from the voltage-controlled oscillator, and outputs a low-speed clock signal having a predetermined phase relationship with the input low-speed clock signal.

(2) The phase difference between the output signal of the pulse width conversion circuit and the externally input low-speed clock signal is "t / 2"
Below or "-t / 2" or more:

The first phase comparator generates a voltage corresponding to a phase difference between two high-speed clock signals, that is, a high-speed clock signal from the outside and a high-speed clock signal generated by a voltage-controlled oscillator. Since the falling point of the output signal of the pulse width conversion circuit changes by "t / 2" in comparison with the low-speed clock signal from the frequency dividing circuit at a period of 2T, the output signal of the pulse width conversion circuit and the external signal When the phase difference of the input low-speed clock signal is equal to or less than “t / 2” or equal to or more than “−t / 2”, the output signal of the second phase comparator changes to logic level “1” every 2T cycle. Output level "-1".
At this time, the output voltage of the integrator 21 becomes 0. And
As long as the phase difference between the output signal of the pulse width conversion circuit input to the second phase comparator and the low-speed clock signal input from the outside is "t / 2" or less, or "-t / 2" or more, the second The output signal of the phase comparator is a rectangular wave having a period of 2T. Even if the phase difference between the two signals changes within this range, the output voltage 0 of the integrator does not change. At this time, the control voltage output from the voltage adder is equal to the voltage output from the first phase comparator. Accordingly, the voltage controlled oscillator uses the voltage output from the first phase comparator as a control voltage and generates a high-speed clock signal that is phase-synchronized with the input high-speed clock signal. Further, the frequency divider divides the frequency of the high-speed clock signal output from the voltage-controlled oscillator, and outputs a low-speed clock signal having a predetermined phase relationship with the input low-speed clock signal.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS.

The embodiment shown in FIG. 1 has a first input terminal 100 for inputting a high-speed clock signal f100 having a period t, and a second input terminal 10 having a low-speed clock signal f101 having a period T input.
1 and a high-speed clock signal f100 input from the first input terminal 100, and a phase of a high-speed clock signal f200 generated by a voltage-controlled oscillator 40, which will be described later, to generate a voltage corresponding to the phase difference between the two signals. , The low-speed clock signal generated by the frequency dividing circuit 50 and the high-speed clock signal generated by the voltage-controlled oscillator 40 are input, and the position of one change point of the pulse of the low-speed clock signal is changed by “t / 2”. Pulse width conversion for changing a pulse having a pulse width of (“T / 2” − “t / 2”) and a pulse of (“T / 2” + “t / 2”) alternately arranged Circuit 60, the phase of the output signal f60 of the pulse width conversion circuit 60, and the low-speed clock signal f101 input from the second input terminal 101.
And a second phase comparator 20 for generating two different logic levels according to the phase relationship between the two signals, and an output signal f20 of the second phase comparator 20 and integrating the average voltage of the output logic levels. Generating integrator 21 and first phase comparator 10
A voltage adder 30 that adds the output voltage of the integrator 21 and the output voltage of the integrator 21 to generate a control voltage of the voltage controlled oscillator 40, and generates a high-speed clock signal based on the voltage generated by the voltage adder 30 as a control voltage. Voltage controlled oscillator 40
And a frequency dividing circuit 50 for dividing the high-speed clock signal generated by the voltage-controlled oscillator 40 and generating a predetermined low-speed clock signal
A first output terminal 200 for outputting a high-speed clock signal generated by the voltage-controlled oscillator 40, and a second output terminal 201 for outputting a low-speed clock signal generated by the frequency dividing circuit 50. I have.

Here, the first phase comparator 10 has a first input terminal 100 as shown in the phase comparison characteristic diagram of FIG.
When the difference between the phase of the high-speed clock signal f100 input from the controller and the phase of the high-speed clock signal f200 generated by the voltage controlled oscillator 40 is “t / 2”, the maximum value “1” is changed to “−t / 2”.
In this case, the minimum value "-1" is output, and the phase difference and the output are in a linear relationship. That is, when the phase difference is between “t / 2” and “−t / 2”, the outputs are “1” and “−1”.
Take a value between.

Further, as shown in the phase comparison characteristic diagram of FIG. 3, the second phase comparator 20 controls the phase of the output signal f60 of the pulse width conversion circuit 60 and the low-speed clock input from the second input terminal 101. When the phase difference of the signal f101 is "0" and "T
/ 2 ”,“ 1 ”is output, and when the phase difference is between“ −T / 2 ”and“ 0 ”,“ −1 ”is output.

In this embodiment, the voltage controlled oscillator 40
Is the maximum frequency when the given control voltage is "1", and "-
1 ", a minimum frequency is generated.
0 means that the maximum output voltage is "1" regardless of the input voltage
In addition, it is assumed that the minimum output voltage is limited to “−1”.

Next, the operation of this embodiment will be described with reference to FIG.

A high-speed clock signal f100 having a period t from the first input terminal 100 is transmitted from the second input terminal 101 at a period T.
Is input.

(1) Output signal f of pulse width conversion circuit 60
When the phase difference between 60 and the low-speed clock signal f101 input from the second input terminal 101 is "t / 2" or more:

As shown in FIG. 4, the pulse width conversion circuit 6
Since the falling transition point of the output signal f60 of 0 changes by “t / 2” in the period 2T, the pulse width conversion circuit 6
When the phase difference between the output signal f60 of “0” and the low-speed clock signal f101 input from the second input terminal 101 is “t / 2” or more, the second phase comparator 20 always outputs the logical level “1”. Is output.

In this state, the output voltage of the integrator 21 also becomes "1".

The first phase comparator 10 has two high-speed clock signals, a high-speed clock signal f100 from a first input terminal 100 input to the phase comparator and a high-speed clock signal f200 generated by the voltage controlled oscillator 40. Are generated in accordance with the phase difference of.

However, since the output voltage of the integrator 21 is "1", the control voltage generated from the voltage adder 30 is "1" regardless of the output voltage of the first phase comparator 10. .

Since the voltage control oscillator 40 uses the voltage output from the integrator 21, that is, “1”, as the control voltage, it generates a signal of the maximum frequency synchronized with the input high-speed clock signal as the high-speed clock signal f 200. .

The frequency dividing circuit 50 divides the frequency of the high-speed clock signal f200 output from the voltage-controlled oscillator 40 and outputs it as a low-speed clock signal f201 having a predetermined phase relationship with the input low-speed clock signal f101.

(2) Output signal f of pulse width conversion circuit 60
When the phase difference between 60 and the low-speed clock signal f101 input from the second input terminal 101 is equal to or less than "-t / 2":

As shown in FIG. 4, the pulse width conversion circuit 6
Since the falling transition point of the output signal f60 of 0 changes by “t / 2” in the period 2T, the pulse width conversion circuit 6
When the phase difference between the 0 output signal f60 and the low-speed clock signal f101 input from the second input terminal 101 is equal to or smaller than "-t / 2", the second phase comparator 20 always outputs the logical level "-". 1 "is output.

In this state, the output voltage of the integrator 21 is also "-
1 ".

The first phase comparator 10 has two high-speed clock signals, a high-speed clock signal f100 from the first input terminal 100 input to the phase comparator and a high-speed clock signal f200 generated by the voltage controlled oscillator 40. Are generated in accordance with the phase difference of.

However, the output voltage of the integrator 21 is "-1".
Therefore, the control voltage generated from the voltage adder 30 is “−” regardless of the output voltage of the first phase comparator 10.
1 ".

The voltage controlled oscillator 40 uses the voltage output from the integrator 21, that is, “−1” as the control voltage.
A signal having the minimum frequency synchronized with the input high-speed clock signal is generated as a high-speed clock signal f200.

The frequency dividing circuit 50 divides the frequency of the high-speed clock signal f200 output from the voltage-controlled oscillator 40 and outputs it as a low-speed clock signal f201 having a predetermined phase relationship with the input low-speed clock signal f101.

(3) Output signal f of pulse width conversion circuit 60
60 and the low-speed clock signal f101 input from the second input terminal 101 have a phase difference of "t / 2" or less or "-t /
2 "or more:

In the first phase comparator 10, a voltage corresponding to the phase difference between two high-speed clock signals, that is, the high-speed clock signal f100 from the first input terminal 100 and the high-speed clock signal f200 generated by the voltage-controlled oscillator 40 is generated. Generated.

Since the falling point of the output signal f60 of the pulse width conversion circuit 60 changes by "t / 2" in the cycle 2T, the pulse width conversion circuit 6 as shown in FIG.
If the phase difference between the 0 output signal f60 and the low-speed clock signal f101 input from the second input terminal 101 is "t / 2" or less or "-t / 2" or more, the second phase comparator 2
The output signal f20 of 0 outputs a logic level "1" and a logic level "-1" every cycle 2T.

Since the time constant of the integrator 21 is sufficiently large, the output voltage of the integrator 21 becomes zero. And the second
The phase difference between the output signal f60 of the pulse width conversion circuit 60 input to the phase comparator 20 and the low-speed clock signal f101 input from the second input terminal 101 is "t / 2" or less or "-t / 2". As far as described above, the output signal of the second phase comparator 20 is a rectangular wave having a period of 2T, and the output voltage 0 of the integrator 21 does not change even if the phase difference between the two signals changes within this range. .

At this time, the control voltage output from the voltage adder 30 is equal to the voltage output from the first phase comparator 10.

Accordingly, the voltage controlled oscillator 40 uses the voltage output from the first phase comparator 10 as a control voltage and generates a signal synchronized in phase with the input high-speed clock signal as a high-speed clock signal f200.

Further, the frequency dividing circuit 50 includes the voltage controlled oscillator 40
Divides the high-speed clock signal f200 output from the oscilloscope and outputs it as a low-speed clock signal f201 having a predetermined phase relationship with the input low-speed clock signal f101.

That is, as shown in FIG. 5, the phase comparison characteristic of the control voltage generated from the voltage adder 30 of the present embodiment is such that the phase difference between the input and output clock signals is within “± t / 2”. In this case, the control voltage having the maximum value “1” is equal to the phase comparison characteristic of the first phase comparator 10 shown in FIG. 2 when the phase difference is “t / 2”, and the phase difference is “−t / At the time of "2", the control voltage of the minimum value "-1" is output, and the phase difference and the control voltage are in a linear relationship. When the maximum control voltage "1" of the voltage controlled oscillator 40 is "-t / 2" or less, the minimum control voltage "-1" is output.

Therefore, when a reference clock signal having an arbitrary phase is input, first, the phase of the low-speed clock signal input from the second phase comparator 20 is compared with the phase of the low-speed clock signal output from the voltage controlled oscillator 40. The frequency of the voltage controlled oscillator 40 is controlled so that the phase difference between the two clock signals is within “± t / 2”. Next, when the phase difference between the input and output clock signals falls within “± t / 2”, the second phase comparator 20 becomes invalid, but instead the first phase comparator 10
Generates a control voltage so that the phase difference between the input and output clock signals becomes 0, and has a predetermined phase relationship between the high-speed clock signal phase-synchronized with the input high-speed clock signal and the input low-speed clock signal. A low speed clock signal is generated.

[0051]

Since the present invention is constructed and functions as described above, according to the present invention, since both input signals are given to the phase locked loop input, even if the input signal is disturbed, the output signal is not changed. The effect can be reduced, and when phase synchronization is established, phase control is effectively applied by a high-speed clock signal, so it is necessary to use a perfect integration element in an extremely sensitive phase comparator and loop filter. Thus, it is possible to provide an unprecedented excellent phase-locked oscillator capable of generating a stable clock signal without unnecessary phase fluctuation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a phase comparison characteristic diagram of the first phase comparator of FIG.

FIG. 3 is a phase comparison characteristic diagram of the second phase comparator of FIG. 1;

FIG. 4 is a waveform chart showing an operation of each unit in FIG. 1;

FIG. 5 is a phase comparison characteristic diagram of the voltage adder of FIG. 1;

FIG. 6 is a block diagram showing a first conventional example.

FIG. 7 is a block diagram showing a second conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 1st phase comparator 20 2nd phase comparator 21 integrator 30 voltage adder 40 voltage controlled oscillator 50 frequency divider 60 pulse width conversion circuit 100 1st input terminal 101 2nd input terminal 200 1st Output terminal 201 Second output terminal

Claims (1)

(57) [Claims] A phase-locked oscillator that receives a high-speed clock signal and a low-speed clock signal synchronized with the high-speed clock signal from an external device and generates a high-speed clock signal and a low-speed clock signal that are phase-synchronized with the two types of clock signals. A voltage-controlled oscillator that generates a clock signal having a frequency corresponding to a given control voltage, and compares the phases of the input high-speed clock signal and the clock signal generated by the voltage-controlled oscillator, and according to the phase difference between the two. A first phase comparator for generating a voltage, a frequency divider for converting the generated clock signal into a low-speed clock signal having the same frequency as the input low-speed clock signal, and a pulse width of an output signal of the frequency divider. A pulse width conversion circuit for changing by a half period of the high-speed clock signal input at a predetermined period; A second phase comparator for comparing the phase of the output signal of the conversion circuit with the phase of the input low-speed clock signal and generating a binary signal according to the phase difference between the two; and an output signal of the second phase comparator. A phase comprising: an integrator that integrates to generate an average voltage; and a voltage adder that adds an output voltage of the integrator and an output signal of a first phase comparator to generate a control voltage of a voltage controlled oscillator. Synchronous oscillator.