JP5025399B2 - 配線基板及びその製造方法 - Google Patents
配線基板及びその製造方法 Download PDFInfo
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- JP5025399B2 JP5025399B2 JP2007250807A JP2007250807A JP5025399B2 JP 5025399 B2 JP5025399 B2 JP 5025399B2 JP 2007250807 A JP2007250807 A JP 2007250807A JP 2007250807 A JP2007250807 A JP 2007250807A JP 5025399 B2 JP5025399 B2 JP 5025399B2
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- wiring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09136—Means for correcting warpage
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
- H05K2201/2018—Presence of a frame in a printed circuit or printed circuit assembly
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structure Of Printed Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
複数の配線層と絶縁層が積層された配線部材と、
前記配線部材に設けられた接続パッドの形成位置と対応する位置に貫通孔が形成されると共に、一側面が前記配線部材の一面側に露出するよう前記絶縁層に配設される補強部材とを有し、
前記補強部材が前記絶縁層内に配設された際、前記接続パッドが前記貫通孔から露出し、かつ前記補強部材の前記絶縁層から露出した面と前記接続パッドとが面一となるよう構成したことを特徴とする配線基板により解決することができる。
また上記の課題は、本発明の他の観点からは、
支持基板に接続パッドを形成する工程と、
前記接続パッドの形成位置に対応した貫通孔が形成された補強部材を、前記接続パッドが前記貫通孔から露出するよう前記支持基板上に配設する工程と、
前記補強部材に絶縁樹脂を配設し、該絶縁樹脂を硬化させて前記補強部材上に絶縁層を形成する工程と、
前記補強部材が配設された前記支持体上に、配線層と絶縁層を積層して配線部材を形成する工程と、
前記配線部材から前記支持体を除去する工程とを有することを特徴とする配線基板の製造方法により解決することができる。
この補強部材53の材料としては、例えば金属(銅或いはアルミニウム等)、ガラス、セラミック、硬質樹脂、及び銅張り積層板(FRグレードがFR−4のもの)等を適用することができる。また補強部材53は、接続パッド18の形成位置に対応して貫通孔53Xが形成されており、よって図9(B)に示すように接続パッド18は貫通孔53Xを介して外部に露出している。このため、図9(A)に示すように、半導体チップ11を第1の外部端子C1となる接続パッド18にフリップチップ接合することができる。
10 支持体
11 半導体チップ
16 レジスト膜
18 接続パッド
18a 第2配線層
18b 第3配線層
18c 第4配線層
19 金型
20 第1絶縁層
22 ソルダーレジスト
29 はんだバンプ
30,32 配線部材
36 接着部材
50,51,52,53 補強部材
50X,51X,52X 開口部
51Y,52Y 鍔部
53X 貫通孔
60 放熱部材
Claims (3)
- 複数の配線層と絶縁層が積層された配線部材と、
前記配線部材に設けられた接続パッドの形成位置と対応する位置に貫通孔が形成されると共に、一側面が前記配線部材の一面側に露出するよう前記絶縁層に配設される補強部材とを有し、
前記補強部材が前記絶縁層内に配設された際、前記接続パッドが前記貫通孔から露出し、かつ前記補強部材の前記絶縁層から露出した面と前記接続パッドとが面一となるよう構成したことを特徴とする配線基板。 - 前記補強部材の表面を粗面としたことを特徴とする請求項1記載の配線基板。
- 支持基板に接続パッドを形成する工程と、
前記接続パッドの形成位置に対応した貫通孔が形成された補強部材を、前記接続パッドが前記貫通孔から露出するよう前記支持基板上に配設する工程と、
前記補強部材に絶縁樹脂を配設し、該絶縁樹脂を硬化させて前記補強部材上に絶縁層を形成する工程と、
前記補強部材が配設された前記支持体上に、配線層と絶縁層を積層して配線部材を形成する工程と、
前記配線部材から前記支持体を除去する工程と、
を有することを特徴とする配線基板の製造方法。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007250807A JP5025399B2 (ja) | 2007-09-27 | 2007-09-27 | 配線基板及びその製造方法 |
KR1020080090916A KR20090033004A (ko) | 2007-09-27 | 2008-09-17 | 배선 기판 및 그 제조 방법 |
US12/236,118 US20090084585A1 (en) | 2007-09-27 | 2008-09-23 | Wiring substrate and method of manufacturing the same |
TW097137221A TW200921874A (en) | 2007-09-27 | 2008-09-26 | Wiring substrate and method of manufacturing the same |
CN2011102042880A CN102280435A (zh) | 2007-09-27 | 2008-09-27 | 配线基板及其制造的方法 |
CN2008101488407A CN101399248B (zh) | 2007-09-27 | 2008-09-27 | 配线基板及其制造的方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007250807A JP5025399B2 (ja) | 2007-09-27 | 2007-09-27 | 配線基板及びその製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2009081358A JP2009081358A (ja) | 2009-04-16 |
JP2009081358A5 JP2009081358A5 (ja) | 2010-06-17 |
JP5025399B2 true JP5025399B2 (ja) | 2012-09-12 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007250807A Expired - Fee Related JP5025399B2 (ja) | 2007-09-27 | 2007-09-27 | 配線基板及びその製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20090084585A1 (ja) |
JP (1) | JP5025399B2 (ja) |
KR (1) | KR20090033004A (ja) |
CN (2) | CN101399248B (ja) |
TW (1) | TW200921874A (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI557855B (zh) * | 2011-12-30 | 2016-11-11 | 旭德科技股份有限公司 | 封裝載板及其製作方法 |
CN103379726A (zh) * | 2012-04-17 | 2013-10-30 | 景硕科技股份有限公司 | 线路积层板的复层线路结构 |
KR101369150B1 (ko) * | 2013-10-15 | 2014-03-04 | 주식회사 에스아이 플렉스 | 단차 지그를 이용한 인쇄공법 |
JP6151461B2 (ja) * | 2014-09-27 | 2017-06-21 | インテル コーポレイション | 単一方向の加熱を用いる強化ガラスを使用する基板の反り制御 |
US11081371B2 (en) * | 2016-08-29 | 2021-08-03 | Via Alliance Semiconductor Co., Ltd. | Chip package process |
JP6693850B2 (ja) * | 2016-09-30 | 2020-05-13 | 新光電気工業株式会社 | キャリア基材付き配線基板、キャリア基材付き配線基板の製造方法 |
US11778293B2 (en) | 2019-09-02 | 2023-10-03 | Canon Kabushiki Kaisha | Mounting substrate to which image sensor is mounted, sensor package and manufacturing method thereof |
CN113131291B (zh) * | 2021-03-11 | 2023-05-12 | 东莞市晟合科技有限公司 | 一种搭载电子元器件的连接线及其制作方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3635219B2 (ja) * | 1999-03-11 | 2005-04-06 | 新光電気工業株式会社 | 半導体装置用多層基板及びその製造方法 |
CN101232776B (zh) * | 1999-09-02 | 2011-04-20 | 揖斐电株式会社 | 印刷布线板 |
JP3492348B2 (ja) * | 2001-12-26 | 2004-02-03 | 新光電気工業株式会社 | 半導体装置用パッケージの製造方法 |
US7795714B2 (en) * | 2004-08-06 | 2010-09-14 | Supertalent Electronics, Inc. | Two step molding process secured digital card manufacturing method and apparatus |
JP2006179606A (ja) * | 2004-12-21 | 2006-07-06 | Nitto Denko Corp | 配線回路基板 |
JP3914239B2 (ja) * | 2005-03-15 | 2007-05-16 | 新光電気工業株式会社 | 配線基板および配線基板の製造方法 |
JP4526983B2 (ja) * | 2005-03-15 | 2010-08-18 | 新光電気工業株式会社 | 配線基板の製造方法 |
JP4619214B2 (ja) * | 2005-07-04 | 2011-01-26 | 日東電工株式会社 | 配線回路基板 |
CN1925148A (zh) * | 2005-08-29 | 2007-03-07 | 新光电气工业株式会社 | 多层配线基板及其制造方法 |
JP4452222B2 (ja) * | 2005-09-07 | 2010-04-21 | 新光電気工業株式会社 | 多層配線基板及びその製造方法 |
-
2007
- 2007-09-27 JP JP2007250807A patent/JP5025399B2/ja not_active Expired - Fee Related
-
2008
- 2008-09-17 KR KR1020080090916A patent/KR20090033004A/ko not_active Application Discontinuation
- 2008-09-23 US US12/236,118 patent/US20090084585A1/en not_active Abandoned
- 2008-09-26 TW TW097137221A patent/TW200921874A/zh unknown
- 2008-09-27 CN CN2008101488407A patent/CN101399248B/zh not_active Expired - Fee Related
- 2008-09-27 CN CN2011102042880A patent/CN102280435A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
JP2009081358A (ja) | 2009-04-16 |
US20090084585A1 (en) | 2009-04-02 |
CN101399248B (zh) | 2011-12-28 |
TW200921874A (en) | 2009-05-16 |
KR20090033004A (ko) | 2009-04-01 |
CN101399248A (zh) | 2009-04-01 |
CN102280435A (zh) | 2011-12-14 |
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