JP5017826B2 - Display panel and driving method thereof - Google Patents

Description

The present invention relates to a display panel and a driving how using light emitting elements which self-emits light when a current flows.

  There is an organic electroluminescence display panel as a display panel using a light emitting element. Organic electroluminescence display panels can be broadly classified into passive drive type and active matrix drive type. Active matrix drive type organic electroluminescence display panels are passive in terms of high contrast and high definition. It is superior to the drive system. For example, in the conventional active matrix driving type organic electroluminescence display panel described in Patent Document 1, an organic electroluminescence element (hereinafter referred to as an organic EL element) and a voltage signal corresponding to image data are applied to the gate. In addition, a driving transistor that supplies current to the organic EL element and a switching transistor that performs switching for supplying a voltage signal corresponding to image data to the gate of the driving transistor are provided for each pixel. In this organic electroluminescence display panel, when a scanning line is selected, the switching transistor is turned on. At that time, a voltage representing a luminance is applied to the gate of the driving transistor via the signal line. As a result, the drive transistor is turned on, and a drive current having a magnitude corresponding to the level of the gate voltage flows from the power source to the organic EL element via the source-drain of the drive transistor, and the organic EL element corresponds to the magnitude of the current. Emits light with high brightness. From the end of the selection of the scanning line to the next selection of the scanning line, even if the switching transistor is turned off, the level of the gate voltage of the driving transistor is kept, and the organic EL element becomes the voltage. Light is emitted at a luminance according to the magnitude of the corresponding drive current.

  In order to drive an organic electroluminescence display panel, a drive circuit is provided around the organic electroluminescence display panel, and a voltage is applied to scanning lines, signal lines, power supply lines, etc. laid on the organic electroluminescence display panel. It has been broken.

In addition, in a conventional active matrix driving type organic electroluminescence display panel, a wiring such as a power supply line for supplying a current to an organic EL element is formed simultaneously with a thin film transistor patterning process using a thin film transistor material such as a switching transistor and a driving transistor. Patterned. That is, in manufacturing an organic electroluminescence display panel, a thin film transistor electrode is shaped from the conductive thin film by performing a photolithography method and an etching method on the conductive thin film that is the source of the thin film transistor electrode. At the same time, the wiring connected to the electrode is processed. Therefore, when the wiring is formed from a conductive thin film, the wiring has the same thickness as the electrode of the thin film transistor.
JP-A-8-330600

  However, since the electrode of the thin film transistor is designed on the assumption that it functions as a transistor, in other words, since it is not designed on the assumption that a current flows through the light emitting element, it is a thin film as the name implies. When an electric current is caused to flow from the wiring to the plurality of light emitting elements, a voltage drop occurs due to the electric resistance of the wiring, or a delay of the current flow through the wiring occurs. In order to suppress the voltage drop and current delay, it is desirable to reduce the resistance of the wiring. For this purpose, the metal layer serving as the source and drain of the transistor or the metal layer serving as the gate is made thick, or the current is sufficient in these metal layers. If it is patterned to be so wide that it flows to a low resistance wiring, the area where the wiring overlaps with other wiring and conductors in plan view increases, and parasitic capacitance occurs between them, A factor that slows down the flow of current has occurred. In particular, in the case of a so-called bottom emission structure in which EL light is emitted from the transistor array substrate side, the wiring blocks light emitted from the EL element, resulting in a decrease in aperture ratio, which is a ratio of the light emitting area. Further, when the gate of the thin film transistor is made thicker in order to reduce the resistance, it is necessary to increase the thickness to a flattening film (for example, corresponding to a gate insulating film when the thin film transistor has an inverted staggered structure) for flattening the step of the gate, The transistor characteristics may change greatly, and if the source and drain are made thicker, the etching accuracy of the source and drain is lowered, which may also adversely affect the characteristics of the transistor.

  Accordingly, an object of the present invention is to suppress voltage drop and signal delay without impairing display characteristics.

In order to solve the above problems, the display panel of the present invention is
A substrate,
A plurality of driving transistors arranged in a matrix on the substrate;
A plurality of signal lines patterned with one of drain / source and gate of the plurality of driving transistors and arranged parallel to each other on the substrate;
A protective insulating film covering the plurality of signal lines and the plurality of driving transistors;
A plurality of pixel electrodes that are electrically connected to one of a source and a drain of each of the plurality of driving transistors and are formed on the protective insulating film;
A plurality of light emitting layers formed on each of the plurality of pixel electrodes;
A counter electrode provided on the plurality of light emitting layers;
It formed on the protective insulating film so as to be parallel to the signal line, and the protection plurality of feed lines that respectively conducted to the other of the source and the drain of said plurality of driving transistors through contact holes formed in the insulating film ,
A plurality of common wires formed on the protective insulating film, electrically connected to the counter electrode, applied with a common voltage, and alternately arranged with the plurality of power supply wires ;
The plurality of light emitting layers are disposed between the power supply wiring and the common wiring, and are formed of an organic compound-containing liquid partitioned into the power supply wiring and the common wiring .

A driving method of the present invention is a driving method for driving the display panel,
The display panel is
Scanning lines;
A holding transistor having a drain connected to the supply line, a source connected to the gate of the drive transistor, and a gate connected to the scan line;
A switch transistor having a drain connected to each of one of the source and drain of the plurality of drive transistors, a source connected to each of the plurality of signal lines, and a gate connected to the scan line;
A transmission circuit for transmitting a clock signal;
With
The oscillation circuit outputs a clock signal to the power supply wiring.

  According to the present invention, the power supply wiring for supplying current to the light emitting layer through the driving transistor is formed separately from the drain, source, and gate of the driving transistor. Therefore, the power supply wiring can be made thick without increasing the width of the power supply wiring, and the resistance of the power supply wiring can be reduced.

The plurality of power supply wirings are electrically connected to each other.

Preferably, in the display panel, the light emitting layer is formed continuously with a plurality of the pixel electrodes along the power supply wiring.

  According to the present invention, since the power supply wiring can be thickened, the resistance of the power supply wiring can be reduced.

  The best mode for carrying out the present invention will be described below with reference to the drawings. However, although various technically preferable limitations for implementing the present invention are given to the embodiments described below, the scope of the invention is not limited to the following embodiments and illustrated examples. Further, in the following description, the term electroluminescence is abbreviated as EL.

[First Embodiment]
[Overall structure of EL display panel]
FIG. 1 shows a schematic diagram of an EL display panel 1 of an active matrix driving system. As shown in FIG. 1, the EL display panel 1 includes a flexible sheet-like or rigid plate-like insulating substrate 2 having optical transparency and n pieces arranged on the insulating substrate 2 so as to be parallel to each other. (plural) signal lines Y ₁ to Y _n and, m the arranged on the insulating substrate 2 as orthogonal to the signal lines Y ₁ to Y _n by the insulating substrate 2 and a plan view of the (plural) and scan lines X ₁ to X _m, a scan line X ₁ to X respectively scan lines X ₁ between the to X _m parallel and staggered with so as m lines arranged on an insulating substrate 2 _m of (plural) (M × n) group of pixel circuits P arranged on the insulating substrate 2 so as to form a matrix along the supply lines Z _{1 to} Z _m , the signal lines Y _{1 to} Y _n and the scanning lines X _{1 to} X _{m. 1, 1 to} P _{m, n} and connected to the supply lines Z _{1 to} Z _m and divided into a plurality so as to be parallel to the signal lines Y _{1 to} Y _{n in} plan view. .., And common wires 91, 91,... Provided alternately and parallel to the power supply wires 90, 90,... Between the power supply wires 90, 90,. Is provided.

The sum of the total number of power supply wirings 90, 90,... And the total number of common wirings 91, 91,... Is (n + 1), and each pixel circuit P _{1, with} respect to the extending direction of the signal lines Y _{1 to} Y _{n .} Either one of the power supply wiring 90 or the common wiring 91 is provided so as to partition the left and right sides of _{1 to} P _{m, n} .

  Since the power supply wirings 90, 90,... Are electrically connected to each other by the routing wiring 90a disposed on one peripheral edge of the insulating substrate 2, they are equipotential by an external clock signal, as will be described later. Furthermore, the routing wiring 90a is connected to the wiring terminals 90b and 90c at both ends of the insulating substrate 2, respectively. Since the voltages applied from the external drive circuit to the wiring terminals 90b and 90c are both equipotential, current can be supplied to the entire power supply wiring 90, 90,. As will be described later, the lead-out wiring 90a functions as a metal partition that partitions the organic EL layer 20b together with the power supply wiring 90 and the common wiring 91 during film formation.

  The common wires 91, 91,... Are connected to each other by a lead wire 91a disposed on the periphery opposite to the periphery on which the wire 90a of the insulating substrate 2 is provided, and a common voltage Vcom is applied. As will be described later, the lead wiring 91a functions as a metal partition that partitions the organic EL layer 20b together with the power supply wiring 90 and the common wiring 91 during film formation.

Hereinafter, the extending direction of the signal lines Y _{1 to} Y _n is referred to as a vertical direction (column direction), and the extending direction of the scanning lines X _{1 to} X _m is referred to as a horizontal direction (row direction). Further, m and n are natural numbers of 2 or more, the numbers subscripted to the scanning line X represent the arrangement order from the top in FIG. 1, and the numbers subscripted to the supply line Z are the arrangement order from the top in FIG. 1, the number subscripted to the signal line Y represents the arrangement order from the left in FIG. 1, the front side of the number subscripted to the pixel circuit P represents the arrangement order from the top, and the rear side represents the arrangement order from the left. To express. That is, when an arbitrary natural number of 1 to m is i and an arbitrary natural number of 1 to n is j, the scanning line X _i is the i-th row from the top, and the supply line Z _i is the left To the i-th row, the signal line Y _j is the j-th column from the left, the pixel circuit P _{i, j} is the i-th row from the top, the j-th column from the left, and the pixel circuit P _{i, j} is the scanning line. It is connected to X _i , supply line Z _i and signal line Y _j .

In this EL display panel 1, each region partitioned in a matrix by scanning lines X _{1 to} X _m and signal lines Y _{1 to} Y _n constitutes a pixel, and pixel circuits P _{1,1 to} P _m, Only one group of _n is provided per region.

[Circuit configuration of pixel circuit]
Since any of the pixel circuits P _{1,1 to} P _{m, n} has the same configuration _, an arbitrary pixel circuit P _{i, j} among the pixel circuits P _1,1 to P _{m, n} will be described. FIG. 2 is an equivalent circuit diagram of the pixel circuit P _{i, j} , and FIG. 3 is a plan view mainly showing the electrodes of the pixel circuit P _{i, j} and the pixel circuit P _{i, j + 1} .

The pixel circuit P _{i, j} includes an organic EL element 20 as a pixel, three N-channel thin film transistors (hereinafter simply referred to as transistors) 21, 22, and 23 disposed around the organic EL element 20, And a capacitor 24. Hereinafter, the transistor 21 is referred to as a switch transistor 21, the transistor 22 is referred to as a holding transistor 22, and the transistor 23 is referred to as a drive transistor 23.

As shown in FIG. 2, in the pixel circuit P _{i, j} , in the switch transistor 21, the source 21s is conducted to the signal line _Yj , the drain 21d is the pixel electrode 20a of the organic EL element 20, and the source 23s of the drive transistor 23. And one electrode 24B of the capacitor 24 is conducted, and the gate 21g is conducted to the scanning line X _i and the gate 22g of the holding transistor 22.

In the holding transistor 22, the source 22s is electrically connected to the gate 23g of the driving transistor 23 and the other electrode 24A of the capacitor 24, the drain 22d is electrically connected to the supply line Z _i and the drain 23d of the driving transistor 23, and the gate 22g is the switch transistor. It is electrically connected to the gate 21g and the scan line X _i of 21.

In the driving transistor 23, the source 23 s is connected to the pixel electrode 20 a of the organic EL element 20, the drain 21 d of the switch transistor 21 and the electrode 24 B of the capacitor 24, and the drain 23 d is connected to the supply line Z _i and the drain 22 d of the holding transistor 22. The gate 23g is electrically connected to the source 22s of the holding transistor 22 and the electrode 24A of the capacitor 24.

Note that when only the switch transistors 21 of the pixel circuits P _{1,1 to} P _{m, n} are focused on the EL display panel 1 in plan view, the plurality of switch transistors 21 are arranged in a matrix on the insulating substrate 2 and are planar. When attention is paid only to the holding transistors 22 of the pixel circuits P _{1,1 to} P _{m, n} as viewed, a plurality of holding transistors 22 are arranged in a matrix on the insulating substrate 2, and the pixel circuits P _{1,1 are} viewed in plan view. Focusing only on the drive transistors 23 of ~ P _{m, n} , a plurality of drive transistors 23 are arranged in a matrix on the insulating substrate 2.

[Layer structure of EL display panel]
The layer structure of the EL display panel 1 will be described. First, the layer structure of the transistors 21 to 23 will be described.

  FIG. 4 is a cross-sectional view of the drive transistor 23. As shown in FIG. 4, the drive transistor 23 includes a gate 23g formed on the insulating substrate 2, a gate insulating film 31 formed on the gate 23g, and a semiconductor film 23c formed on the gate insulating film 31. A channel protective film 23p formed on the central portion of the semiconductor film 23c, and impurity semiconductor films 23a and 23b formed on both ends of the semiconductor film 23c so as to be separated from each other and partially overlapping the channel protective film 23p; The drain 23d is formed on the impurity semiconductor film 23a and the source 23s is formed on the impurity semiconductor film 23b. Note that the drain 23d and the source 23s may have a single-layer structure or a stacked structure of two or more layers.

  Since the switch transistor 21 and the holding transistor 22 have the same layer structure as that of the driving transistor 23, their sectional views are omitted.

Then, each signal line Y ₁ to Y _n of the transistors 21 to 23 and the capacitor 24, the relationship between the scanning lines X ₁ to X _m and the supply lines Z ₁ to Z _m will be described with reference to FIGS. 4 to 6 . 5 is a cross-sectional view taken along the line V-V shown in FIG. 3 in the thickness direction of the insulating substrate 2, and FIG. 6 is a cross-sectional view taken along the line VI-VI shown in FIG. It is arrow sectional drawing cut | disconnected in the thickness direction of the insulated substrate 2 along the line.

4 to 6, the gate 21g of the switch transistor 21, the gate 22g of the holding transistor 22, the gate 23g of the driving transistor 23, the electrode 24A of the capacitor 24, and the signal lines Y _{1 to} Y _n are on the insulating substrate 2. The conductive film formed on the entire surface is patterned by photolithography and etching. The signal lines Y _{1 to} Y _n are wirings through which a gradation current signal having a current value corresponding to the display gradation flows.

The gate insulating film 31 is a film common to all the switch transistor 21, the holding transistor 22, and the driving transistor 23, and is formed on the entire surface in the plane. The gate insulating film 31, a dielectric interposed between the electrode 24A and the electrode 24B of the capacitor 24 also serves as, also covers further signal lines Y ₁ to Y _n. A protective film 34 is formed on the signal lines Y _{1 to} Y _n by patterning a film that is a base of the semiconductor film 23c. On the protective film 34, a film that is a base of the impurity semiconductor films 23a and 23b is patterned. A protective film 35 is formed. Protective film 34 and the protective film 35, when the pin holes had been formed on the gate insulating film 31, and the signal lines Y ₁ to Y _n through the pinhole, any one of the scanning lines X ₁ to X _m or The supply line Z _{1 to} Z _m is protected from short circuit.

Drain 21d · sources 21s of the switch transistors 21, the drain 22 d · source 22s of the holding transistor 22, the electrode 24B of the drain 23d · source 23s and the capacitor 24 of the driving transistor 23 and the scanning lines X ₁ to X _m and the supply lines Z ₁ to Z _m is obtained by patterning a conductive film formed on the entire surface of the gate insulating film 31 by a photolithography method or an etching method. As shown in FIG. 3, the scanning line X _i is connected to the gate 21g of the switch transistor 21 and the gate 22g of the holding transistor 22 through a contact hole 92 formed in the gate insulating film 31. The signal line Y _j is conducted to the source 21s of the switch transistor 21 through the contact hole 94 formed in the gate insulating film 31, and the source 22s of the holding transistor 22 is formed in the gate insulating film 31. The contact portion 93 is electrically connected to the contact portion C3 connected to the gate 23g of the driving transistor 23 through the contact hole 93.

As shown in FIGS. 4 to 6, the switch transistor 21, the holding transistor 22, the drive transistor 23, the scanning lines X _{1 to} X _m, and the supply lines Z _{1 to} Z _m are formed on the protective insulating film 32 formed on the entire surface. It is covered by. Protective insulating film 32 is made of silicon nitride or silicon oxide, the transistors 21 to 23, the scan lines X ₁ to X _m and the supply lines Z ₁ to Z _m are insulating protection.

Over the protective insulating film 32 is planarized film 33 is laminated, the switch transistor 21, holding transistor 22 and driving transistor 23 and the scanning lines X ₁ to X _m and irregularities planarizing film by the supply lines Z ₁ to Z _m 33 has been solved. That is, the surface of the planarizing film 33 is flat. The planarizing film 33 is obtained by curing a resin such as polyimide.

  A stacked structure from the insulating substrate 2 to the planarizing film 33 is referred to as a transistor array substrate 50. In the transistor array substrate 50, the switch transistor 21, the holding transistor 22, and the driving transistor 23 are arranged in a matrix in a plan view.

  When the EL display panel 1 is used as a bottom emission type, that is, when the light of the organic EL element 20 is emitted from the insulating substrate 2 and the insulating substrate 2 is used as a display surface, the gate insulating film 31 and the protective insulation are used. A transparent material is used for the film 32 and the planarizing film 33.

Next, the layer structure laminated on the surface of the transistor array substrate 50 will be described. On the surface of the transistor array substrate 50, that is, on the surface of the planarizing film 33, the pixel electrodes 20a are arranged in a matrix for each of the pixel circuits P _{1,1 to} P _{m, n} . In plan view _, the pixel electrode 20a of the pixel circuit P _{i, j} is formed in a region partitioned by the adjacent scanning line X _i and supply line Z _i, and the adjacent signal line Y _j and signal line Y _{j + 1} . ing. The pixel electrode 20a is electrically connected to the electrode 24B of the capacitor 24, the drain 21d of the switch transistor 21 and the source 23s of the drive transistor 23 through contact holes formed in the planarizing film 33 and the protective insulating film 32.

The pixel electrode 20 a is an electrode that functions as an anode of the organic EL element 20. That is, it is preferable that the pixel electrode 20a has a relatively high work function and efficiently injects holes into the organic EL layer 20b described later. The pixel electrode 20a is transmissive to visible light. Examples of the pixel electrode 20a include tin-doped indium oxide (ITO), zinc-doped indium oxide, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), or cadmium-tin oxide (CTO). ).

  When this EL display panel 1 is used as a top emission type, that is, when the opposite side of the insulating substrate 2 is used as a display surface, conductive and visible light is interposed between the pixel electrode 20a and the planarizing film 33. A reflective film having high reflectivity is preferably formed.

These pixel electrodes 20a are obtained by patterning a transparent conductive film formed on the entire surface of the planarizing film 33 by a photolithography method or an etching method. Between the pixel electrodes 20a adjacent to each other in the horizontal direction, conductive lines 51 that are electrically separated from the pixel electrodes 20a and extend in the vertical direction are connected to the signal lines Y _(j-2k) ,..., Y _{(j− 2)} , Y _j , Y _{(j + 2)} ,... (K is a natural number), that is, similarly to the power supply wiring 90, they are patterned every other row. The conductive line 51 is patterned together with the pixel electrode 20a by etching the transparent conductive film that is the source of the pixel electrode 20a. On the peripheral edges of the left and right sides of the conductive line 51, groove-like insulating lines 57, 57,... That are long in the vertical direction are formed. On the conductive line 51 exposed between the insulating lines 57, 57, power supply wirings 90, 90,.

Between the pixel electrodes 20a adjacent in the horizontal direction, insulating lines 52 that are electrically insulated from the pixel electrodes 20a and extend in the vertical direction are signal lines Y _{(j-2k + 1)} ... Y _{(j− 1)} , Y _{(j + 1)} , Y _{(j + 3)} ,... (K is a natural number), that is, like the common wiring 91, the pixel electrodes 20a are patterned every other column. In order to increase the aperture ratio, these insulating lines 52 are provided so that both sides thereof partially overlap with the peripheral edge of the pixel electrode 20a, but may have a structure that does not overlap with the peripheral edge of the pixel electrode 20a. A common wiring 91 is laminated on the insulating line 52 that does not overlap the conductive line 51 among these insulating lines 52. The insulating line 52 and the insulating line 57 are preferably made of silicon nitride or silicon oxide.

The power supply wiring 90 is sufficiently thicker than the insulating line 52 and protrudes from the insulating line 52. Further, since the power supply wiring 90 is formed by plating, the signal lines Y _{1 to} Y _n , the scanning lines X _{1 to} X _m and the supply lines Z _{1 to} Z _{m and} the gates and sources of the transistors 21 to 23 are used. And sufficiently thicker than the drain. As shown in FIGS. 3 and 6, a contact hole 53 is formed in the planarization film 33 and the protective insulating film 32 at a location where each power supply wiring 90 and the supply lines Z _{1 to} Z _m intersect in plan view. A conductive pad 58 is buried in the contact hole 53, and the conductive line 51 and the power supply wiring 90 overlap with the conductive pad 58 in this order. Therefore, as shown in the circuit diagram of FIG. 2, the power supply wiring 90 is electrically connected to the supply lines Z _{1 to} Z _m at the contact portion C2, and the pixel circuits Z _{i, 1} to are connected via the supply line Z _i. The transistors 22 and 23 of Z _{i, n} are electrically connected to the drains 22d and 23d. The conductive pad 58 in the contact hole 53 is formed by a plating method.

Common interconnection 91 is also because together with the feed lines 90 is one formed by plating, the gate signal lines Y ₁ to Y _n, the scanning lines X ₁ to X _m and the supply lines Z ₁ to Z _m and transistors 21 to 23 It is thicker than the source and drain. The common wiring 91 and the power supply wiring 90 are made of copper, gold, nickel, or a laminate thereof.

  A liquid repellent insulating film 54 having water and oil repellency is formed on the surface of the power supply wiring 90. The liquid repellent insulating film 54 is made of a fluororesin electrodeposition coating and is formed by electrodeposition coating.

  A liquid repellent conductive film 55 having water repellency and oil repellency is formed on the surface of the common wiring 91. In the liquid repellent conductive film 55, the hydrogen atom (H) of one or two thiol groups (-SH: sometimes referred to as a mercapto group) of triazyltrithiol represented by the following chemical formula is reduced and released. The sulfur atoms (S) are oxidized and adsorbed on the surface of the common wiring 91 made of metal.

The liquid-repellent conductive film 55 is a monomolecular film that is planarly coated on the surface of the common wiring 91 and arranged with a monomolecular thickness in the thickness direction of the common wiring 91, or the surface of the common wiring 91. Are a plurality of molecular films that are planarly coated and arranged with a very small number of molecules in the thickness direction of the common wiring 91. That is, since the liquid repellent conductive film 55 is an extremely thin film in which triazyltrithiol molecular units are regularly arranged on the surface of the common wiring 91, the liquid repellent conductive film 55 has a very low resistance and its thickness. There is no loss of electrical conductivity in the direction. For this reason, the common wiring 91 can be electrically connected to the counter electrode 20 c described later via the liquid repellent conductive film 55. In order to make the water repellency and oil repellency remarkable, a triazine thiol derivative in which one or two thiol groups of triazyl trithiol are substituted with a fluorinated alkyl group may be used instead of triazyl trithiol. Such a triazyl compound can be selectively coated and bonded to a metal such as the liquid repellent conductive film 55. Specifically, after adjusting 6-dimethylamino-1,3,5-triazine-2,4-dithiol-sodium salt to a concentration of 10 ⁻³ mol / l aqueous solution, the liquid temperature is 26 ° C. and the immersion time is 5 minutes to When the common wiring 91 is immersed in the aqueous solution under the condition of 30 minutes, a liquid repellent conductive film 55 having a film thickness of about 0.7 nm is coated on the surface of the common wiring 91 made of copper (the film thickness is an ellipsometer). Measured value). In addition, after adjusting 6-didodecylamino-1,3,5-triazine-2,4-dithiol-sodium salt to a concentration of 10 ⁻³ mol / l aqueous solution, the liquid temperature is 46 ° C. and the immersion time is 5 minutes to 30 minutes. When the common wiring 91 whose surface is made of copper is immersed in the aqueous solution under the above conditions, a liquid repellent conductive film 55 having a film thickness of about 1.8 nm is coated on the common wiring 91 (the film thickness is a value measured by an ellipsometer). .

なお、撥液性導通膜５５の被膜構造を模式的に示すと、図７のようになる。図７において置換基Ｒは、例えばジメチルアミノ又はジドデシルアミノである。 When a triazylthiol compound having a fluorinated alkyl group represented by the following chemical formula is used, specifically, it is dissolved in water together with sodium hydroxide to form a 2 × 10 ⁻³ mol / l aqueous solution, and the liquid temperature The common wiring 91 whose surface is made of copper is immersed in the aqueous solution under the conditions of 26 ° C. and immersion time of 5 minutes to 30 minutes, and the liquid repellent conductive film 55 is coated on the common wiring 91.

The film structure of the liquid repellent conductive film 55 is schematically shown in FIG. In FIG. 7, the substituent R is, for example, dimethylamino or didodecylamino.

  The pixel electrode 20a is subjected to a lyophilic process using ultraviolet rays immediately before the liquid repellent conductive film 55 is coated on the surface of the common wiring 91. When the liquid is applied to the surface of the pixel electrode 20a that has been subjected to the lyophilic process, the contact angle of the liquid is low, and the liquid is applied smoothly to the surface. Ultraviolet irradiation was performed with an ultraviolet irradiation device (HMW-615-N-4 manufactured by Oak Seisakusho) with a lamp output of 100 W and an irradiation time of 15 seconds to 3 minutes. By irradiating ultraviolet rays toward the surface of the transistor array panel 50, particularly toward the pixel electrode 20a, the wettability of the surface of the pixel electrode 20a is improved to make the pixel electrode 20a lyophilic. Alternatively, ozone treatment may be performed on the pixel electrode 20a to make it hydrophilic. An organic EL layer 20b of the organic EL element 20 is formed on the pixel electrode 20a. The organic EL layer 20b is a light-emitting layer in a broad sense, and the organic EL layer 20b contains a light-emitting material (phosphor) that is an organic compound. The organic EL layer 20b has a two-layer structure in which a hole transport layer and a narrowly-defined light emitting layer are sequentially stacked from the pixel electrode 20a. The hole transport layer is made of PEDOT (polythiophene) which is a conductive polymer and PSS (polystyrene sulfonic acid) which is a dopant, and the light-emitting layer in a narrow sense is made of a polyfluorene-based light-emitting material. A charge transport layer made of an inorganic material may be combined with the organic EL layer 20b.

  The organic EL layer 20b is formed by a wet application method (for example, an ink jet method) after coating the liquid repellent insulating film 54 and the liquid repellent conductive film 55. The wet coating method is a method in which a solution obtained by dissolving or dispersing an organic compound to be the organic EL layer 20b in a solvent or the like is applied, or the organic compound itself to be the organic EL layer 20b is applied in a liquid state. . In this case, an organic compound-containing liquid containing an organic compound that becomes the organic EL layer 20b is applied to the pixel electrode 20a. The liquid level of the organic compound-containing liquid is the top of the insulating line 52 and the top of the insulating line 57. Higher than. Since the top portions of the insulating lines 52 and the thick portions of the power supply wirings 90 and the common wirings 91 which are sufficiently higher than the top portions of the insulating lines 57 are alternately provided between the pixel electrodes 20a adjacent in the horizontal direction, the pixels The organic compound-containing liquid applied to the electrode 20a is dammed so as not to leak to the adjacent pixel electrode 20a with respect to the horizontal direction. Further, the pixel electrode 20a is made lyophilic, the power supply wiring 90 is coated with a water-repellent / oil-repellent liquid-repellent insulating film 54, and the common wiring 91 is coated with a water-repellent / oil-repellent liquid-repellent conductive film 55. Is coated, the organic compound-containing liquid containing an organic compound that becomes the organic EL layer 20b applied to the pixel electrode 20a spreads over the entire surface of the pixel electrode 20a, and the liquid-repellent insulating film 54 and the liquid-repellent conductive film Therefore, the organic compound-containing liquid applied to the pixel electrode 20a is not deposited extremely thick near the corner of the insulating line 52 with respect to the center of the pixel electrode 20a. Therefore, the organic EL layer 20b formed by drying the organic compound-containing liquid can be formed with a uniform film thickness.

  By forming the organic EL layer 20b in this way, as shown in FIG. 8, the region R where the organic EL layer 20b emitting red light was formed and the organic EL layer 20b emitting green light were formed. The stripe structure of the area | region B in which the organic electroluminescent layer 20b light-emitted in the area | region G and blue is formed is comprised, and the several pixel of the row | line | column light-emits the same color.

  When viewed in plan, the applied organic compound-containing liquid is uniformly distributed in each column in the vertical direction because the left and right are partitioned into either the power supply wiring 90 or the common wiring 91, respectively. The plurality of arranged organic EL layers 20b all have the same layer structure and emit light in the same color. On the other hand, in the plurality of organic EL layers 20b arranged in a line in the horizontal direction, light emitting layers in a narrow sense are arranged so as to repeat red light emission, green light emission, and blue light emission in this order. For the hole transport layer, the same material may be used for pixels emitting light of different colors.

  In addition to the two-layer structure, the organic EL layer 20b may have a three-layer structure that becomes a hole transport layer, a light-emitting layer in a narrow sense, and an electron transport layer in order from the pixel electrode 20a. It may be a single layer structure, a laminated structure in which an electron or hole injection layer is interposed between appropriate layers in these layer structures, or another laminated structure.

  On the organic EL layer 20b, a counter electrode 20c that functions as a cathode of the organic EL element 20 is formed. The counter electrode 20c is a common electrode formed in common for all pixels. Since the counter electrode 20c is formed on the entire surface, the counter electrode 20c covers the common wiring 91 with the liquid repellent conductive film 55 interposed therebetween, and also covers the power supply wiring 90 with the liquid repellent insulating film 54 interposed therebetween. Yes. Therefore, as shown in the circuit diagram of FIG. 2, the counter electrode 20 c is electrically connected to the common wiring 91. On the other hand, the counter electrode 20 c is insulated from the power supply wiring 90.

  As shown in FIGS. 4 to 6, the counter electrode 20c is made of a material having a work function lower than that of the pixel electrode 20a, and includes, for example, at least one of magnesium, calcium, lithium, barium, indium, and a rare earth metal. It is preferably formed of a low work function material having a simple substance or an alloy. Further, the counter electrode 20c may have a laminated structure in which layers of the above various materials are laminated, and in addition to the above layers of various materials, a metal layer that is not easily oxidized is deposited in order to reduce sheet resistance. Specifically, it may have a laminated structure. Specifically, a low-work function high-purity barium layer provided on the interface side in contact with the organic EL layer 20b, and an aluminum layer provided so as to cover the barium layer; And a laminated structure in which a lithium layer is provided in the lower layer and an aluminum layer is provided in the upper layer. In the case of a top emission structure, the counter electrode 20c may be a transparent electrode in which a thin film having a low work function as described above and a transparent conductive film such as ITO are laminated thereon.

  A sealing insulating film 56 is formed on the counter electrode 20c. The sealing insulating film 56 is an inorganic film or an organic film provided to cover the entire counter electrode 20c and prevent the counter electrode 20c from being deteriorated.

  Conventionally, in an EL display panel having a top emission type structure, a transparent electrode having a high resistance value such as a metal oxide is used for at least a part of the counter electrode. However, such a material must be sufficiently thick. If the sheet resistance is not sufficiently low, the transmittance of the organic EL element is inevitably lowered by increasing the thickness, and the larger the screen, the less uniform the potential in the plane, and the lower the display characteristics. . However, in the present embodiment, since a plurality of low resistance common wirings 91, 91,... Are provided for sufficient thickness in the vertical direction, the organic EL elements 20, 20,. The sheet resistance value of the entire cathode electrode can be lowered, and a large current can flow sufficiently and uniformly in the plane. Further, in such a structure, since the common wires 91, 91,... Reduce the sheet resistance as the cathode electrode, it is possible to improve the transmittance by using the counter electrode 20c as a thin film. In the top emission structure, the pixel electrode 20a may be a reflective material.

[Driving method of EL display panel]
The EL display panel 1 is driven by the active matrix method as follows. That is, as shown in FIG. 9, a clock signal is output to the power supply wirings 90, 90,... And the supply lines Z _{1 to} Z _m by the oscillation circuit. The scanning lines X ₁ to X _m by sequentially outputting the high-level shift pulse sequentially (the next scan line X _m scanning lines X ₁₎ from the scanning line X ₁ by a scanning-side driver to the scan line X _m Are sequentially selected, but when the scanning side driver outputs a shift pulse to any _{one of the} scanning lines X _{1 to} X _m , the clock signal of the oscillation circuit becomes low level. Further, when the scanning side driver selects each of the scanning lines X _{1 to} X _m , the data side driver applies a drawing current (current signal) as a writing current to all signals via the source and drain of the driving transistor 23. flowing through the line Y ₁ ~Y _n. Note that the common voltage Vcom (for example, ground = 0 volts) of the counter electrode 20c and the power supply wiring 90 is maintained.

In the selection period of the scan line X _i, from the shift pulse to the i-th scanning line X _i is output, the switch transistor 21 and holding transistor 22 are turned on. In each selection period, the potential on the data side driver side is equal to or lower than the low level of the clock signal output to the power supply wirings 90, 90,... And the supply lines Z _{1 to} Z _m , and the low level of this clock signal is the common voltage Vcom. It is set as follows. Therefore, at this time, since the organic EL element 20 does not flow to the signal lines Y _{1 to} Y _n , as shown in FIG. 2, a write current (drawing current) having a current value corresponding to the gradation is indicated by the data side driver. As shown in A, the signal flows to the signal lines Y _{1 to} Y _n , and in the pixel circuit P _{i, j} , the power supply wiring 90 and the supply line Z _i pass between the source and drain of the drive transistor 23 and between the source and drain of the switch transistor 21. Thus, a write current (drawing current) directed to the signal line Y _j flows. In this way, the current value of the current flowing between the source and drain of the drive transistor 23 is uniquely controlled by the data side driver, and the data side driver determines the write current (drawing current) according to the gradation input from the outside. ) Current value is set. While the write current (drawing current) is flowing, the voltage between the gate 23g and the source 23s of each driving transistor 23 of the _i- th row P _{i, 1 to} P _{i, n} is the signal line Y _{1 to} Y _n , respectively. Current value of the write current (extraction current) flowing through the transistor 23, that is, the current value of the write current (extraction current) flowing between the drain 23d and the source 23s of the drive transistor 23 regardless of the change with time in the Vg-Ids characteristic of the drive transistor 23. The capacitor 24 is forcibly set to meet the voltage level, the capacitor 24 is charged with a charge, and the current value of the write current (drawing current) is between the gate 23g and the source 23s of the drive transistor 23. Is converted to the voltage level. In the subsequent light emission period, the scanning line X _i becomes a low level, and the switch transistor 21 and the holding transistor 22 are turned off. However, the charge on the electrode 24A side of the capacitor 24 is confined by the holding transistor 22 in the off state and floats. Even when the voltage of the source 23s of the drive transistor 23 is modulated when the voltage shifts from the selection period to the light emission period, the potential difference between the gate 23g and the source 23s of the drive transistor 23 is maintained as it is. During this light emission period, during which the row is not a selection period, that is, the clock signal is high when the potential of the power supply wiring 90 and the supply line Z _i is higher than the potential Vcom of the counter electrode 20 c of the organic EL element 20 and the power supply wiring 90. During the level, the drive current flows in the direction of the arrow B from the higher potential power supply line 90 and the supply line Z _i to the organic EL element 20 through the source and drain of the drive transistor 23, and the organic EL element 20 emits light. . Since the current value of the drive current depends on the voltage between the gate 23g and the source 23s of the drive transistor 23, the current value of the drive current in the light emission period is equal to the current value of the write current (drawing current) in the selection period. Further, in the light emission period, during the selection period of any row, that is, when the clock signal is at a low level, the potential of the power supply wiring 90 and the supply line Z _i is equal to or lower than the potential Vcom of the counter electrode 20c and the power supply wiring 90. Therefore, no drive current flows through the organic EL element 20 and no light is emitted.

That is, during the selection period, the switch transistor 21 forms a current path so that a write current (extraction current) flows between the source 23s of the drive transistor 23 and the signal line _Yj, and the holding transistor 2 A current path is formed so that a write current (drawing current) flows between 90 and the drain 23 d of the driving transistor 23.

During the light emission period, the switch transistor 21 closes the current path so that the drive current flowing from the source 23 s of the drive transistor 23 does not flow to the signal line Y _j , and the holding transistor 22 has the gate 23 g-source 23 s of the drive transistor 23. The voltage between them is held to make the current value of the drive current constant. The driving transistor 23 has a magnitude corresponding to the gray level according to the charge charged between the gate 23g and the source 23s during the selection period when the supply line Z _i and the power supply wiring 90 become high level during the light emission period. This current is passed through the organic EL element 20 to drive the organic EL element 20.

[Width, cross-sectional area and resistivity of power supply wiring and common wiring]
Here, when the number of pixels of the EL display panel 1 is WXGA (768 × 1366), desirable widths and cross-sectional areas of the power supply wiring 90 and the common wiring 91 are defined. FIG. 10 is a graph showing current-voltage characteristics of the drive transistor 23 and the organic EL element 20 of each pixel circuit P _{1,1 to} P _{m, n} .

  In FIG. 10, the vertical axis represents the current value of the write current flowing between the source 23 s and the drain 23 d of one drive transistor 23 or the current value of the drive current flowing between the anode and cathode of one organic EL element 20. The axis is the voltage between the source 23s and the drain 23d of one drive transistor 23 (at the same time, the voltage between the gate 23g and the drain 23d of one drive transistor 23). In the figure, solid line Ids max is a write current and drive current at the maximum luminance gradation (brightest display), and alternate long and short dash line Ids mid is an intermediate luminance between the highest luminance gradation and the lowest luminance gradation. The two-dot chain line Vpo is a threshold value, that is, a pinch-off voltage between the unsaturated region (linear region) and the saturated region of the driving transistor 23, and the three-dot chain line Vds is the driving transistor 23. The write current flowing between the source 23 s and the drain 23 d of the organic EL element 20, and the broken line Iel is the drive current flowing between the anode and the cathode of the organic EL element 20.

  Here, the voltage VP1 is a pinch-off voltage of the driving transistor 23 at the maximum luminance gradation, and the voltage VP2 is a source-drain voltage when a writing current of the maximum luminance gradation flows through the driving transistor 23. VELmax (voltage VP4−voltage VP3) is a voltage between the anode and the cathode when the organic EL element 20 emits light with the driving current of the maximum luminance gradation whose current value is equal to the writing current of the maximum luminance gradation. The voltage VP2 ′ is a source-drain voltage when the driving transistor 23 receives an intermediate luminance gradation write current, and the voltage (voltage VP4′−voltage VP3 ′) is an organic EL element 20 having an intermediate luminance gradation. This is the anode-cathode voltage when light is emitted with a drive current of an intermediate luminance gradation whose current value is equal to the write current.

  In order to drive both the driving transistor 23 and the organic EL element 20 in the saturation region, a value VX obtained by subtracting (the voltage Vcom during the light emission period of the common wiring 91) from (the voltage VH during the light emission period of the power supply wiring 90) is The following formula (2) is satisfied.

      VX = Vpo + Vth + Vm + VEL (2)

  Vth (equal to VP2−VP1 at the maximum luminance) is a threshold voltage of the drive transistor 23, VEL (equal to VELmax at the maximum luminance) is an anode-cathode voltage of the organic EL element 20, and Vm is The allowable voltage is displaced according to the gradation.

  As is apparent from the figure, the higher the luminance gradation of the voltage VX, the higher the voltage (Vpo + Vth) required between the source and drain of the transistor 23 and the voltage VEL required between the anode and cathode of the organic EL element 20. Becomes higher. Therefore, the allowable voltage Vm becomes lower as the luminance gradation becomes higher, and the minimum allowable voltage Vmmin becomes VP3−VP2.

  The organic EL element 20 generally deteriorates with time regardless of the low-molecular EL material and the high-molecular EL material, and increases in resistance. It has been confirmed that the anode-cathode voltage after 10,000 hours is about 1.4 times the initial voltage. That is, the voltage VEL increases with time even at the same luminance gradation. For this reason, the higher the allowable voltage Vm at the beginning of driving, the more stable the operation over a long period of time. Therefore, the voltage VX is set so that the voltage VEL is 8V or higher, more preferably 13V or higher.

  This allowable voltage Vm includes not only the increase in resistance of the organic EL element 20 but also the voltage drop due to the power supply wiring 90.

  If the voltage drop is large due to the wiring resistance of the power supply wiring 90, the power consumption of the EL display panel 1 is remarkably increased. Therefore, the voltage drop of the power supply wiring 90 is particularly preferably set to 1V or less.

The pixel width Wp, which is the length of one pixel in the row direction, the number of pixels in the row direction (1366), the extended portion from the routing wiring 90a to the wiring terminal 90b outside the pixel region, and the routing wiring 90a outside the pixel region. As a result of considering the extended portion from the wiring terminal 90c to the wiring terminal 90c, when the panel size of the EL display panel 1 is 32 inches and 40 inches, the total length of the lead wiring 90a is 706.7 mm and 895.2 mm, respectively. Here, when the line width WL of the power supply wiring 90 and the line width WL of the common wiring 91 are widened, the area of the organic EL layer 20b is structurally reduced, and further, a parasitic capacitance with other wiring is generated, resulting in further voltage drop. Therefore, it is desirable to suppress the width WL of the power supply wiring 90 and the line width WL of the common wiring 91 to one fifth or less of the pixel width Wp. Considering this, when the panel size of the EL display panel 1 is 32 inches and 40 inches, the width WL is within 34 μm and within 44 μm, respectively. Further, the maximum film thickness Hmax of the power supply wiring 90 and the common wiring 91 is 1.5 times the minimum processing dimension 4 μm of the transistors 21 to 23, that is, 6 μm, in consideration of the aspect ratio. Thus the maximum cross-sectional area Smax of the feed interconnection 90 and common interconnection 91 is 32-inch 40-inch respectively 204Myuemu ^2, a 264μm ^2.

  In order to reduce the maximum voltage drop of the power supply wiring 90 and the common wiring 91 to 1 V or less when such a 32-inch EL display panel 1 is fully lit so that the maximum current flows, as shown in FIG. The wiring resistivity ρ / cross-sectional area S of each of the power supply wiring 90 and the common wiring 91 needs to be set to 4.7 Ω / cm or less. FIG. 12 shows the correlation between the cross-sectional area of each of the power supply wiring 90 and the common wiring 91 of the 32-inch EL display panel 1 and the current density. Note that the resistivity allowed at the time of the maximum cross-sectional area Smax of the power supply wiring 90 and the common wiring 91 is 9.6 μΩcm at 32 inches and 6.4 μΩcm at 40 inches.

  Then, for the 40-inch EL display panel 1, in order to set the maximum voltage drop of the power supply wiring 90 and the common wiring 91 to 1 V or less when fully lit so that the maximum current flows, as shown in FIG. The wiring resistivity ρ / cross-sectional area S of each of the power supply wiring 90 and the common wiring 91 needs to be set to 2.4 Ω / cm or less. FIG. 14 shows the correlation between the cross-sectional area of each of the power supply wiring 90 and the common wiring 91 of the 40-inch EL display panel 1 and the current density.

  The failure life MTF that does not operate due to the failure of the power supply wiring 90 and the common wiring 91 satisfies the following formula (3).

MTF = A exp (Ea / K _b T) / ρJ ² (3)

Ea is the activation energy, the resistivity of the ^{_{K b T = 8.617 × 10- 5}} eV, ρ is the feed interconnection 90 and common interconnection 91, J is the current density.

The failure lifetime MTF of the power supply wiring 90 and the common wiring 91 is limited by the increase in resistivity and electromigration. When the power supply wiring 90 and the common wiring 91 are set to Al (alloy such as AlTi and AlNd or Al alone) and the MTF is estimated at an operating temperature of 85 ° C. for 10,000 hours, the current density J is 2.1 × 10 ⁴ A. / Cm ² or less. Similarly, when the power supply wiring 90 and the common wiring 91 are set to Cu, the power supply wiring 90 and the common wiring 91 need to be 2.8 × 10 ⁶ A / cm ² or less. It is assumed that materials other than Al in the Al alloy have a lower resistivity than Al.

Considering these, in the 32-inch EL display panel 1, each of the Al-based power supply wiring 90 and the common wiring 91 is disconnected so that the power supply wiring 90 and the common wiring 91 do not break down in 10,000 hours in the fully lit state. The area S is required to be 57 μm ² or more from FIG. 12, and similarly, the cross-sectional areas S of the Cu power supply wiring 90 and the common wiring 91 are required to be 0.43 μm ² or more from FIG.

In the 40-inch EL display panel 1, the cross-sectional areas S of the Al-based power supply wiring 90 and the common wiring 91 so that the power supply wiring 90 and the common wiring 91 do not fail in 10,000 hours in the fully lit state are shown in FIG. 92 μm ² or more is required, and similarly, the cross-sectional areas S of the Cu power supply wiring 90 and the common wiring 91 are required to be 0.69 μm ² or more from FIG.

Assuming that the Al-based power supply wiring 90 and the common wiring 91 have an Al-based resistivity of 4.00 μΩcm, the 32-inch EL display panel 1 has a wiring resistivity ρ / cross-sectional area S of 4.7 Ω / cm as described above. Therefore, the minimum cross-sectional area Smin is 85.1 μm ² . At this time, since the wiring width WL of the power supply wiring 90 and the common wiring 91 is within 34 μm as described above, the minimum film thickness Hmin of the power supply wiring 90 and the common wiring 91 is 2.50 μm.

Further, in the 40-inch EL display panel 1 of the Al-based power supply wiring 90 and the common wiring 91, the wiring resistivity ρ / cross-sectional area S is 2.4Ω / cm or less as described above, so the minimum cross-sectional area Smin is 167 μm ^2. . At this time, since the wiring width WL of the power supply wiring 90 and the common wiring 91 is within 44 μm as described above, the minimum film thickness Hmin of the power supply wiring 90 and the common wiring 91 is 3.80 μm.

In the Cu power supply wiring 90 and the common wiring 91, if the Cu resistivity is 2.10 μΩcm, the wiring resistivity ρ / cross-sectional area S is 4.7 Ω / cm or less in the 32-inch EL display panel 1 as described above. The minimum cross-sectional area Smin is 44.7 μm ² . At this time, since the wiring width WL of the power supply wiring 90 and the common wiring 91 is within 34 μm as described above, the minimum film thickness Hmin of the power supply wiring 90 and the common wiring 91 is 1.31 μm.

Further, in the 40-inch EL display panel 1 of the Cu power supply wiring 90 and the common wiring 91, since the wiring resistivity ρ / cross-sectional area S is 2.4Ω / cm or less as described above, the minimum cross-sectional area Smin is 87.5 μm ² . Become. At this time, since the wiring width WL of the power supply wiring 90 and the common wiring 91 is within 44 μm as described above, the minimum film thickness Hmin of the power supply wiring 90 and the common wiring 91 is 1.99 μm.

  From the above, in order to operate the EL display panel 1 normally and with low power consumption, it is preferable to set the voltage drop in the power supply wiring 90 and the common wiring 91 to 1 V or less. In a panel of 32 inches in which the power supply wiring 90 and the common wiring 91 are Al-based, the film thickness H is 2.50 μm to 6 μm, the width WL is 14.1 μm to 34.0 μm, and the resistivity is 4.0 μΩcm to 9.6 μΩcm. In a 40-inch panel in which the power supply wiring 90 and the common wiring 91 are Al-based, when the power supply wiring 90 and the common wiring 91 are Al-based, the film thickness H is 3.80 μm to 6 μm and the width WL is 27.8 μm to 44.0 μm. The resistivity is 4.0 μΩcm to 9.6 μΩcm.

In general, in the case of the Al-based power supply wiring 90 and the common wiring 91, the film thickness H is 2.50 μm to 6 μm, the width WL is 14.1 μm to 44 μm, and the resistivity is 4.0 μΩcm to 9.6 μΩcm.
Similarly, in a 32-inch panel in which the power supply wiring 90 and the common wiring 91 are Cu, the film thickness H is 1.31 μm to 6 μm, the width WL is 7.45 μm to 34 μm, and the resistivity is 2.1 μΩcm to 9.6 μΩcm. When the power supply wiring 90 and the common wiring 91 are 40-inch panels made of Cu, when the power supply wiring 90 and the common wiring 91 are Cu-based, the film thickness H is 1.99 μm to 6 μm, the width WL is 14.6 μm to 44.0 μm, The resistivity is 2.1 μΩcm to 9.6 μΩcm.

  In general, in the case of the Cu power supply wiring 90 and the common wiring 91, the film thickness H is 1.31 μm to 6 μm, the width WL is 7.45 μm to 44 μm, and the resistivity is 2.1 μΩcm to 9.6 μΩcm.

  Therefore, when Al-based material or Cu is applied as the power supply wiring 90 and the common wiring 91, the power supply wiring 90 and the common wiring 91 of the EL display panel 1 have a film thickness H of 1.31 μm to 6 μm and a width WL of 7.45 μm. 44 μm and resistivity 2.1 μΩcm to 9.6 μΩcm.

As described above, the magnitude of the current flowing through the power supply wiring 90 is the sum of the magnitudes of the drive currents flowing through the n organic EL elements 20 connected to the one line of scanning lines X _i. In this case, the parasitic capacitance of the power supply wiring 90 is increased, and a thin film such as a gate or source / drain of a thin film transistor has a write current (that is, a write current (ie In this embodiment, the resistance is too high to pass a driving current). However, in this embodiment, at least a part of the power supply wiring 90 is formed by a conductive layer different from the gate, source, and drain of the thin film transistors of the pixel circuits P _{1,1 to} P _{m, n.} Therefore, even in a short selection period, a sufficient writing current (drawing current) can be passed without delay. Since the resistance of the power supply wiring 90 is reduced by increasing the thickness of the power supply wiring 90, the width of the power supply wiring 90 can be reduced. Therefore, in the case of bottom emission, the decrease in pixel aperture ratio can be minimized.

Similarly, since the magnitude of the drive current flowing through the common line 91 during the light emission period is the same as the magnitude of the write current (drawing current) flowing through the power supply line 90 during the selection period, the pixel circuits P _{1,1 to} P _{m, n} Since the conductive layer different from the gate, source and drain of the thin film transistor is connected to the counter electrode 20c, the wiring 91 can be made thicker, the resistance of the common wiring 91 can be reduced, and the counter electrode Even if the thickness of the thin film 20c itself becomes higher, the voltage of the counter electrode 20c can be made uniform in the plane. Therefore, even if the same potential is applied to all the pixel electrodes 20a, the light emission intensity of any organic EL layer 20b is substantially equal, and the in-plane light emission intensity can be made uniform.

  Further, when the EL display panel 1 is used as a top emission type, the counter electrode 20c can be made thinner, so that light emitted from the organic EL layer 20b is not easily attenuated while being transmitted through the counter electrode 20c. Furthermore, since the common wiring 91 is provided between the pixel electrodes 20a adjacent in the horizontal direction in plan view, a decrease in the pixel aperture ratio can be minimized.

In the EL display panel 1, the signal lines Y _{1 to} Y _n inevitably intersect with the scanning lines X _{1 to} X _{m due} to the structure of the matrix pixel, so that one of them is used as the gate conductive layer of the transistors 21 to 23. The other must be the source and drain conductive layers of the transistors 21-23. Since the scanning lines X ₁ to X _m, which is orthogonal to the signal lines Y ₁ to Y _n extend in the horizontal direction, and the supply lines Z ₁ to Z _m and each independently time difference to the selection period only Low Level When other periods are set to the high level, the supply lines Z _{1 to} Z _m are arranged in the horizontal direction, and the power supply wirings 90, 90,... Are connected to the supply lines Z _{1 to} Z _m provided for each row. Since they must be connected to each other, the power supply wirings 90, 90,... Must be extended in the horizontal direction.

  As described above, when the power supply wirings 90, 90,... Extend in the horizontal direction and the common wiring 91 extends in the horizontal direction in accordance with this, the number of pixel rows of the RGB light emission colors of the organic EL element 20 is m. It becomes. The EL display panel 1 is generally long in the horizontal direction in aspect ratio. That is, the number n of pixels in the horizontal direction is larger than the number m of pixels in the vertical direction.

In this embodiment for the supply line Z ₁ to Z _m and feed interconnections 90, 90, feed interconnections since the ... to the common potential 90, 90, ... extending direction of the scanning lines X ₁ to X _m and the supply of It is not necessary to match the extending direction of the lines Z _{1 to} Z _m , and the power supply wirings 90, 90,... Can be laid out so as to be orthogonal to the scanning lines X _{1 to} X _m and the supply lines Z _{1 to} Z _m . Therefore, the power supply wirings 90, 90,... And the common wirings 91, 91,... Are extended in the vertical direction, and are used as metal partition walls that divide the organic EL layer 20b to the left and right to emit light of the same color as the organic EL element 20. The organic EL layer 20b to be formed has a stripe shape extending in the vertical direction. Therefore, the number of RGB light emitting pixel columns of the organic EL element 20 is larger than the number of RGB light emitting pixel rows when the extending direction of the power supply wiring 90 and the common wiring 91 is designed in the horizontal direction. A display with excellent color resolution can be performed.

[Modification 1]
The present invention is not limited to the above embodiment, and various improvements and design changes may be made without departing from the spirit of the present invention.

In the above embodiment, the common wiring 91 and the power supply wiring 90 are alternately arranged. However, as in the EL display panel 101 shown in FIG. 15, the power supply wiring 90 is all between the pixel electrodes 20a adjacent in the vertical direction. There may be. In that case, the common wiring 91 is not formed on the same surface as the power supply wiring 90 but may be provided on an insulating film that insulates the upper side of the power supply wiring 90. It is desirable to arrange (m + 1) common wires 91 so as to partition 20a. The common lines 91, 91,... Are connected to the counter electrode 20c of each pixel through a contact hole of this insulating film provided for each pixel. Feed interconnection 90, so structures in the vertical direction and partitions the organic EL layer 20b, the pixel circuits _{P 1, j, P 2,} j, P 3, j, ..., a P _m, the organic EL element 20 of the _j region When the solution to be the organic EL layer 20b is applied to the pixel circuits P1 _{, (j-1)} , P2 _{, (j-1)} , P3 _{, (j-1)} ,. , P _{m, (j-1)} and P _{1, (j + 1)} , P _{2, (j + 1)} , P _{3, (j + 1)} ,..., P _{m, (j + 1)} It dams up so that it may not go to the field used as element 20. Note that portions corresponding to each other between the EL display panel 101 shown in FIG. 15 and the EL display panel 1 shown in FIG.

[Modification 2]
Further, the above embodiment, in the above modification, there are supply lines Z ₁ to Z _m, the feed interconnection 90 is electrically connected to the drain 22 d, 23d of the transistors 22 and 23 via supply lines Z ₁ to Z _m and the contact hole 53 However, the supply lines Z _{1 to} Z _m are not provided, and the power supply wiring 90 may be conducted to the drains 22 d and 23 d of the transistors 22 and 23 via the contact hole 53.

[Modification 3]
Moreover, in the said embodiment and said each modification, the transistors 21-23 were demonstrated as an N channel type field effect transistor. The transistors 21 to 23 may be P-channel field effect transistors. In that case, in the circuit configuration of FIG. 2, the relationship between the sources 21s, 22s, and 23s of the transistors 21 to 23 and the drains 21d, 22d, and 23d of the transistors 21 to 23 is reversed. For example, when the drive transistor 23 is a P-channel field effect transistor, the drain 23d of the drive transistor 23 is conducted to the pixel electrode 20a of the organic EL element 20, and the source 23s is conducted to the supply line Z _i .

[Modification 4]
Further, the embodiment described above, in the above modification, the signal lines Y ₁ to Y _n gate 21g, 22 g, but which has been patterned from the underlying conductive film of the gate 23g, the signal lines Y ₁ to Y _n May be patterned from the conductive film that is the source of the sources 21s, 22s, and 23s and the drains 21d, 22d, and 23d. In this case, the scanning lines X _{1 to} X _m and the supply lines Z _{1 to} Z _m are patterned from the conductive films that are the sources of the gates 21g, 22g and the gate 23g, and the signal lines Y _{1 to} Y _n are the scanning lines. It is higher than X _{1 to} X _m and supply lines Z _{1 to} Z _m .

[Modification 5]
In the above-described embodiment and each of the above-described modifications, three transistors 21 to 23 are provided for each pixel. However, an EL display panel provided with a driving transistor in which a source or a drain is connected in series to an organic EL element. If so, the present invention can be applied without limitation of the number of transistors, current driving, and voltage driving.

[Modification 6]
In the above-described embodiment and the above-described modifications, the drain 22d of each holding transistor 22 is connected to any _one of the supply lines Z _{1 to} Z _m , but the present invention is not limited thereto, and each pixel circuit P _{i, 1} , P The drain 22d of the holding transistor 22 of _{i, 2} , P _{i, 3} ... P _{i, n} may be connected to the scanning line X _i .
A plurality of the above modifications may be combined.

[Modification 7]
In the above-described embodiment and each of the above-described modifications, the voltage VL serving as a writing current and the voltage VH serving as a driving current are supplied to the power supply wiring 90 from both the wiring terminals 90b and 90c to reduce the voltage drop of the power supply wiring 90. However, if it is a design in which the voltage drop may be high, the wiring terminals 90b and 90c may be supplied from only one of them.

[Second Embodiment]
As a second embodiment, an EL display manufacturing method will be described with reference to FIGS. Note that portions corresponding to each other between the second embodiment and the first embodiment will be described with the same reference numerals. In the present embodiment, the power supply wiring 90 is embedded in the planarization film 33 of the transistor array panel 50, and only the common wiring 91 is interposed between the pixel electrodes 20a arranged in a predetermined direction.

  First, after performing vapor phase growth (for example, sputtering), photolithography, and etching on the insulating substrate 2 several times as appropriate, a resin flattening film 33 is formed by spin coating. The transistor array panel 50 is manufactured.

  Next, a transparent conductive film is formed on the surface of the transistor array panel 50 by a vapor deposition method, and the transparent conductive film is shaped by a photolithography method or an etching method, whereby a plurality of pixel electrodes 20a are formed into a matrix. It forms so that it may arrange in a shape.

  Next, the network-like insulating film 52A is patterned by sequentially performing a vapor deposition method, a photolithography method, and an etching method. In patterning the insulating film 52A, a matrix-shaped opening is formed in the insulating film 52A, and the pixel electrode 20a is exposed in each opening of the insulating film 52A. The edge portion of the pixel electrode 20a is covered with the insulating film 52A.

  Next, a plurality of common wires 91 are provided so as to sew between the pixel electrodes 20a. Specifically, a plurality of common wirings 91 are grown on the insulating film 52A by plating. Here, the common wiring 91 is formed so as to extend in the vertical direction between the pixel electrodes 20a adjacent in the horizontal direction. Since the common wiring 91 is grown by the plating method, the height of the common wiring 91 is larger than the thickness of the insulating film 52A and the pixel electrode 20a. As a material for the common wiring 91, copper, silver, or gold is preferably used.

  Next, the wettability of the surface of the pixel electrode 20a is improved to make the pixel electrode 20a lyophilic by irradiating ultraviolet rays toward the surface of the transistor array panel 50, particularly toward the pixel electrode 20a.

Next, an aqueous solution of a triazine thiol derivative (for example, the following chemical formula) to which sodium hydroxide is added as an additive is prepared. Here, the solvent is pure water, and the concentration of the triazine thiol derivative added with sodium hydroxide is 2.0 × 10 ⁻³ mol / l.

  Next, the transistor array panel 50 is immersed in an aqueous solution of a triazine thiol derivative at 15 to 50 ° C. for 5 to 30 minutes. The thiol group of the triazine thiol derivative is selectively chemically bonded to the metal to such an extent that it exhibits liquid repellency, but is not chemically bonded to the metal oxide or the insulating film to the extent that it exhibits liquid repellency. Therefore, the liquid repellent conductive film 55 of the triazine teal derivative is formed on the surface of the common wiring 91 to the extent that it exhibits liquid repellency, but the surface of the pixel electrode 20a formed of a transparent metal oxide such as ITO and the inorganic compound A film of the triazine thiol derivative is not formed on the surface of the insulating film 52A formed in step 1 to the extent that it exhibits liquid repellency. For example, the immersion time is set to 10 minutes.

  Next, the excess triazine thiol derivative attached to the transistor array substrate 50 is removed with ethanol. By washing the transistor array substrate 50 with ethanol in this manner, excess triazine thiol derivative deposited on the surface of the pixel electrode 20a can be removed, and a decrease in wettability of the pixel electrode 20a can be suppressed. Note that the liquid-repellent conductive film 55 on the surface of the common wiring 91 is fixed to the common wiring 91 by a chemical bond and thus is not removed even by ethanol. If there is a cleaning effect, an alcohol such as methanol or an organic solvent such as acetaldehyde may be used.

  Next, the transistor array substrate 50 is washed with pure water, and then the transistor array substrate 50 is dried by blowing an inert gas such as nitrogen gas onto the transistor array substrate 50.

  Next, an organic compound dispersion in which a hole injection material (for example, PEDOT as a conductive polymer and PSS as a dopant) is dispersed in a dispersion medium or an organic compound solution in which the hole injection material is dissolved in a solvent is used as the pixel electrode 20a. Then, a dispersion medium or solution of a light emitting material (for example, polyfluorene light emitting material) is applied thereon. Pure water is desirable as the solvent or dispersion medium of the hole injection material, and mesitylene is desirable as the solvent or dispersion medium of the light emitting material. By such application, an organic EL layer 20b made of an organic compound is formed on each pixel electrode 20a. Here, since the thick common wiring 91 is provided and the liquid repellent conductive film 55 is coated on the surface of the common wiring 91, the solution or dispersion medium applied to the adjacent pixel electrode 20a. Are not mixed over the common wiring 91. Therefore, the organic EL layer 20b having a uniform film thickness can be formed on the pixel electrode 20a. As an application method, an inkjet method (droplet discharge method) or other printing methods may be used, or a coating method such as a dip coating method or a spin coating method may be used.

  Next, the counter electrode 20c is formed on the entire surface by vapor deposition. The EL display panel is thus completed.

As described above, according to the present embodiment, since the counter electrode 20c is formed on the entire surface in a conductive state with respect to the thick common wiring 91, the counter electrode 20c itself is thinned to have a higher resistance. Even in this case, the voltage of the counter electrode 20c can be made uniform at any location in the plane. Therefore, even if the same potential is applied to all the pixel electrodes 20a, the light emission intensity of any organic EL layer 20b is substantially equal, and the in-plane light emission intensity can be made uniform.
In each of the above embodiments, at least one of the power supply wiring 90 and the common wiring 91 is formed by a plating method. However, the present invention is not limited thereto, and metal fine particles are included in the opening of the resist in which the opening is provided in the region to be formed. After embedding the ink, it may be dried and sintered to form at least one of the power supply wiring 90 and the common wiring 91.

Examples of the present invention will be described below.
When a liquid repellent conductive film was formed on a Cu, Ag, Au, Al, Cr, ITO or SiN thin film in the same manner as the liquid repellent conductive film 55 described above, the contact angle with respect to pure water or mesitylene was measured. The results are shown in Table 1. Cu, Au, Al, Cr and ITO were formed by sputtering, Ag was baked after coating with a nanometal ink, and SiN was formed by plasma CVD. As is clear from Table 1, in the case of pure water, the contact angle exceeds 100 ° for Cu, Ag, and Au, and less than 20 ° for the other cases. In the case of mesitylene, Cu, Ag and Au showed a strong liquid repellency with a contact angle exceeding 40 °. In other conductive films, there was no significant difference in the contact angle between pure water and mesitylene. Accordingly, Cu, Ag, and Au are suitable as materials for the common wiring 91, and an organic compound-containing liquid solvent containing an organic compound that becomes the organic EL layer 20b that is in direct contact with the pixel electrode 20a is an organic solvent such as mesitylene. It can be seen that the solvent is preferred.

また比較例として、溶剤を塗布前にＯ_２プラズマ処理を行った例、Ｏ_２プラズマ処理及びＣＦ_４プラズマ処理を行った例、隔壁にフッ素コーティングを行った例において、溶剤との接触角を測定した。

Ｏ_２プラズマ処理では、共通配線９１のような金属隔壁と異なってポリイミドを隔壁として用いた場合、画素電極が親液化処理を行うことができたが、同時に隔壁も親液化処理化されてしまい、純水及びメシチレンを溶剤として成膜すると、隔壁や絶縁ライン寄りの画素電極の周縁で膜厚が厚く中央部で薄くなってしまっていた。
Ｏ_２プラズマ処理後にＣＦ_４プラズマ処理を行った場合、隔壁を選択的に撥液化できたが、純水及びメシチレンの接触角が本実施例のＣｕ、Ａｇ、Ａｕに比べて劣っていた。また隔壁が金属ではないので、隔壁を配線として利用できない。
Ａｕからなる隔壁にフッ素コーティング（KP801M 信越化学製）を行った場合、隔壁が撥液性を示したが、画素電極まで撥液性を示してしまい、画素電極上に均一な膜厚に塗布できなかった。
このように比較例では、撥液性を十分示さないか、隔壁と画素電極との選択性はあっても本願発明より劣るか、撥液性を示しても隔壁と画素電極との選択性がないことが確認された。

In addition, as a comparative example, the contact angle with the solvent was measured in an example in which the O ₂ plasma treatment was performed before coating the solvent, an example in which the O ₂ plasma treatment and the CF ₄ plasma treatment were performed, and an example in which the partition walls were coated with fluorine. did.

In the O ₂ plasma treatment, when polyimide is used as a partition unlike the metal partition like the common wiring 91, the pixel electrode can be lyophilic, but at the same time, the partition is also made lyophilic. When pure water and mesitylene were used as a solvent, the film thickness was thick at the periphery of the pixel electrode near the partition walls and the insulation lines, and thin at the center.
When CF ₄ plasma treatment was performed after O ₂ plasma treatment, the partition walls could be selectively made liquid repellent, but the contact angles of pure water and mesitylene were inferior to those of Cu, Ag, and Au in this example. Moreover, since the partition is not a metal, the partition cannot be used as wiring.
When fluorine coating (KP801M manufactured by Shin-Etsu Chemical Co., Ltd.) was applied to the barrier ribs made of Au, the barrier ribs showed liquid repellency, but they showed liquid repellency up to the pixel electrodes and could be applied to the pixel electrodes with a uniform film thickness. There wasn't.
As described above, in the comparative example, the liquid repellency is not sufficiently exhibited, the selectivity between the partition walls and the pixel electrode is inferior to that of the present invention, or the selectivity between the partition walls and the pixel electrode is exhibited even though the liquid repellency is exhibited. Not confirmed.

1 is a diagram illustrating a circuit configuration of an EL display panel 1 together with an insulating substrate 2. 3 is an equivalent circuit diagram of a pixel circuit P _{i, j} of the EL display panel 1. FIG. 3 is a plan view showing electrodes of a pixel circuit P _{i, j} and a pixel circuit P _{i, j + 1} of the EL display panel 1. FIG. 4 is a cross-sectional view taken along a plane orthogonal to the channel width of the drive transistor 23. FIG. FIG. 5 is a cross-sectional view taken along line VV shown in FIG. 3. FIG. 4 is a cross-sectional view taken along the line VI-VI shown in FIG. 3. 5 is a schematic diagram showing a film structure of a liquid repellent conductive film 55. FIG. 2 is a schematic plan view showing a layout of an organic EL layer of an EL display panel 1. FIG. 4 is a timing chart for explaining the operation of the EL display panel 1. 4 is a graph showing current-voltage characteristics of a drive transistor 23 and an organic EL element 20 of each pixel circuit P _{1,1 to} P _{m, n} . 4 is a graph showing the correlation between the maximum voltage drop of each of the power supply wiring 90 and the common wiring 91 of the 32-inch EL display panel 1 and the wiring resistivity ρ / cross-sectional area S. It is a graph which shows the correlation of each cross-sectional area of the electric power feeding wiring 90 and the common wiring 91 of 32 inch EL display panel 1, and current density. It is a graph which shows the correlation of each maximum voltage drop of the electric power feeding wiring 90 and the common wiring 91 of 40-inch EL display panel 1, and wiring resistivity (rho) / sectional area S. FIG. It is a graph which shows the correlation of each cross-sectional area of the electric power feeding wiring 90 of the 40-inch EL display panel 1, and the common wiring 91, and a current density. It is drawing which showed the circuit structure of EL display panel 1 of a modification. It is a schematic sectional drawing of EL display of 2nd Embodiment.

Explanation of symbols

1 EL Display Panel 2 Insulating Substrate 20a Pixel Electrode 20b Organic EL Layer 20c Counter Electrode 23 Drive Transistor 23
23d drain 23s source 23g gate 32 protective insulating film 54 liquid repellent insulating film 90 power supply wiring Y _{1 to} Y _n signal line Z _{1 to} Z _m supply line

Claims (6)

A substrate,
A plurality of driving transistors arranged in a matrix on the substrate;
A plurality of signal lines patterned with one of drain / source and gate of the plurality of driving transistors and arranged parallel to each other on the substrate;
A protective insulating film covering the plurality of signal lines and the plurality of driving transistors;
A plurality of pixel electrodes that are electrically connected to one of a source and a drain of each of the plurality of driving transistors and are formed on the protective insulating film;
A plurality of light emitting layers formed on each of the plurality of pixel electrodes;
A counter electrode provided on the plurality of light emitting layers;
It formed on the protective insulating film so as to be parallel to the signal line, and the protection plurality of feed lines that respectively conducted to the other of the source and the drain of said plurality of driving transistors through contact holes formed in the insulating film ,
A plurality of common wires formed on the protective insulating film, electrically connected to the counter electrode, applied with a common voltage, and alternately arranged with the plurality of power supply wires ;
The display panel, wherein the plurality of light emitting layers are disposed between the power supply wiring and the common wiring, and are formed of an organic compound-containing liquid partitioned into the power supply wiring and the common wiring . The display panel according to claim 1 , wherein the light emitting layer is formed continuously to a plurality of the pixel electrodes along the power supply wiring. Display panel according to claim 1 or 2 the thickness of the feed line is characterized in that it is a 1.31～6Myuemu. The display panel according to any one of claims 1 to 3 , wherein a width of the power supply wiring is 7.45 to 44 µm. Display panel as claimed in any one of claims 4 to resistivity of the feed interconnection is characterized in that it is a 2.1～9.6Myuomegacm. A driving method for driving the display panel according to any one of claims 1 to 5 ,
The display panel is
Scanning lines;
A holding transistor having a drain connected to the supply line, a source connected to the gate of the drive transistor, and a gate connected to the scan line;
A switch transistor having a drain connected to each of one of the source and drain of the plurality of drive transistors, a source connected to each of the plurality of signal lines, and a gate connected to the scan line;
A transmission circuit for transmitting a clock signal;
With
The display panel driving method, wherein the oscillation circuit outputs a clock signal to the power supply wiring.

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