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JP2006119618A5 - - Google Patents

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Publication number
JP2006119618A5
JP2006119618A5 JP2005269434A JP2005269434A JP2006119618A5 JP 2006119618 A5 JP2006119618 A5 JP 2006119618A5 JP 2005269434 A JP2005269434 A JP 2005269434A JP 2005269434 A JP2005269434 A JP 2005269434A JP 2006119618 A5 JP2006119618 A5 JP 2006119618A5
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JP
Japan
Prior art keywords
display panel
power supply
panel according
supply wiring
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2005269434A
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Japanese (ja)
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JP5017826B2 (en
JP2006119618A (en
Filing date
Publication date
Application filed filed Critical
Priority claimed from JP2005269434A external-priority patent/JP5017826B2/en
Priority to JP2005269434A priority Critical patent/JP5017826B2/en
Priority to TW094132283A priority patent/TWI279752B/en
Priority to US11/232,368 priority patent/US7573068B2/en
Priority to CN200510106398A priority patent/CN100595819C/en
Priority to CN2008100832178A priority patent/CN101266945B/en
Priority to KR1020050087577A priority patent/KR100735977B1/en
Publication of JP2006119618A publication Critical patent/JP2006119618A/en
Publication of JP2006119618A5 publication Critical patent/JP2006119618A5/ja
Priority to US12/477,710 priority patent/US7871837B2/en
Publication of JP5017826B2 publication Critical patent/JP5017826B2/en
Application granted granted Critical
Active legal-status Critical Current
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Claims (11)

基板と、
前記基板上にマトリクス状に配列された複数の駆動トランジスタと、
前記複数の駆動トランジスタのドレイン・ソースとゲートのうちの一方とともにパターニングされ、前記基板上において互いに平行となるよう配列された複数の信号線と、
前記複数の信号線及び前記複数の駆動トランジスタを被覆した保護絶縁膜と、
前記複数の駆動トランジスタそれぞれのソースとドレインの一方に導通した複数の画素電極と、
前記複数の画素電極それぞれに成膜された複数の発光層と、
前記信号線と平行となるよう前記保護絶縁膜上に形成され、前記保護絶縁膜に形成されたコンタクトホールを介して前記複数の駆動トランジスタのソースとドレインの他方に導通した給電配線と、を備えることを特徴とするディスプレイパネル。 A substrate,
A plurality of driving transistors arranged in a matrix on the substrate;
A plurality of signal lines patterned with one of drain / source and gate of the plurality of driving transistors and arranged parallel to each other on the substrate;
A protective insulating film covering the plurality of signal lines and the plurality of driving transistors;
A plurality of pixel electrodes electrically connected to one of a source and a drain of each of the plurality of driving transistors;
A plurality of light emitting layers formed on each of the plurality of pixel electrodes;
A power supply wiring that is formed on the protective insulating film so as to be parallel to the signal line, and is electrically connected to the other of the source and drain of the plurality of driving transistors through a contact hole formed in the protective insulating film. A display panel characterized by that. 前記給電配線は複数本であり、互いに導通していることを特徴とする請求項１に記載のディスプレイパネル。   The display panel according to claim 1, wherein a plurality of the power supply wirings are connected to each other. 前記保護絶縁膜上に、前記複数の給電配線と互い違いに配列された複数の共通配線を有することを特徴とする請求項２に記載のディスプレイパネル。   The display panel according to claim 2, further comprising a plurality of common wirings arranged alternately with the plurality of power supply wirings on the protective insulating film. 前記発光層は、前記給電配線と前記共通配線との間に形成されていることを特徴とする請求項３に記載のディスプレイパネル。   The display panel according to claim 3, wherein the light emitting layer is formed between the power supply wiring and the common wiring. 前記発光層は、前記給電配線に沿って前記画素電極のうちの複数に連続して形成されていることを特徴とする請求項１から請求項４の何れか一項に記載のディスプレイパネル。   5. The display panel according to claim 1, wherein the light emitting layer is formed continuously to a plurality of the pixel electrodes along the power supply wiring. 6. 前記給電配線を被覆した撥液性絶縁膜を更に備えていることを特徴とする請求項１から請求項５の何れか一項に記載のディスプレイパネル。   The display panel according to claim 1, further comprising a liquid repellent insulating film covering the power supply wiring. 前記複数の駆動トランジスタのドレイン・ソースとゲートの他方とともにパターニングされ、平面視して前記複数の信号線と直交するよう配列され、前記駆動トランジスタのソースとドレインの他方及び前記給電配線に導通した供給線を更に備えていることを特徴とする請求項１から請求項６の何れか一項に記載のディスプレイパネル。   Patterned together with the other of the drain / source and gate of the plurality of driving transistors, arranged to be orthogonal to the plurality of signal lines in plan view, and connected to the other of the source and drain of the driving transistor and the power supply wiring The display panel according to claim 1, further comprising a line. 前記給電配線の厚さが１．３１〜６μｍであることを特徴とする請求項１から請求項７の何れか一項に記載のディスプレイパネル。   The display panel according to claim 1, wherein a thickness of the power supply wiring is 1.31 to 6 μm. 前記給電配線の幅が７．４５〜４４μｍであることを特徴とする請求項１から請求項８の何れか一項に記載のディスプレイパネル。   The display panel according to claim 1, wherein a width of the power supply wiring is 7.45 to 44 μm. 前記給電配線の抵抗率が２．１〜９．６μΩｃｍであることを特徴とする請求項１から請求項９の何れか一項に記載のディスプレイパネル。   The display panel according to claim 1, wherein a resistivity of the power supply wiring is 2.1 to 9.6 μΩcm. 請求項１から請求項１０の何れか一項に記載のディスプレイパネルを駆動する駆動方法であって、
クロック信号を前記給電配線に出力することを特徴とするディスプレイパネルの駆動方法。 A driving method for driving the display panel according to any one of claims 1 to 10,
A display panel driving method, comprising: outputting a clock signal to the power supply wiring.
JP2005269434A 2004-09-21 2005-09-16 Display panel and driving method thereof Active JP5017826B2 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2005269434A JP5017826B2 (en) 2004-09-21 2005-09-16 Display panel and driving method thereof
TW094132283A TWI279752B (en) 2004-09-21 2005-09-19 Transistor array substrate, display panel and manufacturing method of display panel
CN2008100832178A CN101266945B (en) 2004-09-21 2005-09-21 Manufacturing method of display panel
CN200510106398A CN100595819C (en) 2004-09-21 2005-09-21 Transistor array substrate and display panel
US11/232,368 US7573068B2 (en) 2004-09-21 2005-09-21 Transistor array substrate and display panel
KR1020050087577A KR100735977B1 (en) 2004-09-21 2005-09-21 Transistor array substrate, manufacturing method thereof and display panel
US12/477,710 US7871837B2 (en) 2004-09-21 2009-06-03 Display panel manufacturing method

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2004273580 2004-09-21
JP2004273580 2004-09-21
JP2005269434A JP5017826B2 (en) 2004-09-21 2005-09-16 Display panel and driving method thereof

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2008231811A Division JP5040867B2 (en) 2004-09-21 2008-09-10 Display panel and manufacturing method thereof

Publications (3)

Publication Number Publication Date
JP2006119618A JP2006119618A (en) 2006-05-11
JP2006119618A5 true JP2006119618A5 (en) 2008-10-30
JP5017826B2 JP5017826B2 (en) 2012-09-05

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005269434A Active JP5017826B2 (en) 2004-09-21 2005-09-16 Display panel and driving method thereof

Country Status (1)

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JP (1) JP5017826B2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4857688B2 (en) 2005-09-29 2012-01-18 カシオ計算機株式会社 Display device and manufacturing method thereof
KR100868427B1 (en) 2006-05-10 2008-11-11 가시오게산키 가부시키가이샤 Display device and manufacturing method thereof
US7863612B2 (en) 2006-07-21 2011-01-04 Semiconductor Energy Laboratory Co., Ltd. Display device and semiconductor device
JP5119635B2 (en) * 2006-09-25 2013-01-16 カシオ計算機株式会社 Manufacturing method of display device
JP2009070708A (en) * 2007-09-13 2009-04-02 Casio Comput Co Ltd Display device and method of manufacturing the same
JP4497185B2 (en) 2007-09-18 2010-07-07 カシオ計算機株式会社 Manufacturing method of display device
KR101456154B1 (en) 2009-08-25 2014-11-04 삼성디스플레이 주식회사 Organic light emitting diode lighting apparatus
JP5685855B2 (en) 2009-09-08 2015-03-18 株式会社リコー Display device and manufacturing method of display device
CN103229227B (en) * 2011-11-24 2016-02-10 株式会社日本有机雷特显示器 The driving method of display device

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4593740B2 (en) * 2000-07-28 2010-12-08 ルネサスエレクトロニクス株式会社 Display device
JP2003022892A (en) * 2001-07-06 2003-01-24 Semiconductor Energy Lab Co Ltd Manufacturing method of light emitting device
JP2003059660A (en) * 2001-08-17 2003-02-28 Toshiba Corp Manufacturing method of self-luminescence display
JP2003108070A (en) * 2001-09-28 2003-04-11 Sanyo Electric Co Ltd Display device
JP3893937B2 (en) * 2001-10-19 2007-03-14 セイコーエプソン株式会社 Head unit assembling apparatus and assembling method, and droplet discharge head positioning apparatus and positioning method
JP2003127342A (en) * 2001-10-19 2003-05-08 Seiko Epson Corp Liquid drop ejection head and electronic equipment equipped with the same, manufacturing methods for liquid crystal display, organic el device, electron- emitting device, pdp device, electrophoretic display, color filter and organic el, and methods for forming spacer, metallic wiring, lens, resist and light diffusion body
JP4141674B2 (en) * 2001-10-22 2008-08-27 セイコーエプソン株式会社 Droplet discharge head, wiping method thereof, and electronic apparatus equipped with the same
AU2003253719A1 (en) * 2002-03-20 2003-09-29 Koninklijke Philips Electronics N.V. Active matrix display devices, and their manufacture
JP3551194B1 (en) * 2002-05-29 2004-08-04 セイコーエプソン株式会社 Electro-optical device, its driving circuit, element driving device, and electronic equipment
JP4103500B2 (en) * 2002-08-26 2008-06-18 カシオ計算機株式会社 Display device and display panel driving method
JP3922374B2 (en) * 2002-09-25 2007-05-30 セイコーエプソン株式会社 Electro-optical device, matrix substrate, and electronic apparatus
JP2004163673A (en) * 2002-11-13 2004-06-10 Toshiba Corp Display device
CN100370491C (en) * 2002-12-10 2008-02-20 株式会社半导体能源研究所 Light emitting device and manufacturing method thereof
KR100521277B1 (en) * 2003-02-05 2005-10-13 삼성에스디아이 주식회사 Flat Panel Display with Anode electrode layer as Power Supply Layer and Fabrication Method thereof

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