JP4192879B2 - Display panel - Google Patents

Description

  The present invention relates to a display panel using light emitting elements as subpixels.

  Organic electroluminescence display panels can be broadly classified into passive drive type and active matrix drive type. Active matrix drive type organic electroluminescence display panels are passive in terms of high contrast and high definition. It is superior to the drive system. For example, in the conventional active matrix driving organic electroluminescence display panel described in Patent Document 1, an organic electroluminescence element (hereinafter referred to as an organic EL element) and a voltage signal corresponding to image data are applied to the gate. In addition, a driving transistor that supplies current to the organic EL element and a switching transistor that performs switching for supplying a voltage signal corresponding to image data to the gate of the driving transistor are provided for each subpixel. In this organic electroluminescence display panel, when a scanning line is selected, the switching transistor is turned on. At that time, a voltage representing a luminance is applied to the gate of the driving transistor via the signal line. As a result, the drive transistor is turned on, and a drive current having a magnitude corresponding to the level of the gate voltage flows from the power source to the organic EL element via the source-drain of the drive transistor, and the organic EL element corresponds to the magnitude of the current. Emits light with high brightness. From the end of the selection of the scanning line to the next selection of the scanning line, even if the switching transistor is turned off, the level of the gate voltage of the driving transistor is kept, and the organic EL element becomes the voltage. Light is emitted at a luminance according to the magnitude of the corresponding drive current.

  In order to drive an organic electroluminescence display panel, a drive circuit is provided around the organic electroluminescence display panel, and a voltage is applied to a scanning line, a signal line, a power supply line, etc. laid on the organic electroluminescence display panel. It has been broken.

In addition, in a conventional active matrix driving type organic electroluminescence display panel, wiring for passing a current through an organic EL element such as a power supply line is formed simultaneously with a thin film transistor patterning process using a thin film transistor material such as a switching transistor and a driving transistor. Patterned. That is, in manufacturing an organic electroluminescence display panel, the thin film transistor electrode is shaped from the conductive thin film by performing a photolithography method and an etching method on the conductive thin film that is the source of the thin film transistor electrode. At the same time, the wiring connected to the electrode is processed. Therefore, when the wiring is formed from a conductive thin film, the wiring has the same thickness as the electrode of the thin film transistor.
JP-A-8-330600

  However, since the electrode of the thin film transistor is designed on the assumption that it functions as a transistor, in other words, it is not designed on the assumption that a current flows through the organic EL element. When a current is caused to flow from the wiring to the plurality of organic EL elements, a voltage drop occurs due to the electrical resistance of the wiring, or a delay of the current flow through the wiring occurs. In order to suppress the voltage drop and current delay, it is desirable to reduce the resistance of the wiring. For this purpose, the metal layers that serve as the source and drain of the transistor and the metal layer that serves as the gate are made thicker, or the current is sufficient for these metal layers. If it is patterned to be so wide that it flows to a low resistance wiring, the area where the wiring overlaps with other wiring or conductors in plan view increases, and parasitic capacitance occurs between them, In the case of a so-called bottom emission structure that causes the current flow to slow down or emits EL light from the transistor array substrate side, the light from the organic EL element is shielded, so the ratio of the light emitting area This has led to a decrease in the aperture ratio. Further, when the gate of the thin film transistor is made thicker in order to reduce the resistance, it is necessary to increase the thickness to a flattening film (for example, corresponding to a gate insulating film when the thin film transistor has an inverted staggered structure) for flattening the step of the gate, The transistor characteristics may change greatly, and if the source and drain are made thicker, the etching accuracy of the source and drain is lowered, which may also adversely affect the characteristics of the transistor.

  Accordingly, an object of the present invention is to suppress voltage drop and signal delay through wiring.

In order to solve the above problems, the display panel according to claim 1 is:
A substrate,
A driving transistor provided for each subpixel on the substrate;
One of a source and a drain is electrically connected to one of a source and a drain of the driving transistor, and a switch transistor provided for each subpixel on the substrate;
One of the source and drain is conducted to the other of the source and drain of the driving transistor, and the other of the source and drain is conducted to the gate of the driving transistor, and is provided for each subpixel on the substrate. Holding transistor,
An insulating film formed to cover the driving transistor, the switch transistor, and the holding transistor, and having a plurality of grooves;
Wherein the projecting manner from the insulating film together when it is buried in each groove, electrically connected to the other of the source and drain of the driving transistor, the driving transistor, the switching transistor and a gate of the holding transistor, the source and drain A power supply wiring formed by a different conductive layer from
A sub-pixel electrode provided in a matrix for each sub-pixel on the insulating film and electrically connected to one of a source and a drain of the driving transistor;
A light emitting layer formed on an upper surface of the subpixel electrode;
A counter electrode formed to cover the light emitting layer;
A selection wiring for selecting the switch transistor and the holding transistor, which is a groove different from the groove in which the power supply wiring of the insulating film is embedded, and is embedded in the groove formed in the insulating film;
A common wiring connected to the counter electrode;
Equipped with a,
The power supply wiring has a lower layer formed with the selection wiring and an upper layer formed with the common wiring .

  Preferably, the subpixel electrodes are arranged along the power supply wiring.

In the present invention, the selection wiring for selecting the switch transistor and the holding transistor is embedded in a groove formed in the insulating film which is different from the groove in which the power supply wiring of the insulating film is embedded. .

Further , a common wiring connected to the counter electrode is provided.

In particular, the selection wiring for selecting the switch transistor and the holding transistor is embedded in a groove formed in the insulating film which is different from the groove in which the power supply wiring of the insulating film is embedded, and the counter electrode The power supply wiring is formed such that a lower layer is formed with the selection wiring and an upper layer is formed with the common wiring.

  Preferably, the power supply wiring is thicker than the selection wiring and thicker than the common wiring.

  Preferably, the power supply wiring is patterned together with the gate, source or drain of the drive transistor, the switch transistor and the holding transistor, and is stacked on the supply line exposed by the groove.

  The display panel may further include a hydrophobic insulating film that covers each of the power supply wirings, has water repellency, oil repellency, and insulation and is covered with the counter electrode. The light emitting layer is formed by a wet coating method.

The display panel according to claim 6 comprises:
A substrate,
A light emitting device provided on the substrate;
A first transistor connected to one electrode of the light emitting element and supplying a drive current;
A second transistor for controlling the first transistor;
A selection wiring for selecting the second transistor formed by a conductive layer different from the gate, source and drain of the second transistor;
A lower layer is formed together with the selection wiring, an upper layer is formed on the lower layer , connected to the first transistor, and a power supply wiring having a lower resistance per unit length than the selection wiring,
A common line formed together with the upper layer of the power supply line and connected to the other electrode of the light emitting element;
Is provided.

  According to the first aspect of the present invention, since the power supply wiring is formed of a conductive layer different from that of the transistor, the power supply wiring is made thick regardless of the thicknesses of the gate, source and drain of the drive transistor, switch transistor and holding transistor. And the resistance of the power supply wiring can be reduced. Therefore, even when a signal is output to the transistor / subpixel electrode through the power supply wiring, the voltage drop can be suppressed and the signal delay can be suppressed.

According to the sixth aspect of the present invention, since the selection wiring is formed of a conductive layer different from that of the second transistor, it can be formed thick and low resistance regardless of the design of the second transistor, so that the voltage drop is suppressed. In addition, since the resistance per unit length of the power supply wiring is further lower than that of the selection wiring, a voltage drop can be suppressed and a driving current can be passed quickly to the light emitting element.

  The best mode for carrying out the present invention will be described below with reference to the drawings. However, although various technically preferable limitations for implementing the present invention are given to the embodiments described below, the scope of the invention is not limited to the following embodiments and illustrated examples. Further, in the following description, the term electroluminescence is abbreviated as EL.

[Planar layout of display panel]
FIG. 1 shows a schematic plan view of a pixel 3 of a display panel 1 for color display that operates by an active matrix driving method. In this display panel 1, one dot of red subpixel Pr, one dot of green subpixel Pg, and one dot of blue subpixel Pb are adjacent to each other in the vertical direction (column direction) for each pixel 3. It is arranged. In the display panel 1, a plurality of pixels 3 are arranged in a matrix. A row composed of a plurality of subpixels Pr along a horizontal direction (row direction), a row composed of a plurality of subpixels Pg, and a row composed of subpixels Pb are arranged. In the vertical direction, one red subpixel Pr, one green subpixel Pg, and one blue subpixel Pb are repeatedly arranged in this order, and the subpixels Pr, Pg, and Pb are arranged in a matrix as a whole. . In the following description, the sub-pixel P represents an arbitrary sub-pixel among the red sub-pixel Pr, the green sub-pixel Pg, and the blue sub-pixel Pb. This applies to any of the blue subpixels Pb.

  Further, signal lines Yr, Yg, Yb extend along the columns of the pixels 3 in the vertical direction, and three signal lines Yr, Yg, Yb are provided for each column of the pixels 3 in the vertical direction. The signal line Yr supplies a signal to all red subpixels Pr in one column of the pixels 3 along the vertical direction, and the signal line Yg is all green in one column of the pixels 3 along the vertical direction. A signal is supplied to the subpixel Pg, and the signal line Yb supplies a signal to all the blue subpixels Pb in one column of the pixels 3 along the vertical direction.

  A plurality of scanning lines X extend in the horizontal direction, and a plurality of supply lines Z, a plurality of selection wirings 89, a plurality of power supply wirings 90, and a plurality of common lines are shared with respect to the scanning lines X. Wirings 91A and 91B are provided in parallel. For each column of pixels 3 in the horizontal direction, one scanning line X, one supply line Z, one power supply wiring 90, one selection wiring 89, two common wirings 91A, 91B. Specifically, the common wiring 91A is arranged between one row of the red subpixel Pr in the horizontal direction and one row of the green subpixel Pg adjacent to this row, and the common wiring 91B is one row of the green subpixel Pg in the horizontal direction. And a row of blue subpixels Pb adjacent to this row. The scanning line X and the selection wiring 89 are arranged between one row of the green subpixel Pg in the horizontal direction and one row of the blue subpixel Pb adjacent to the row, and the supply line Z and the power supply wiring 90 are the red subpixel in the horizontal direction. It is arranged between one row of Pr and one row of blue subpixels Pb adjacent to this row.

  Here, the scanning line X supplies signals to all the sub-pixels Pr, Pg, and Pb of the pixels 3 arranged in three rows along the horizontal direction, and the supply line Z also extends in three rows along the horizontal direction. Signals are supplied to all the sub-pixels Pr, Pg, and Pb of the arranged pixels 3.

  When m scanning lines X and supply lines Z are provided, and n signal lines Yr, Yg, and Yb are provided, subpixels Pr, Pg, and Pb are provided (m × n) dots, respectively. The sum of the pixels Pr, Pg, and Pb is (3 × m × n) dots. In this case, the pixels 3 are arranged by m pixels in the vertical direction and n pixels in the horizontal direction.

  Also, in plan view, the selection wiring 89 overlaps the scanning line X, the power supply wiring 90 overlaps the supply line Z, and the common wiring 91B overlaps the selection wiring 89. As will be described in detail later, the selection wiring 89 is electrically connected to the scanning line X and the power supply wiring 90 is electrically connected to the supply line Z, but the common wiring 91B is also connected to the scanning line X. Also not conducting.

  The colors of the subpixels Pr, Pg, and Pb are determined by the emission color of the organic EL element 20 (shown in FIG. 2 and the like) described later. When viewed in plan with a focus on the entire display panel 1, the subpixel electrodes 20a (shown in FIG. 2 and the like) that are anodes of the organic EL elements 20 are arranged in a matrix, and one dot is formed by one subpixel electrode 20a. Sub-pixels P are determined.

[Sub-pixel circuit configuration]
Next, the circuit configuration of the subpixels Pr, Pg, and Pb will be described with reference to the equivalent circuit diagram of FIG. All of the subpixels Pr, Pg, and Pb are configured in the same manner. For each subpixel P of one dot, the organic EL element 20 and an N-channel amorphous silicon thin film transistor (hereinafter simply referred to as a transistor) 21,22. 23 and a capacitor 24 are provided. Hereinafter, the transistor 21 is referred to as a switch transistor 21, the transistor 22 is referred to as a holding transistor 22, and the transistor 23 is referred to as a drive transistor 23. In FIG. 2 and the following description, in the case of the red subpixel Pr, the signal line Y represents the signal line Yr in FIG. 1, and in the case of the green subpixel Pg, the signal line Y represents the signal line Yg in FIG. In the case of the blue subpixel Pb, the signal line Y represents the signal line Yb in FIG.

  In the switch transistor 21, the source 21s is conducted to the signal line Y, the drain 21d is conducted to the subpixel electrode 20a of the organic EL element 20, the source 23s of the driving transistor 23 and the upper layer electrode 24B of the capacitor 24, and the gate 21g is held. The transistor 22 is electrically connected to the scanning line X and the selection wiring 89 together with the gate 22g.

  In the holding transistor 22, the source 22 s is connected to the gate 23 g of the drive transistor 23 and the lower layer electrode 24 A of the capacitor 24, the drain 22 d is connected to the drain 23 d of the drive transistor 23 and the supply line Z, and the gate 22 g is connected to the switch transistor 21. It is electrically connected to the gate 21g and the scanning line X.

  In the drive transistor 23, the source 23 s is connected to the subpixel electrode 20 a of the organic EL element 20, the drain 21 d of the switch transistor 21 and the electrode 24 B of the capacitor 24, and the drain 23 d is connected to the drain 22 d of the holding transistor 22 and the supply line Z. The gate 23g is electrically connected to the source 22s of the holding transistor 22 and the lower layer electrode 24A of the capacitor 24.

  The counter electrode 20c serving as the cathode of the organic EL element 20 is electrically connected to the common wires 91A and 91B.

  The source 21s of the switch transistor 21 of any red sub-pixel Pr in the column of pixels 3 arranged in a line along the vertical direction is electrically connected to the common signal line Yr, and the pixels 3 arranged in a line along the vertical direction. The source 21s of the switch transistor 21 of any of the green subpixels Pg in the column is electrically connected to the common signal line Yg, and the switch transistor of any of the blue subpixels Pb in the column of the pixels 3 arranged in a line along the vertical direction. The 21 sources 21s are also connected to the common signal line Yb.

  On the other hand, the gates 21g of the switch transistors 21 of any of the sub-pixels Pr, Pg, and Pb of the pixels 3 in one row arranged along the horizontal direction are electrically connected to the common scanning line X and arranged along the horizontal direction. The gates 22g of the holding transistors 22 of any of the subpixels Pr, Pg, and Pb of the pixels 3 for one row are electrically connected to the common scanning line X, and any of the subpixels of the pixels 3 for one row arranged in the horizontal direction. The drains 22d of the holding transistors 22 of Pr, Pg, and Pb are also conducted to the common supply line Z, and the drive transistors 23 of any of the sub-pixels Pr, Pg, and Pb of the pixels 3 in one row arranged along the horizontal direction. The drain 23d is also connected to the common supply line Z.

[Plane layout of pixels]
The planar layout of the pixel 3 will be described with reference to FIGS. 3 is a plan view mainly showing electrodes of the red subpixel Pr, FIG. 4 is a plan view mainly showing electrodes of the green subpixel Pg, and FIG. 5 is an electrode of the blue subpixel Pb. It is the top view which mainly showed. 3 to 5, illustration of the subpixel electrode 20a and the counter electrode 20c of the organic EL element 20 is omitted for easy viewing of the drawings.

  As shown in FIG. 3, in the red subpixel Pr, the driving transistor 23 is arranged along the supply line Z and the power supply wiring 90 and the switch transistor 21 is arranged along the common wiring 91A in plan view. The holding transistor 22 is arranged at the corner of the red subpixel Pr near the supply line Z.

  As shown in FIG. 4, in the green subpixel Pg, the driving transistor 23 is arranged along the common wiring 91A and the switch transistor 21 is arranged along the scanning line X and the selection wiring 89 in plan view. The holding transistor 22 is disposed at the corner of the green subpixel Pg near the common wiring 91A.

  As shown in FIG. 5, in the blue subpixel Pb, the driving transistor 23 is arranged along the scanning line X in plan view, and the switch transistor 21 is along the supply line Z and the power supply wiring 90 in the adjacent row. The holding transistor 22 is arranged at the corner of the blue subpixel Pb near the scanning line X.

  In any of the subpixels Pr, Pg, Pb, the capacitor 24 is arranged along the signal line Yr in the adjacent column.

  When the entire display panel 1 is viewed in plan and attention is paid only to the switch transistors 21 of all the subpixels Pr, Pg, Pb, a plurality of switch transistors 21 are arranged in a matrix, and all the subpixels Pr, Pg, When attention is paid only to the holding transistor 22 of Pb, a plurality of holding transistors 22 are arranged in a matrix, and when attention is paid only to the driving transistors 23 of all the subpixels Pr, Pg, Pb, the plurality of driving transistors 23 are arranged in a matrix. Has been.

[Layer structure of display panel]
The layer structure of the display panel 1 will be described with reference to FIG. Here, FIG. 6 is a cross-sectional view taken in the direction of the thickness of the insulating substrate 2 along the broken line VI-VI shown in FIGS.

  The display panel 1 is obtained by laminating various layers on an insulating substrate 2 having optical transparency. The insulating substrate 2 is provided in the form of a flexible sheet or is provided in the form of a rigid plate.

  First, the layer structure of the transistors 21 to 23 will be described. As shown in FIG. 6, the switch transistor 21 includes a gate 21g formed on the insulating substrate 2, a semiconductor film 21c facing the gate 21g with a gate insulating film 31 covering the gate 21g interposed therebetween, and a semiconductor film 21c. Impurity semiconductor films 21a and 21b that are formed on both ends of the semiconductor film 21c so as to be separated from each other and partially overlap the channel protection film 21p, and the impurity semiconductor film 21a The drain 21d is formed on the impurity semiconductor film 21b, and the source 21s is formed on the impurity semiconductor film 21b. Note that the drain 21d and the source 21s may have a single-layer structure or a stacked structure of two or more layers.

  The driving transistor 23 includes a gate 23g formed on the insulating substrate 2, a semiconductor film 23c opposed to the gate 23g with the gate insulating film 31 interposed therebetween, and a channel protective film 23p formed on the central portion of the semiconductor film 23c. The impurity semiconductor films 23a and 23b are formed on both ends of the semiconductor film 23c so as to be separated from each other and partially overlap the channel protective film 23p, the drain 23d formed on the impurity semiconductor film 23a, and the impurity semiconductor film 23b. And a source 23s formed on the top. When viewed in plan as shown in FIGS. 3 to 5, the channel width of the drive transistor 23 is widened because the drive transistor 23 is provided in a comb shape. The drain 23d and the source 23s may have a single layer structure or a stacked structure of two or more layers.

  Note that since the holding transistor 22 has the same layer structure as that of the driving transistor 23, a cross-sectional view of the holding transistor 22 is omitted. In any of the subpixels Pr, Pg, and Pb, the switch transistor 21, the holding transistor 22, and the driving transistor 23 have the same layer structure.

  Next, the layer structure of the capacitor 24 will be described with reference to FIGS. The capacitor 24 is composed of a lower layer electrode 24A formed on the insulating substrate 2 and an upper layer electrode 24B facing the lower layer electrode 24A with the gate insulating film 31 interposed therebetween. The capacitor 24 has the same layer structure in any of the subpixels Pr, Pg, and Pb.

  As shown in FIG. 3, a connection line 96 is formed for each pixel 3 between the insulating substrate 2 and the gate insulating film 31. In plan view, the connection line 96 extends from the red subpixel Pr to the blue subpixel Pb vertically in each pixel 3.

  Next, the relationship among the layers of the transistors 21 to 23 and the capacitor 24 and the signal line Y, the scanning line X, and the supply line Z will be described with reference to FIGS.

  Connection line 96, gate 21g of switch transistor 21 of all subpixels Pr, Pg, Pb, gate 22g of holding transistor 22, gate 23g of drive transistor 23, lower electrode 24A of capacitor 24, and all signal lines Yr, Yg, Yb is formed by patterning the same conductive film formed on the entire surface of the insulating substrate 2 by photolithography and etching. In the following description, the connection line 96, the gate 21g of the switch transistor 21, the gate 22g of the holding transistor 22, the gate 23g of the drive transistor 23, the electrode 24A of the capacitor 24, and the conductive film that is the source of the signal lines Yr, Yg, Yb are gated. This is called a layer.

  The gate insulating film 31 is an insulating film common to the switch transistor 21, the holding transistor 22, the driving transistor 23, and the capacitor 24 of all the subpixels Pr, Pg, and Pb, and is formed over the entire surface. Therefore, the gate insulating film 31 covers the gate 21g of the switch transistor 21, the gate 22g of the holding transistor 22, the gate 23g of the drive transistor 23, the lower layer electrode 24A of the capacitor 24, and the signal lines Yr, Yg, Yb.

  The drain 21d and source 21s of the switch transistor 21 of all the subpixels Pr, Pg, and Pb, the drain 22d and source 22s of the holding transistor 22, the drain 23d and source 23s of the driving transistor 23, the upper layer electrode 24B of the capacitor 24, and all the scans. The line X and the supply line Z are formed by patterning the same conductive film formed on the entire surface of the gate insulating film 31 by a photolithography method and an etching method. In the following, the drain 21d and source 21s of the switch transistor 21, the drain 22d and source 22s of the holding transistor 22, the drain 23d and source 23s of the driving transistor 23, the upper layer electrode 24B of the capacitor 24, the source of the scanning line X and the supply line Z This conductive film is called a drain layer.

  One contact hole 92 per pixel 3 is formed at a position overlapping the scanning line X of the gate insulating film 31, and the gate 21g of the switch transistor 21 and the gate 22g of the holding transistor 22 of the subpixels Pr, Pg, and Pb are in contact with each other. It is electrically connected to the scanning line X through the hole 92. One contact hole 94 is formed at a position overlapping the signal line Y of the gate insulating film 31 for each subpixel P of one dot, and the source 21s of the switch transistor 21 is the contact hole 94 in any subpixel Pr, Pg, Pb. To the signal line Y. One contact hole 93 is formed for each dot subpixel P at a position overlapping the lower electrode 24A of the gate insulating film 31, and the source 22s of the holding transistor 22 is connected to the drive transistor 23 in any subpixel Pr, Pg, Pb. It is electrically connected to the gate 23g and the lower layer electrode 24A of the capacitor 24.

  In the red subpixel Pr, the drain 22d of the holding transistor 22 and the drain 23d of the driving transistor 23 are provided integrally with the supply line Z. On the other hand, in the green subpixel Pg and the blue subpixel Pb, both the drain 22d of the holding transistor 22 and the drain 23d of the driving transistor 23 are provided separately from the supply line Z. Therefore, the drain 22d of the holding transistor 22 and the drain 23d of the driving transistor 23 of the green subpixel Pg and the blue subpixel Pb are electrically connected to the supply line Z as follows.

  That is, one connection line 96 per pixel 3 is provided so as to cut the pixel 3 vertically. The connection line 96 is formed by patterning the gate layer and is covered with the gate insulating film 31. A contact hole 97 is formed at a portion where the supply line Z and the connection line 96 of the gate insulating film 31 overlap each other, and the connection line 96 is electrically connected to the supply line Z through the contact hole 97. In the green subpixel Pg, a contact hole 98 is formed at a position where the connection line 96 of the gate insulating film 31 and the drain 23d of the drive transistor 23 overlap, and the connection line 96 and the drive transistor 23 are connected via the contact hole 98. The drain 23d is conductive. In the blue subpixel Pb, the contact hole 99 is formed at a position where the connection line 96 of the gate insulating film 31 and the drain 23d of the drive transistor 23 overlap, and the connection line 96 and the drain of the drive transistor 23 are connected via the contact hole 99. 23d is conducting. As described above, in both the green subpixel Pg and the blue subpixel Pb, the drain 22d of the holding transistor 22 and the drain 23d of the drive transistor 23 are electrically connected to the supply line Z and the power supply wiring 90 through the connection line 96.

  The switch transistors 21, the holding transistors 22 and the drive transistors 23 of all the subpixels Pr, Pg, and Pb, and all the scanning lines X and supply lines Z are protective insulating films such as silicon nitride or silicon oxide formed on the entire surface. 32. In addition, although mentioned later for details, the protective insulating film 32 is divided | segmented into the rectangular shape in the location which overlaps with the scanning line X and the supply line Z. FIG.

  A planarizing film 33 is laminated on the protective insulating film 32, and a laminated structure from the insulating substrate 2 to the planarizing film 33 is referred to as a transistor array substrate 50. The flattening film 33 eliminates unevenness caused by the switch transistor 21, the holding transistor 22, the driving transistor 23, the scanning line X, and the supply line Z. That is, the surface of the planarizing film 33 is flat. The planarizing film 33 is obtained by curing a photosensitive insulating resin such as polyimide, and the planarizing film 33 has an insulating property like the protective insulating film 32. In addition, although mentioned later for details, the planarization film | membrane 33 is divided | segmented into the rectangular shape in the location which overlaps with the scanning line X and the supply line Z. FIG.

  When the display panel 1 is used as a bottom emission type, that is, when the insulating substrate 2 is used as a display surface, a transparent material is used for the gate insulating film 31, the protective insulating film 32, and the planarizing film 33.

  A groove 34 along the supply line Z is formed in a portion of the protective insulating film 32 and the planarizing film 33 that overlaps each supply line Z. Further, the scanning line X of the protective insulating film 32 and the planarizing film 33 is provided on each scanning line X. A groove 35 along the scanning line X is recessed in the overlapping portion. The protective insulating film 32 and the planarizing film 33 are divided into rectangular shapes by the grooves 34 and 35, the supply line Z is at the bottom of the groove 34, and the scanning line X is at the bottom of the groove 35. A power supply wiring 90 is buried in the groove 34, and the power supply wiring 90 is electrically connected by being stacked on the supply line Z in the groove 34. A selection wiring 89 is buried in the groove 35, and the selection wiring 89 is electrically connected by being stacked on the scanning line X in the groove 35.

  The lower layer portion of the power supply wiring 90 and the selection wiring 89 are formed by electrolytic plating using the supply line Z exposed by the groove 34 and the scanning line X exposed by the groove 35 as the base electrode, respectively. It is sufficiently thicker than the line Y, the scanning line X, and the supply line Z. Both the selection wiring 89 and the lower layer portion of the power supply wiring 90 preferably include at least one of copper, aluminum, gold, and nickel.

  A plurality of subpixel electrodes 20 a are arranged in a matrix on the surface of the planarizing film 33, that is, on the surface of the transistor array substrate 50. Specifically, the subpixel electrodes 20a of the red subpixel Pr are arranged in a line along the supply line Z between the supply line Z and the common wiring 91A, and the subpixel electrode 20a of the green subpixel Pg is arranged in the common wiring 91A. Between the scanning line X and the scanning line X, the sub-pixel electrodes 20a of the blue sub-pixels Pb are arranged in a line along the scanning line X between the scanning line X and the supply line Z. It is arranged. These subpixel electrodes 20a are obtained by patterning a transparent conductive film formed on the entire surface of the planarizing film 33 by a photolithography method or an etching method.

The subpixel electrode 20 a is an electrode that functions as an anode of the organic EL element 20. That is, it is preferable that the work function of the subpixel electrode 20a is relatively high and holes are efficiently injected into the organic EL layer 20b described later. The subpixel electrode 20a is formed of, for example, tin-doped indium oxide (ITO), zinc-doped indium oxide, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), or cadmium-tin oxide (CTO). ).

  One contact hole 88 for each dot subpixel P is formed at a position overlapping the subpixel electrode 20a of the planarization film 33 and the protective insulating film 32, and a conductive pad is embedded in the contact hole 88. In any subpixel Pr, Pg, Pb, the subpixel electrode 20a is electrically connected to the upper layer electrode 24B of the capacitor 24, the drain 21d of the switch transistor 21 and the source 23s of the drive transistor 23.

  When this display panel 1 is used as a bottom emission type, the subpixel electrode 20a is transmissive to visible light. On the other hand, when the display panel 1 is used as a top emission type, that is, when the opposite side of the insulating substrate 2 is used as a display surface, conductive and visible light is interposed between the subpixel electrode 20a and the planarizing film 33. A reflective film having high reflectivity may be formed, or the subpixel electrode 20a itself may be a reflective electrode.

  As shown in FIG. 6, the subpixel electrode 20 a is patterned by etching the transparent conductive film that is the basis of the subpixel electrode 20 a, but one of the transparent conductive films is also formed on the selection wiring 89. The part 51 remains.

  A row of the subpixel electrodes 20a of the red subpixel Pr in the horizontal direction on the surface of the planarizing film 33, that is, the surface of the transistor array substrate 50, and a row of the subpixel electrodes 20a of the green subpixel Pg adjacent to this row An insulating line 61 parallel to the scanning line X is formed between them. The row of the subpixel electrode 20a of the green subpixel Pg in the horizontal direction on the surface of the planarizing film 33, that is, the surface of the transistor array substrate 50, and the row of the subpixel electrode 20a of the blue subpixel Pb adjacent to this row In the meantime, an insulating line 62 parallel to the scanning line X is formed so as to cover the selection wiring 89 and the remaining portion 51 of the transparent conductive film in the upper layer. The insulating line 61 and the insulating line 62 are made of silicon nitride or silicon oxide.

  On the insulating line 61, a common wiring 91A narrower than the insulating line 61 is stacked, and on the insulating line 62, a common wiring 91B narrower than the insulating line 62 is stacked. Since the common wires 91A and 91B are formed by an electroless plating method, the common wires 91A and 91B are sufficiently thicker than the signal lines Y, the scanning lines X, and the supply lines Z, and are protruded from the surface of the planarizing film 33. Yes. The common wires 91A and 91B preferably include at least one of copper, aluminum, gold, and nickel. The groove 34 that opens the planarizing film 33 and the protective insulating film 32 opens to the insulating line 60 formed together with the insulating line 61 and the insulating line 62, and the upper layer portion (above the lower layer portion) of the power supply wiring 90. Are formed by electroless plating together with the common wirings 91A and 91B, and the lower layer portion of the power supply wiring 90 is formed by electrolytic plating together with the selection wiring 89 as described above. That is, the thickness of the power supply wiring 90 is the thickness of the selection wiring 89 plus the thickness of the common wirings 91A and 91B. That is, the power supply wiring 90 is thicker than the selection wiring 89 and thicker than the common wirings 91A and 91B. As a result, the power supply wiring 90 is embedded in the groove 34 and protruded from the surface of the planarizing film 33.

  Liquid repellent conductive layers 55A and 55B having water repellency and oil repellency are formed on the surfaces of the common wirings 91A and 91B, respectively. In the liquid repellent conductive layers 55A and 55B, the hydrogen atom (H) of the thiol group (—SH) of triazyltrithiol represented by the following chemical formula (1) is reduced and released, and the sulfur atom (S) is a common wiring. It is oxidized and adsorbed on the surfaces of 91A and 91B.

  The liquid repellent conductive layers 55A and 55B are monomolecular layers. That is, the liquid-repellent conductive layers 55A and 55B are films composed of a single layer of molecules in which triazyltrithiol molecules are regularly arranged on the surfaces of the common wirings 91A and 91B. Therefore, the liquid-repellent conductive layers 55A and 55B are extremely low. Resistive and conductive. In addition, in order to make water repellency and oil repellency remarkable, instead of triazyltrithiol, one obtained by substituting one or two thiol groups of triazyltrithiol with a fluorinated alkyl group may be used.

  A hydrophobic insulating film 54 having water and oil repellency is formed on the surface of the power supply wiring 90. The hydrophobic insulating film 54 is made of a fluororesin electrodeposition paint electrodeposited on the power supply wiring 90, and is formed by electrodeposition coating.

  An organic EL layer 20b of the organic EL element 20 is formed on the subpixel electrode 20a. The organic EL layer 20b is a light-emitting layer in a broad sense, and the organic EL layer 20b contains a light-emitting material (phosphor) that is an organic compound. The organic EL layer 20b has a two-layer structure in which a hole transport layer and a narrow light-emitting layer are sequentially stacked from the subpixel electrode 20a. The hole transport layer is made of PEDOT (polythiophene) which is a conductive polymer and PSS (polystyrene sulfonic acid) which is a dopant, and the light-emitting layer in a narrow sense is made of a polyfluorene-based light-emitting material.

  In the case of the red subpixel Pr, the organic EL layer 20b emits red light, in the case of the green subpixel Pg, the organic EL layer 20b emits green light, and in the case of the blue subpixel Pb, the organic EL layer 20b. 20b emits blue light.

  The organic EL layer 20b is provided independently for each subpixel electrode 20a, and when viewed in plan, a plurality of organic EL layers 20b are arranged in a matrix. Since the red sub-pixels Pr are arranged in one row along the horizontal direction, the sub-pixel electrodes 20a of the plurality of red sub-pixels Pr arranged in one row along the horizontal direction are strip-shaped along the horizontal direction. It may be covered with a long common red light emitting organic EL layer 20b. The subpixel electrodes 20a of a plurality of green subpixels Pg arranged adjacently in the horizontal direction may be covered with a common green light emitting organic EL layer 20b that is elongated in a strip shape along the horizontal direction. The subpixel electrodes 20a of a plurality of blue subpixels Pb arranged adjacently in the horizontal direction may be covered with a common blue-emitting organic EL layer 20b that is elongated in a strip shape along the horizontal direction.

  The organic EL layer 20b is formed by a wet coating method (for example, an inkjet method) after the liquid repellent conductive layers 55A and 55B and the hydrophobic insulating film 54 are formed. In this case, the organic compound-containing liquid is applied to the subpixel electrode 20a, but the liquid repellent conductive layers 55A and 55B or the hydrophobic insulating film 54 are provided between the subpixel electrodes 20a adjacent in the horizontal direction. The organic compound-containing liquid applied to the electrode 20a does not leak to the adjacent subpixel electrode 20a. Therefore, the organic EL layer 20b can be applied for each color by a wet coating method.

  Further, since the organic compound-containing liquid applied to the subpixel electrode 20a does not become thick around the subpixel electrode 20a due to the water and oil repellency of the liquid repellent conductive layers 55A and 55B or the hydrophobic insulating film 54, the organic EL layer 20b can be formed with a uniform film thickness.

  In addition to the two-layer structure, the organic EL layer 20b may have a three-layer structure that becomes a hole transport layer, a narrow light-emitting layer, and an electron transport layer in order from the subpixel electrode 20a, or a narrow light-emitting layer. It may be a single layer structure composed of the above, or a laminated structure in which an electron or hole injection layer is interposed between appropriate layers in these layer structures, or another laminated structure.

  On the organic EL layer 20b, a counter electrode 20c that functions as a cathode of the organic EL element 20 is formed. The counter electrode 20c is a common electrode formed in common to all the subpixels Pr, Pg, and Pb, and is formed on the entire surface. By forming the counter electrode 20c on the entire surface, the counter electrode 20c covers the common wiring 91 with the liquid repellent conductive layers 55A and 55B interposed therebetween. Therefore, as shown in the circuit diagram of FIG. 2, the counter electrode 20 c is electrically connected to the common wiring 91. On the other hand, since the insulating line 61 is formed on the selection wiring 89 and the power supply wiring 90 is coated with the hydrophobic insulating film 54, the counter electrode 20 c is insulated from both the selection wiring 89 and the power supply wiring 90. Has been.

  The counter electrode 20c is made of a material having a work function lower than that of the subpixel electrode 20a. For example, the counter electrode 20c is made of a simple substance or an alloy containing at least one of magnesium, calcium, lithium, barium, indium, and a rare earth metal. Is preferred. Further, the counter electrode 20c may have a laminated structure in which layers of the above various materials are laminated, and in addition to the above layers of various materials, a metal layer that is not easily oxidized is deposited in order to reduce sheet resistance. Specifically, it may have a laminated structure. Specifically, a low-work function high-purity barium layer provided on the interface side in contact with the organic EL layer 20b, and an aluminum layer provided so as to cover the barium layer; And a laminated structure in which a lower layer is provided with a lithium layer and an upper layer is provided with an aluminum layer. In the case of a top emission structure, the counter electrode 20c may be a transparent electrode in which a thin film having a low work function as described above and a transparent conductive film such as ITO are laminated thereon.

  An inorganic or organic sealing insulating film 56 is formed on the counter electrode 20c. The sealing insulating film 56 is provided to cover the entire counter electrode 20c and prevent the counter electrode 20c from deteriorating.

  Conventionally, an EL display panel having a top emission type structure uses a transparent electrode having a high resistance value such as a metal oxide for at least a part of the counter electrode 20c. However, such a material is sufficiently thick. Otherwise, the sheet resistance will not be sufficiently low, so increasing the thickness will inevitably reduce the transmittance of the organic EL element, and the larger the screen, the less likely it will be a uniform potential in the plane, resulting in lower display characteristics. It was.

  However, in this embodiment, since a plurality of low-resistance common wires 91A and 91B are provided for a sufficient thickness in the horizontal direction, the cathode electrodes of the organic EL elements 20, 20,. It is possible to reduce the overall sheet resistance value and to flow a large current sufficiently and uniformly in the plane. Further, in such a structure, since the common wirings 91A and 91B reduce the sheet resistance as the cathode electrode, it is possible to improve the transmittance by making the counter electrode 20c a thin film. In the top emission structure, the subpixel electrode 20a may be made of a reflective material.

  Since the power supply wiring 90 formed using a thick conductive layer other than the conductive layer when forming the thin film transistors 21 to 23 is provided so as to be electrically connected to the supply line Z, the thin film transistors 21 to 21 are provided. A plurality of organic EL elements 20 due to a voltage drop in a supply line formed of only 23 conductive layers are prevented from delaying until a write current and a drive current, which will be described later, reach a predetermined current value, and driven satisfactorily. Is possible.

  Further, since the selection wiring 89 formed using a thick conductive layer other than the conductive layer when forming the thin film transistor is provided so as to be electrically connected to the scanning line X, only the conductive layer of the thin film transistor is formed. The signal delay due to the voltage drop in the scanning line X can be prevented, and the switch transistor 21 and the holding transistor 22 can be quickly switched and driven satisfactorily.

[Driving method of display panel]
In order to drive the display panel 1 by the active matrix method, it is as shown in the timing chart of FIG. 7 or FIG. In the description of the driving method, the numbers attached to the scanning lines X represent the arrangement order from the top of the display panel 1, the numbers attached to the supply lines Z represent the arrangement order from the top of the display panel 1, and the signal lines Y The numbers subscripted to indicate the arrangement order from the left of the display panel 1. That is, when an arbitrary number of 1 to m is i and an arbitrary number of 1 to n is j, the scanning line X _i is the i-th from the top, and the supply line Z _i is _i from the top. The signal line _Yj is _jth from the left. The subpixel Pi, j represents the subpixel P connected to the scanning line X _i , the supply line Z _i , and the signal line Y _j .

  In the driving method as shown in FIG. 7, the counter electrode 20c and the common wires 91A and 91B are connected to the outside by wiring terminals, and the counter electrode 20c and the common wires 91A and 91B are at a constant common potential while the display panel 1 is driven. Vcom (eg, ground = 0 volts).

Further, the scanning lines X ₁ ~ scan line X _m to the connected selection driver (shift register), the next scanning line sequentially (scan line X _m from the first row to the scan lines X ₁ ~ scan line X _m The scanning lines X _{1 to} X _m are sequentially selected by applying a high level shift pulse to the line X ₁ ). Note that a shift pulse is applied to the selection wiring 89 connected to each of the scanning lines X ₁ to X _m in a row sequence by the selection driver.

In addition, the power supply driver (shift register) is low in order from the first row with respect to the supply line Z ₁ to supply line Z _m so as to synchronize with the selected driver (the supply line Z ₁ is next to the supply line Z _m ). The supply line Z ₁ to the supply line Z _m are sequentially selected by applying a write power supply voltage VL at a level (a level lower than the voltage of the counter electrode 20 c of the organic EL element 20). A low-level write power supply voltage VL is applied to the power supply wiring 90 connected to the supply line Z ₁ to the supply line Z _m in a row sequence by the power supply driver.

In addition, when each scanning line X _{1 to} X _m is selected by the selection driver, the data driver connected to the signal line Y ₁ to signal line Y _n converts the data represented by the magnitude of the current to all signal lines. Write to Y ₁ to signal line Y _n . Specifically, a write current that is a drawing current directed from the signal line Y ₁ to the signal line Y _n toward the data driver is caused to flow to all the signal lines Y ₁ to Y _n by the data driver.

In the selection period of the scan line X _i, because the shift pulse to the scan line X _i and the selection lines 89 is applied, the switch transistor 21 and holding transistor 22 are turned on. In the selection period of the scanning line X _i , the potential on the data driver side is set to be equal to or lower than the write power supply voltage VL output to the power supply wiring 90 and the supply line Z _i , and the write power supply voltage VL is set to be equal to or lower than the common potential Vcom. Has been. Therefore, in the selection period of the scanning line X _i , no flow from the organic EL element 20 to the signal line Y ₁ to the signal line Y _n , so as shown in FIG. The write current flows from the signal line Y ₁ to the signal line Y _n as indicated by the arrow A. In the subpixel P _{i, j} , the power supply wiring 90 and the supply line Z _{i are connected} between the source and drain of the drive transistor 23, the switch transistor 21. A write current directed to the signal line Y _j flows between the source and drain of each other. Thus, the magnitude of the current flowing between the source and drain of the drive transistor 23 is uniquely controlled by the data driver, and the data driver sets the magnitude of the write current according to the gradation input from the outside. To do. While the write current is flowing, the voltage level between the gate 23g and the source 23s of each drive transistor 23 is the magnitude of the write current flowing through the signal line Y ₁ to the signal line Y _n , that is, the drive transistor 23. Regardless of the change in the Vg-Ids characteristic with time, it is forcibly set to match the magnitude of the write current flowing between the drain 23d and the source 23s of the drive transistor 23, and a charge having a magnitude according to the level of this voltage is set. The capacitor 24 is charged, and the magnitude of the write current is converted into the voltage level between the gate 23g and the source 23s of the drive transistor 23.

In the subsequent light emission period, the scanning line X _i and the selection wiring 89 connected thereto are at a low level, and the switch transistor 21 and the holding transistor 22 are turned off. However, the electrode 24A of the capacitor 24 is turned off by the holding transistor 22 in the off state. Even when the voltage of the source 23s of the drive transistor 23 shifts from the selection period to the light emission period, the potential difference between the gate 23g and the source 23s of the drive transistor 23 remains as it is. Maintained. In this light emission period, the supply line Z _i and connected thereto potential of the feed interconnection 90 equals the driving feed voltage VH, the counter electrode 20c and the common line 91A, by becoming higher than the potential Vcom of 91B, Z _i and its supply line A drive current flows from the connected power supply wiring 90 to the organic EL element 20 through the drive transistor 23 in the direction of arrow B, and the organic EL element 20 emits light. Since the magnitude of the drive current depends on the voltage level between the gate 23g and the source 23s of the drive transistor 23, the magnitude of the drive current in the light emission period is equal to the magnitude of the write current (extraction current) in the selection period. Become.

  Another active matrix driving method for the display panel 1 is as follows. That is, a constant common potential Vcom (for example, ground = 0 volts) of the counter electrode 20c and the power supply wiring 90 is maintained.

Further, as shown in FIG. 8, a clock signal is output to the power supply wiring 90 and the supply lines Z ₁ to Z _m by the oscillation circuit. When the clock signal is at a low level, the voltage level of the power supply wiring 90 and the supply lines Z ₁ to Z _m is equal to or lower than the voltage Vcom of the counter electrode 20c of the organic EL element 20, and the write power supply voltage VL. is there. When the clock signal is at a high level, the voltage level of the power supply wiring 90 and the supply lines Z ₁ to Z _m is higher than the voltage Vcom of the counter electrode 20 c of the organic EL element 20 and is the drive power supply voltage VH.

Further, by applying a high-level shift pulse from the first row to the scanning lines X ₁ to X _m by the selection driver (scanning line X ₁ next to scanning line X _m ), scanning line X ₁ is applied. While sequentially selecting _one to scan line X _m, the clock signal of the oscillation circuit becomes low level when the shift pulse is applied to the scan lines X ₁ through scan line X _m by the selection driver. Note that a shift pulse is also applied to the selection wiring 89 connected to each of the scanning lines X ₁ to X _m by the selection driver.

In addition, when each of the scanning lines X ₁ to X _m is selected by the selection driver, the data driver connected to the signal lines Y ₁ to Y _n converts all the data represented by the magnitude of the current. Write to the signal lines Y ₁ to Y _n . Specifically, a write current that is a drawing current directed from the signal line Y ₁ to the signal line Y _n toward the data driver is caused to flow to all the signal lines Y ₁ to Y _n by the data driver.

In the selection period of the scan line X _i, from the shift pulse to the i-th scanning line X _i is applied, the switch transistor 21 and holding transistor 22 are turned on. In the selection period of the scanning line X _i , the potential on the data driver side is equal to or lower than the low level of the clock signal output to the power supply wiring 90 and the supply lines Z ₁ to Z _m , and the low level of the clock signal is common. It is set below the potential Vcom. Therefore, in the selection period of the scanning line X _i , no flow from the organic EL element 20 to the signal line Y ₁ to the signal line Y _n , so as shown in FIG. The write current flows from the signal line Y ₁ to the signal line Y _n as indicated by the arrow A. In the subpixel P _{i, j} , the power supply wiring 90 and the supply line Z _{i are connected} between the source and drain of the drive transistor 23, the switch transistor 21. A write current directed to the signal line Y _j flows between the source and drain of each other. Thus, the magnitude of the current flowing between the source and drain of the drive transistor 23 is uniquely controlled by the data driver, and the data driver sets the magnitude of the write current according to the gradation input from the outside. To do. While the write current is flowing, the level of the voltage between the gate 23g and the source 23s of the drive transistor 23 is the magnitude of the write current (drawing current) flowing through the signal line Y ₁ to the signal line Y _n , that is, driving. Regardless of the change in the Vg-Ids characteristic of the transistor 23 with time, it is forcibly set to match the magnitude of the write current flowing between the drain 23d and the source 23s of the drive transistor 23, and the magnitude according to the level of this voltage. Is charged in the capacitor 24, and the magnitude of the write current is converted into the voltage level between the gate 23g and the source 23s of the drive transistor 23.

In the subsequent light emission period, the scanning line X _i becomes a low level, and the switch transistor 21 and the holding transistor 22 are turned off. However, the charge on the electrode 24A side of the capacitor 24 is confined by the holding transistor 22 in the off state and floats. Even if the voltage of the source 23s of the drive transistor 23 is modulated when the voltage shifts from the selection period to the light emission period, the potential difference between the gate 23g and the source 23s of the drive transistor 23 is maintained as it is. Of the light emission period, while not a selection period of one row, i.e., the clock signal is the potential of the feed interconnection 90 and supply line Z _i counter electrode 20c and common interconnection 91A of the organic EL element 20, than the potential Vcom of the 91B During a high level, a drive current flows in the direction of arrow B from the higher potential power supply line 90 and the supply line Z _i to the organic EL element 20 through the source and drain of the drive transistor 23, and the organic EL element 20 Emits light. Since the magnitude of the drive current depends on the voltage level between the gate 23g and the source 23s of the drive transistor 23, the magnitude of the drive current in the light emission period is equal to the magnitude of the write current in the selection period. In the light emission period, during the selection period of another row, that is, when the clock signal is at a low level, the potentials of the power supply wiring 90 and the supply line Z _i are equal to or lower than the potential Vcom of the counter electrode 20c and the common wirings 91A and 91B. Therefore, no drive current flows through the organic EL element 20 and no light is emitted.

  In any driving method, the switch transistor 21 functions to turn on (selection period) and off (light emission period) the current between the source 23s of the driving transistor 23 and the signal line Y. The holding transistor 22 is in a state in which a current can flow between the source 23s and the drain 23d of the driving transistor 23 during the selection period, and holds the voltage applied between the gate 23g and the source 23s of the driving transistor 23 during the light emission period. It functions as a thing. Then, when the supply line Z and the power supply line 90 are at a high level during the light emission period, the drive transistor 23 drives the organic EL element 20 by causing a current having a magnitude corresponding to the gradation to flow through the organic EL element 20. It functions as a thing.

As described above, the magnitude of the current flowing through the power supply wiring 90 is the sum of the magnitudes of the drive currents flowing through the (3 × n) organic EL elements 20 connected to the supply line Z _i . When the selection period for moving image driving with the number of pixels is set, the parasitic capacitance of the power supply wiring 90 increases, and in the wiring made of a thin film such as the gate, source, or drain of the thin film transistors 21 to 23 (3 × n) Although the resistance is too high to cause a write current to flow through each organic EL element 20, in this embodiment, the power supply wiring 90 is configured by a conductive layer different from the gate, source, and drain of the thin film transistors 21 to 23, respectively. Therefore, the voltage drop due to the power supply wiring 90 is reduced, and a sufficient write current can be passed without delay even in a short selection period. Since the resistance of the power supply wiring 90 is reduced by increasing the thickness of the power supply wiring 90, the width of the power supply wiring 90 can be reduced. Therefore, in the case of bottom emission, the decrease in pixel aperture ratio can be minimized.

Similarly, the magnitude of the current flowing through the common lines 91A and 91B during the light emission period is the same as the magnitude of the write current flowing through the power supply line 90 during the selection period, but what are the gates, sources and drains of the thin film transistors 21 to 23? Since different conductive layers are used for the common wiring 91, the common wiring 91 can be made sufficiently thick. Therefore, the resistance of the common wiring 91 can be reduced, and the counter electrode 20c itself can be made thinner and higher. Even if the resistance is reached, the voltage of the counter electrode 20c can be made uniform in the plane. Therefore, even if the same voltage is applied to all the subpixel electrodes 20a, the light emission intensity of any organic EL layer 20b becomes substantially equal, and the in-plane light emission intensity can be made uniform. Further, when the display panel 1 is used as a top emission type, the counter electrode 20c can be made thinner, so that light emitted from the organic EL layer 20b is not easily attenuated while being transmitted through the counter electrode 20c. Furthermore, since the common wiring 91 is provided between the subpixel electrodes 20a adjacent in the horizontal direction in plan view, a decrease in the pixel aperture ratio can be minimized.
Since the selection wiring 89 connected to the scanning line X is formed of a conductive layer different from the gate, source, and drain of the thin film transistors 21 to 23, the plurality of switch transistors 21 connected to a predetermined row in the selection period. It is possible to suppress the voltage drop of the selection voltage of the scanning line X due to the parasitic capacitance of the gate and the parasitic capacitance of the gates of the plurality of holding transistors 22 connected to the predetermined row. Therefore, the switch transistor 21 and the holding transistor 22 can be selected without lengthening the selection period.
Note that the power supply wiring 90 causes a predetermined write current to flow through each of the signal lines Y ₁ to Y _n , so that the parasitic capacitance and drive of the holding transistor 22 are driven for each selected subpixel within the selection period. The parasitic capacitance of the transistor 23, the parasitic capacitance of the capacitor 24, the parasitic capacitance of the switch transistor 21 and the parasitic capacitance of the signal line Y must be charged up. The parasitic capacitance of the power supply wiring 90 is larger than the parasitic capacitance of the selection wiring 89. large. For this reason, it is necessary to pass a larger current than the selection wiring 89. However, since the power supply wiring 90 is formed thicker than the selection wiring 89, the power supply wiring 90 has a lower resistance per unit length than the selection wiring 89. Therefore, voltage drop due to parasitic capacitance can be suppressed.

[Width, cross-sectional area and resistivity of power supply wiring and common wiring]
Hereinafter, the width, cross-sectional area, and resistivity of the power supply wiring 90 and the common wirings 91A and 91B of the display panel 1 are defined. Here, when the number of sub-pixels of the display panel 1 is WXGA (768 × 1366), desirable widths and cross-sectional areas of the power supply wiring 90 and the common wirings 91A and 91B are defined. FIG. 9 is a graph showing current-voltage characteristics of the drive transistor 23 and the organic EL element 20 of each subpixel.

  In FIG. 9, the vertical axis represents the magnitude of the write current flowing between the source 23 s and the drain 23 d of one drive transistor 23 or the magnitude of the drive current flowing between the anode and cathode of one organic EL element 20. The axis represents the level of the voltage between the source 23s and the drain 23d of one drive transistor 23 (at the same time, the voltage between the gate 23g and the drain 23d of one drive transistor 23). In the figure, solid line Ids max is a write current and drive current at the maximum luminance gradation (brightest display), and alternate long and short dash line Ids mid is an intermediate luminance between the highest luminance gradation and the lowest luminance gradation. The two-dot chain line Vpo is a threshold value, that is, a pinch-off voltage between the unsaturated region (linear region) and the saturated region of the driving transistor 23, and the three-dot chain line Vds is the driving transistor 23. The write current flowing between the source 23 s and the drain 23 d of the organic EL element 20, and the broken line Iel is the drive current flowing between the anode and the cathode of the organic EL element 20.

  Here, the voltage VP1 is a pinch-off voltage of the driving transistor 23 at the maximum luminance gradation, and the voltage VP2 is a source-drain voltage when a writing current of the maximum luminance gradation flows through the driving transistor 23. VELmax (voltage VP4−voltage VP3) is a voltage between the anode and the cathode when the organic EL element 20 emits light with the driving current of the maximum luminance gradation equal in magnitude to the writing current of the maximum luminance gradation. The voltage VP2 ′ is a source-drain voltage when the driving transistor 23 receives an intermediate luminance gradation write current, and the voltage (voltage VP4′−voltage VP3 ′) is an organic EL element 20 having an intermediate luminance gradation. This is the anode-cathode voltage when light is emitted with a driving current of intermediate luminance gradation having the same magnitude as the writing current.

  In order to drive both the drive transistor 23 and the organic EL element 20 in the saturation region, a value obtained by subtracting (voltage Vcom during the light emission period of the common wiring 91A, 91B) from (voltage VH during the light emission period of the power supply wiring 90). VX satisfies the following formula (1).

      VX = Vpo + Vth + Vm + VEL (1)

  Vth (equal to VP2−VP1 at the maximum luminance) is a threshold voltage of the drive transistor 23, VEL (equal to VELmax at the maximum luminance) is an anode-cathode voltage of the organic EL element 20, and Vm is The allowable voltage is displaced according to the gradation.

  As is apparent from the figure, the higher the luminance gradation of the voltage VX, the higher the voltage (Vpo + Vth) required between the source and drain of the transistor 23 and the voltage VEL required between the anode and cathode of the organic EL element 20. Becomes higher. Therefore, the allowable voltage Vm decreases as the luminance gradation increases, and the minimum allowable voltage Vmin becomes VP3−VP2.

  The organic EL element 20 generally deteriorates with time regardless of the low-molecular EL material and the high-molecular EL material, and increases in resistance. It has been confirmed that the anode-cathode voltage after 10,000 hours is about 1.4 times the initial voltage. That is, the voltage VEL increases with time even at the same luminance gradation. For this reason, the higher the allowable voltage Vm at the beginning of driving, the more stable the operation over a long period of time. Therefore, the voltage VX is set so that the voltage VEL is 8V or higher, more preferably 13V or higher.

  This allowable voltage Vm includes not only the increase in resistance of the organic EL element 20 but also the voltage drop due to the power supply wiring 90.

  When the voltage drop is large due to the wiring resistance of the power supply wiring 90, the power consumption of the display panel 1 is remarkably increased. Therefore, the voltage drop of the power supply wiring 90 is particularly preferably set to 1V or less.

As a result of considering the subpixel width Wp which is the length of one subpixel P in the row direction and the number of subpixels (1366) in the row direction, when the panel size of the display panel 1 is 32 inches or 40 inches, The total length of the power supply wiring 90 is 706.7 mm and 895.2 mm, respectively. Here, when the line width WL of the power supply wiring 90 and the line width WL of the common wirings 91A and 91B are widened, the area of the organic EL layer 20b is structurally reduced, and further, a parasitic capacitance with other wirings is generated. In order to cause a voltage drop, it is desirable that the width WL of the power supply wiring 90 and the line width WL of the common wirings 91A and 91B are respectively suppressed to one fifth or less of the subpixel width Wp. Considering this, when the panel size of the display panel 1 is 32 inches and 40 inches, the width WL is within 34 μm and 44 μm, respectively. In addition, the maximum film thickness Hmax of the power supply wiring 90 and the common wirings 91A and 91B is 1.5 times the minimum processing dimension 4 μm of the transistors 21 to 23, that is, 6 μm in consideration of the aspect ratio. Thus the feed interconnection 90 and common interconnection 91A, the maximum cross-sectional area Smax of 91B 32 inch, 40 inches, respectively 204Myuemu ^2, a 264μm ^2.

  In order to reduce the maximum voltage drop of the power supply wiring 90 and the common wirings 91A and 91B to 1 V or less when such a 32-inch display panel 1 is fully lit so that the maximum current flows, as shown in FIG. Further, the wiring resistivity ρ / cross-sectional area S of each of the power supply wiring 90 and the common wirings 91A and 91B needs to be set to 4.7 Ω / cm or less. FIG. 11 shows the correlation between the cross-sectional area of each of the power supply wiring 90 and the common wirings 91A and 91B of the 32-inch display panel 1 and the current density. Note that the resistivity allowed at the maximum cross-sectional area Smax of the power supply wiring 90 and the common wirings 91A and 91B described above is 9.6 μΩcm for 32 inches and 6.4 μΩcm for 40 inches.

  Then, for the 40-inch display panel 1, in order to reduce the maximum voltage drop of the power supply wiring 90 and the common wirings 91 </ b> A and 91 </ b> B when fully lit so that the maximum current flows, as shown in FIG. The wiring resistivity ρ / cross-sectional area S of each of the power supply wiring 90 and the common wirings 91A and 91B needs to be set to 2.4 Ω / cm or less. FIG. 13 shows the correlation between the cross-sectional area of each of the power supply wiring 90 and the common wirings 91A and 91B of the 40-inch display panel 1 and the current density.

  The failure life MTF that stops operating due to the failure of the power supply wiring 90 and the common wirings 91A and 91B satisfies the following equation (2).

MTF = A exp (Ea / K _b T) / ρJ ² (2)

Ea is the activation _{energy, K b T = 8.617 × 10-} 5 eV, ρ is the feed interconnection 90 and common interconnection 91A, 91B of the resistivity, J is the current density.

The failure life MTF of the power supply wiring 90 and the common wirings 91A and 91B is limited by an increase in resistivity and electromigration. When the power supply wiring 90 and the common wirings 91A and 91B are set to Al (Al alone or an alloy such as AlTi or AlNd) and the MTF is estimated at an operating temperature of 85 ° C. for 10,000 hours, the current density J is 2.1 × 10. ^It must be ⁴ A / cm ² or less. Similarly, when the power supply wiring 90 and the common wirings 91A and 91B are set to Cu, it is necessary to set the power supply wiring 90 and the common wirings 91A and 91B to 2.8 × 10 ⁶ A / cm ² or less. It is assumed that materials other than Al in the Al alloy have a lower resistivity than Al.
In consideration of these matters, in the 32-inch display panel 1, the Al-based power supply wiring 90 and the common wirings 91A and 91B are configured so that the power supply wiring 90 and the common wirings 91A and 91B do not fail in 10,000 hours in the fully lit state. Each cross-sectional area S needs to be 57 μm ² or more from FIG. 10, and similarly each cross-sectional area S of the Cu power supply wiring 90 and the common wirings 91A and 91B needs to be 0.43 μm ² or more from FIG. Become.

In the 40-inch display panel 1, the cross-sectional areas S of the Al-based power supply wiring 90 and the common wirings 91A and 91B so that the power supply wiring 90 and the common wirings 91A and 91B do not break down in 10,000 hours in the fully lit state are: From FIG. 12, 92 μm ² or more is required, and similarly, the cross-sectional area S of each of the Cu power supply wiring 90 and the common wirings 91A and 91B is 0.69 μm ² or more from FIG.

Assuming that the Al-based power supply wiring 90 and the common wirings 91A and 91B have an Al-based resistivity of 4.00 μΩcm, the 32-inch display panel 1 has a wiring resistivity ρ / cross-sectional area S of 4.7Ω / Since it is cm or less, the minimum cross-sectional area Smin is 85.1 μm ² . At this time, since the wiring width WL of the power supply wiring 90 and the common wirings 91A and 91B is within 34 μm as described above, the minimum film thickness Hmin of the power supply wiring 90 and the common wirings 91A and 91B is 2.50 μm.

Further, in the 40-inch display panel 1 of the Al-based power supply wiring 90 and the common wirings 91A and 91B, the wiring resistivity ρ / cross-sectional area S is 2.4Ω / cm or less as described above, so the minimum cross-sectional area Smin is 167 μm ² . Become. At this time, since the wiring width WL of the power supply wiring 90 and the common wirings 91A and 91B is within 44 μm as described above, the minimum film thickness Hmin of the power supply wiring 90 and the common wirings 91A and 91B is 3.80 μm.

In the Cu power supply wiring 90 and the common wirings 91A and 91B, when the Cu resistivity is 2.10 μΩcm, the wiring resistivity ρ / cross-sectional area S is 4.7 Ω / cm or less in the 32-inch display panel 1 as described above. Therefore, the minimum cross-sectional area Smin is 44.7 μm ² . At this time, since the wiring width WL of the power supply wiring 90 and the common wirings 91A and 91B is within 34 μm as described above, the minimum film thickness Hmin of the power supply wiring 90 and the common wirings 91A and 91B is 1.31 μm.

Further, in the 40-inch display panel 1 of the Cu power supply wiring 90 and the common wirings 91A and 91B, the wiring resistivity ρ / cross-sectional area S is 2.4Ω / cm or less as described above, so the minimum cross-sectional area Smin is 87.5 μm ^2. It becomes. At this time, since the wiring width WL of the power supply wiring 90 and the common wirings 91A and 91B is within 44 μm as described above, the minimum film thickness Hmin of the power supply wiring 90 and the common wirings 91A and 91B is 1.99 μm.

  From the above, in order to operate the display panel 1 normally and with low power consumption, it is preferable to set the voltage drop in the power supply wiring 90 and the common wirings 91A and 91B to 1 V or less. In the case of a panel of 32 inches in which the power supply wiring 90 and the common wirings 91A and 91B are Al-based, the film thickness H is 2.50 μm to 6 μm, the width WL is 14.1 μm to 34.0 μm, and the resistivity is 4.0 μΩcm to 9. When the power supply wiring 90 and the common wirings 91A and 91B are 40-inch panels made of Al, when the power supply wiring 90 and the common wirings 91A and 91B are Al-based, the film thickness H is 3.80 μm to 6 μm and the width WL is 6 μΩcm. The resistivity is 27.8 μm to 44.0 μm, and the resistivity is 4.0 μΩcm to 9.6 μΩcm.

In general, in the case of the Al-based power supply wiring 90 and the common wirings 91A and 91B, the film thickness H is 2.50 μm to 6 μm, the width WL is 14.1 μm to 44 μm, and the resistivity is 4.0 μΩcm to 9.6 μΩcm.
Similarly, in a 32-inch panel in which the power supply wiring 90 and the common wirings 91A and 91B are Cu, the film thickness H is 1.31 μm to 6 μm, the width WL is 7.45 μm to 34 μm, and the resistivity is 2.1 μΩcm to 9.6 μΩcm. Thus, in a 40-inch panel in which the power supply wiring 90 and the common wirings 91A and 91B are Cu, when the power supply wiring 90 and the common wirings 91A and 91B are Cu-based, the film thickness H is 1.99 μm to 6 μm and the width WL is 14. 6 μm to 44.0 μm, and the resistivity is 2.1 μΩcm to 9.6 μΩcm.

In general, in the case of the Cu power supply wiring 90 and the common wirings 91A and 91B, the film thickness H is 1.31 μm to 6 μm, the width WL is 7.45 μm to 44 μm, and the resistivity is 2.1 μΩcm to 9.6 μΩcm.
Therefore, when an Al-based material or Cu is applied as the power supply wiring 90 and the common wirings 91A and 91B, the power supply wiring 90 and the common wirings 91A and 91B of the display panel 1 have a film thickness H of 1.31 μm to 6 μm and a width WL. 7.45 μm to 44 μm, and the resistivity is 2.1 μΩcm to 9.6 μΩcm.

  As described above, since the common wires 91A and 91B conducted to the counter electrode 20c are formed in a layer different from the electrodes of the transistors 21 to 23, the common wires 91A and 91B can be made thick, The resistance of 91A and 91B can be reduced. Since the low-resistance common wirings 91A and 91B are electrically connected to the counter electrode 20c, the voltage of the counter electrode 20c is made uniform in the plane even when the counter electrode 20c itself is thinned to have a higher resistance. Can do. Therefore, even if the same potential is applied to all the subpixel electrodes 20a, the light emission intensity of any organic EL layer 20b becomes substantially equal, and the in-plane light emission intensity can be made uniform.

  Further, when the display panel 1 is used as a top emission type, the counter electrode 20c can be made thinner, so that light emitted from the organic EL layer 20b is not easily attenuated while being transmitted through the counter electrode 20c. Furthermore, since the selection wiring 89, the power supply wiring 90, and the common wirings 91A and 91B are provided between the subpixel electrodes 20a, it is possible to minimize the decrease in the pixel aperture ratio.

  Further, since the power supply wiring 90 embedded in the groove of the planarization film 33 and the protective insulating film 32 and protruding from the surface from the planarization film 33 is formed in a layer different from the electrodes of the transistors 21 to 23, the power supply wiring 90 can be a thick film, and the resistance of the power supply wiring 90 can be reduced. Since the low-resistance power supply wiring 90 is laminated on the thin film supply line Z, the voltage drop of the supply line Z can be suppressed, and further, the signal delay of the supply line Z and the power supply wiring 90 can be suppressed. For example, if the display panel 1 is enlarged when the power supply wiring 90 is not provided, the in-plane emission intensity unevenness occurs due to the voltage drop of the supply line Z, or there is an organic EL element 20 that does not emit light. There is a fear. However, in this embodiment, since the low-resistance power supply wiring 90 is electrically connected to the supply line Z, unevenness of the in-plane light emission intensity can be suppressed, and the organic EL element 20 that does not emit light can be eliminated.

  Further, since the resistance of the power supply wiring 90 is reduced by increasing the thickness of the power supply wiring 90, the width of the power supply wiring 90 can be reduced. Further, since the narrow power supply wiring 90 is provided between the subpixel electrodes 20a adjacent in the vertical direction in plan view, a decrease in the pixel aperture ratio can be minimized.

  Further, since the selection wiring 89 stacked on the scanning line X is made thick, signal delay of the scanning line X and the selection wiring 89 can be suppressed. That is, when attention is paid to the column of the sub-pixels P in the horizontal direction, the shift pulse becomes high level at the same time without delaying any sub-pixel P. Further, since the resistance of the selection wiring 89 is reduced by increasing the thickness of the selection wiring 89, the width of the selection wiring 89 can be reduced. Therefore, it is possible to minimize the decrease in the pixel aperture ratio.

  Further, since the protruding selection wiring 89 and common wirings 91A and 91B are thickly provided, the organic EL layer 20b can be applied for each color by a wet coating method. Therefore, it is not necessary to separately provide banks for partitioning the subpixels P, and the display panel 1 can be easily manufactured.

[Modification 1]
The present invention is not limited to the above embodiment, and various improvements and design changes may be made without departing from the spirit of the present invention.

  In the above embodiment, the transistors 21 to 23 have been described as N-channel field effect transistors. The transistors 21 to 23 may be P-channel field effect transistors. In that case, in the circuit configuration of FIG. 2, the relationship between the sources 21s, 22s, and 23s of the transistors 21 to 23 and the drains 21d, 22d, and 23d of the transistors 21 to 23 is reversed. For example, when the drive transistor 23 is a P-channel field effect transistor, the drain 23d of the drive transistor 23 is conducted to the subpixel electrode 20a of the organic EL element 20, and the source 23s is conducted to the supply line Z.

[Modification 2]
In the above embodiment, the signal line Y is patterned from the gate layer, but the signal line Y may be patterned from the drain layer. In this case, the scanning line X and the supply line Z are patterned from the gate layer, and the signal line Y is higher than the scanning line X and the supply line Z.

[Modification 3]
In the above embodiment, the organic EL layer 20b of the red sub-pixel Pr, the organic EL layer 20b of the green sub-pixel Pg, and the organic EL layer 20b of the blue sub-pixel Pb are repeatedly arranged for each row in this order. It is not necessary to arrange.

[Modification 4]
In each of the above embodiments, the counter electrode 20c is the cathode of the organic EL element 20, and the subpixel electrode 20a is the anode of the organic EL element 20. However, the counter electrode 20c is the anode of the organic EL element 20, and the subpixel electrode 20a may be used as the cathode of the organic EL element 20.

[Modification 5]
In each of the above embodiments, the drain 22d of the holding transistor 22 is connected to the supply line Z. However, the present invention is not limited to this, and the drain 22d of the holding transistor 22 does not conduct with the drain 23d of the driving transistor 23. X may be connected.
As long as there is consistency, a plurality of the modified examples may be combined.

3 is a plan view showing a pixel 3 of the display panel 1. FIG. 3 is an equivalent circuit diagram of a subpixel P of the display panel 1. FIG. It is the top view which showed the electrode of red subpixel Pr. It is the top view which showed the electrode of the green sub pixel Pg. It is the top view which showed the electrode of the blue sub pixel Pb. FIG. 6 is a cross-sectional view taken along a line VI-VI shown in FIGS. 3 to 5. 3 is a timing chart for explaining a method of driving the display panel 1. 6 is a timing chart for explaining another driving method of the display panel 1. 4 is a graph showing current-voltage characteristics of a driving transistor 23 and an organic EL element 20 of each subpixel. 4 is a graph showing the correlation between the maximum voltage drop of each of the power supply wiring 90 and the common wirings 91A and 91B of the 32-inch display panel 1 and the wiring resistivity ρ / cross-sectional area S. It is a graph which shows the correlation of each cross-sectional area and electric current density of the electric power feeding wiring 90 and common wiring 91A, 91B of a 32-inch display panel 1. FIG. 4 is a graph showing the correlation between the maximum voltage drop of each of the power supply wiring 90 and the common wirings 91A and 91B of the 40-inch display panel 1 and the wiring resistivity ρ / cross-sectional area S. It is a graph which shows the correlation of each cross-sectional area and electric current density of the electric power feeding wiring 90 of the 40-inch display panel 1, and common wiring 91A, 91B.

Explanation of symbols

2 Insulating substrate 20a Subpixel electrode 20b Organic EL layer (light emitting layer)
20c Counter electrode 21 Switch transistor (second transistor)
22 Holding transistor (second transistor)
23 Drive transistor (first transistor)
21s, 22s, 23s Source 21d, 22d, 23d Drain 21g, 22g, 23g Gate 32 Protective insulating film (insulating film)
33 Planarization film (insulating film)
34 Groove 90 Power supply wiring Pr Red subpixel Pg Green subpixel Pr Blue subpixel

Claims (8)

A substrate,
A driving transistor provided for each subpixel on the substrate;
One of a source and a drain is electrically connected to one of a source and a drain of the driving transistor, and a switch transistor provided for each subpixel on the substrate;
One of the source and drain is conducted to the other of the source and drain of the driving transistor, and the other of the source and drain is conducted to the gate of the driving transistor, and is provided for each subpixel on the substrate. Holding transistor,
An insulating film formed to cover the driving transistor, the switch transistor, and the holding transistor, and having a plurality of grooves;
Wherein the projecting manner from the insulating film together when it is buried in each groove, electrically connected to the other of the source and drain of the driving transistor, the driving transistor, the switching transistor and a gate of the holding transistor, the source and drain A power supply wiring formed by a different conductive layer from
A sub-pixel electrode provided in a matrix for each sub-pixel on the insulating film and electrically connected to one of a source and a drain of the driving transistor;
A light emitting layer formed on an upper surface of the subpixel electrode;
A counter electrode formed to cover the light emitting layer;
A selection wiring for selecting the switch transistor and the holding transistor, which is a groove different from the groove in which the power supply wiring of the insulating film is embedded, and is embedded in the groove formed in the insulating film;
A common wiring connected to the counter electrode;
Equipped with a,
The power supply wiring has a lower layer formed with the selection wiring and an upper layer formed with the common wiring .   The display panel according to claim 1, wherein the sub-pixel electrodes are arranged along the power supply wiring. The display panel according to claim 1 , wherein the power supply wiring is thicker than the selection wiring. The display panel according to claim 1 , wherein the power supply wiring is thicker than the common wiring. The power supply wiring, the driving transistor, the switching transistor and a gate of the holding transistor, the source or the preceding claims, characterized in that it is laminated to the exposed supply lines by patterned and the groove with drain 4 The display panel according to any one of the above. A substrate,
A light emitting device provided on the substrate;
A first transistor connected to one electrode of the light emitting element and supplying a drive current;
A second transistor for controlling the first transistor;
A selection wiring for selecting the second transistor formed by a conductive layer different from the gate, source and drain of the second transistor;
A lower layer is formed together with the selection wiring, an upper layer is formed on the lower layer , connected to the first transistor, and a power supply wiring having a lower resistance per unit length than the selection wiring,
A common line formed together with the upper layer of the power supply line and connected to the other electrode of the light emitting element;
A display panel comprising: The display panel according to claim 6 , wherein the second transistor is a holding transistor that holds a voltage applied between a gate and a source of the first transistor. A signal line,
The display panel according to claim 6 , wherein the second transistor is a switch transistor that causes a write current to flow from the first transistor to the signal line.

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