JP5212405B2 - Display panel - Google Patents

Description

  The present invention relates to a display panel using light emitting elements as subpixels.

  As described in Patent Document 1, an organic electroluminescence element as a light emitting element has a laminated structure in which an anode, an electroluminescence layer (hereinafter referred to as an EL layer), and a cathode are laminated on a substrate in this order. When a voltage is applied between the cathode and the cathode, holes and electrons are injected into the EL layer, and electroluminescence occurs in the EL layer. An electroluminescence element designed to transmit light and display through a substrate on which an organic electroluminescence element is provided is referred to as a bottom emission type, whereas it is opposite to a substrate on which an organic electroluminescence element is provided. An electroluminescence element designed to emit light from the side to the outside is called a top emission type.

  In an active matrix drive type display panel, one or a plurality of thin film transistors are provided for each pixel, and the organic electroluminescence element emits light by the thin film transistors. For example, in the display panel described in Patent Document 1, two thin film transistors are provided for each pixel. When manufacturing an active matrix display panel, a transistor array substrate in which thin film transistors are patterned for each pixel is manufactured, and then an organic electroluminescence element is patterned on the surface of the transistor array substrate for each pixel. The reason why the organic electroluminescence element is patterned after the thin film transistor is that the temperature at which the thin film transistor is patterned exceeds the heat resistance temperature of the organic electroluminescence element.

  Since the thin film transistor is patterned for each pixel, when the plurality of organic electroluminescence elements are patterned in a matrix, the lower-layer subpixel electrode connected to the thin film transistor is patterned independently for each pixel. On the other hand, the counter electrode is formed on the entire surface as a common electrode common to all organic electroluminescence elements.

JP-A-8-330600

  By the way, when the counter electrode is formed, the EL layer may be damaged due to thermal factors or chemical factors. Therefore, in order to suppress the damage of the EL layer, it is possible to shorten the film formation time of the counter electrode as much as possible. It is conceivable that the counter electrode becomes thinner when the counter electrode deposition time is shortened. In addition, when the organic electroluminescence element is a top emission type, it is desired that the counter electrode be formed as thin as possible so that light emitted from the EL layer is not attenuated as much as possible during transmission through the counter electrode.

  However, as the counter electrode becomes thinner, the sheet resistance of the counter electrode becomes higher. Due to the increase in resistance of the counter electrode, the voltage of the counter electrode does not become uniform in the plane, and the voltage level difference becomes noticeable in the plane. Appears. That is, since the counter electrode is formed on the entire surface as a common electrode, even if the same potential is applied to all the subpixel electrodes, the emission intensity differs for each organic electroluminescent element, and the in-plane The emission intensity is not uniform.

  Accordingly, the present invention has been made to solve the above-described problems, and an object thereof is to make the voltage of the counter electrode uniform in the plane.

In order to solve the above problems, the display panel of the present invention is
A transistor array substrate in which a plurality of subpixels are two-dimensionally arranged on one surface side, and a transistor is provided for each subpixel;
The one surface side of the transistor array substrate is provided in parallel with each other along the row direction, and a power supply voltage for operating the transistors is supplied, and the current paths of the transistors in each of the plurality of subpixels are supplied. A plurality of first power supply wirings electrically connected to one end;
A first insulating film provided on the one surface side of the transistor array substrate and covering each of the transistors and the plurality of first power supply wirings of the plurality of sub-pixels;
A plurality of second power supply lines provided in parallel to each other along the column direction on the first insulating film and electrically connected to the first power supply lines ;
A second insulating film covering a surface of the plurality of second power supply wirings;
Between each of the second power supply lines , formed on the upper surface of the first insulating film, arranged along each of the second power supply lines , provided for each subpixel, and at the other end of the current path of the transistor connected, and a plurality of sub-pixel electrodes,
A light emitting layer formed on each of the subpixel electrodes;
A counter electrode that covers the light emitting layer on the plurality of subpixel electrodes and covers the plurality of second power supply wirings via the second insulating film ;
A common line provided on the upper surface of the one surface side of the counter electrode on the second power supply line and electrically connected to the counter electrode;
With
The plurality of second power supply wirings are formed such that a height from an upper surface of the first insulating film is higher than a height of each subpixel electrode from an upper surface of the first insulating film. Yes,
The common wiring is formed thicker than the thickness of the counter electrode,
The plurality of first power supply wirings and the plurality of second power supply wirings correspond to each of the plurality of subpixels in a plan view in an area where the plurality of subpixels of the transistor array substrate are two-dimensionally arranged. Intersecting at a plurality of locations, and at each intersecting location, they are electrically connected to each other through a contact hole provided in the first insulating film .

Preferably, the second insulating film has water repellency and oil repellency.

Good Mashiku, the common wiring is opaque to the emitted light of the light emitting layer.

Preferably, the one surface of the transistor array substrate, wherein provided on the lower surface side of the first insulating film, along the column direction, a plurality of signal lines arranged parallel to each other, said plurality of The second power supply wiring overlaps with the plurality of signal lines in plan view .

According to the present invention, the second power feeding is performed via the insulating film on the first power feeding wiring that is electrically connected to one end of the current path of the transistor of each subpixel and is supplied with the power supply voltage for operating the transistor. Since the wiring is formed and the first power supply wiring and the second power supply wiring are conductive, the electric resistance of the power supply wiring for supplying the power supply voltage to the transistor is reduced and applied to the transistor of each subpixel. The power supply voltage can be made uniform. Further , since the common wiring is formed on the counter electrode, the voltage of the counter electrode can be made uniform in the plane even if the counter electrode itself has a high resistance. Further, since the counter electrode can be made thinner, the light emitted from the light emitting layer is not easily attenuated during transmission through the counter electrode.

  Further, if the common wiring formed on the counter electrode is patterned separately from the gate, source, and drain of the transistor, the common wiring can be thickened. Therefore, the resistance of the common wiring can be reduced. Therefore, the voltage of the counter electrode can be made uniform in the plane.

The sub-pixel electrodes, between the second power supply wiring is arranged on the first insulating film along the second feed line, high from the upper surface of each of the second power supply wiring, the first insulating film However, when the light emitting layer is patterned by a wet coating method, adjacent subpixels sandwiching the second power supply wiring are formed. It is possible to prevent the liquid for the light emitting layer from being mixed between the electrodes.

Further, since the common wiring overlaps the second power supply wiring in a plan view and the subpixel electrodes are arranged along the common wiring between the second power supply wirings , the pixel aperture ratio is reduced by the common wiring. Can be suppressed.

  According to the present invention, since the common wiring is formed on the counter electrode, the voltage of the counter electrode can be made uniform in the plane even when the counter electrode itself is thinned to have a higher resistance. . Further, since the counter electrode can be made thinner, the light emitted from the light emitting layer is not easily attenuated during transmission through the counter electrode.

In addition, since the second power supply wiring and the selection wiring are formed separately from the drain, the source, and the gate of the transistor, it is possible to increase the thickness of the power supply wiring and the selection wiring without increasing the width of the second power supply wiring and the selection wiring. In addition, the resistance of the power supply wiring and the selection wiring can be reduced. Therefore, even when a signal is output to the transistor through the power supply wiring and the selection wiring, a voltage drop can be suppressed and a signal delay can be suppressed. Further, since the width of the power supply wiring and the selective defeat is not widened, a decrease in the pixel aperture ratio can be minimized.

  In addition, since the subpixel electrode is arranged along each selection wiring and each power supply wiring between each selection wiring and each power supply wiring and is covered with a hydrophobic insulating film, when the light emitting layer is patterned by the wet coating method In addition, the liquid for the light emitting layer can be prevented from being mixed between the subpixel electrodes adjacent to each other with the hydrophobic insulating film interposed therebetween.

  In addition, since the common wiring overlaps the selection wiring and the power supply wiring in a plan view, a decrease in the pixel aperture ratio can be minimized.

According to the present invention, the second power feeding is performed via the insulating film on the first power feeding wiring that is electrically connected to one end of the current path of the transistor of each subpixel and is supplied with the power supply voltage for operating the transistor. Since the wiring is formed and the first power supply wiring and the second power supply wiring are conductive, the electric resistance of the power supply wiring for supplying the power supply voltage to the transistor is reduced and applied to the transistor of each subpixel. The power supply voltage can be made uniform. Further, the common electrode formed on the counter electrode can make the voltage of the counter electrode uniform in the plane. Therefore, the counter electrode can be made thinner, and the light emitted from the light emitting layer is less likely to attenuate during transmission through the counter electrode.

It is the top view which showed the pixel 3 of the display panel in 1st Embodiment. 3 is an equivalent circuit diagram of a subpixel P. FIG. 3 is a plan view showing electrodes of subpixels P. FIG. It is arrow sectional drawing cut | disconnected in the thickness direction of the insulated substrate 2 along the cutting line IV-IV shown by FIG. It is arrow sectional drawing cut | disconnected in the thickness direction of the insulated substrate 2 along the cutting line VV shown by FIG. It is arrow sectional drawing cut | disconnected in the thickness direction of the insulated substrate 2 along the cutting line VI-VI shown by FIG. It is arrow sectional drawing cut | disconnected in the thickness direction of the insulated substrate 2 along the cutting line VII-VII shown by FIG. It is the schematic plan view which showed the wiring structure of the display panel. FIG. 9 is a timing chart for explaining a method of driving the display panel of FIG. 8. It is the schematic plan view which showed the wiring structure of the display panel. 11 is a timing chart for explaining a method of driving the display panel of FIG. 10. 4 is a graph showing current-voltage characteristics of a driving transistor 23 and an organic EL element 20 of each subpixel. It is a graph which shows the correlation of each maximum voltage drop of the electric power feeding wiring 90 of the 32 inch display panel 1, and the common wiring 91, and wiring resistivity (rho) / sectional area S. FIG. It is a graph which shows the correlation of each cross-sectional area and electric current density of the electric power feeding wiring 90 of the 32-inch display panel 1, and the common wiring 91. FIG. It is a graph which shows the correlation of each maximum voltage drop of the electric power feeding wiring 90 of the 40-inch display panel 1, and the common wiring 91, and wiring resistivity (rho) / sectional area S. FIG. It is a graph which shows the correlation of each cross-sectional area of the electric power feeding wiring 90 of the 40-inch display panel 1, and the common wiring 91, and current density. It is the top view which showed the pixel 3 of the display panel in 2nd Embodiment. 3 is a plan view showing electrodes of subpixels P. FIG. FIG. 18 is a cross-sectional view taken in the direction of the thickness of the insulating substrate 2 along the cutting line XIX-XIX shown in FIG. 17. It is arrow sectional drawing cut | disconnected in the thickness direction of the insulated substrate 2 along the cutting line XX-XX shown by FIG. It is arrow sectional drawing cut | disconnected in the thickness direction of the insulated substrate 2 along the cutting line XXI-XVI shown by FIG. 18 is a cross-sectional view taken in the direction of the arrow along the cutting line XXII-XXII shown in FIG. It is the schematic plan view which showed the arrangement position of the wiring of the display panel in 2nd Embodiment. It is the schematic plan view which showed the arrangement position of the mesh common wiring of the display panel in 2nd Embodiment. It is the schematic plan view which showed the display panel in 2nd Embodiment. It is the top view which showed the pixel 3 of the display panel in 3rd Embodiment. It is arrow sectional drawing cut | disconnected in the thickness direction of the insulated substrate 2 along the cutting line XXVII-XXVII shown by FIG. It is arrow sectional drawing cut | disconnected in the thickness direction of the insulated substrate 2 along the cutting line XXVIII-XXVIII shown by FIG.

  The best mode for carrying out the present invention will be described below with reference to the drawings. However, although various technically preferable limitations for implementing the present invention are given to the embodiments described below, the scope of the invention is not limited to the following embodiments and illustrated examples. Further, in the following description, the term electroluminescence is abbreviated as EL.

[First Embodiment]
[Planar layout of display panel]
FIG. 1 shows a schematic plan view of a pixel 3 of a display panel 1 that operates in an active matrix drive system. In the display panel 1, a pixel 3 includes one red subpixel Pr that emits red light, one green subpixel Pg that emits green light, and one blue subpixel that emits blue light. Pb. Such pixels 3 are arranged in a matrix on the insulating substrate 2. Specifically, when attention is paid to the arrangement in the vertical direction (column direction), a plurality of red subpixels Pr are arranged in a line along the vertical direction, and a plurality of green subpixels Pg are arranged in a line along the vertical direction. Blue subpixels Pb are arranged in a line along the vertical direction. Focusing on the arrangement in the horizontal direction (row direction), a red subpixel Pr, a green subpixel Pg, a red subpixel Pr, a green subpixel Pg, and a blue subpixel Pb, which are repeatedly arranged in this order, are continuously arranged in the horizontal direction. The combination of the blue subpixels Pb is the pixel 3. In the following description, the sub-pixel P represents an arbitrary sub-pixel among the red sub-pixel Pr, the green sub-pixel Pg, and the blue sub-pixel Pb, and the description of the sub-pixel P is a red sub-pixel Pr and a green sub-pixel. This applies to both the pixel Pg and the blue subpixel Pb.

  A signal line Yr is laid between the vertical blue subpixel Pb column and the red subpixel Pr column, and between the vertical red subpixel Pr column and the green subpixel Pg column. The signal line Yg is laid, and the signal line Yb is laid between the column of the green subpixels Pg and the column of the blue subpixels Pb in the vertical direction. Therefore, when attention is paid to the arrangement order in the horizontal direction, the signal lines Yr, the signal lines Yg, and the signal lines Yb are repeatedly arranged in this order. These signal line Yr, signal line Yg, and signal line Yb extend in the vertical direction and are provided in parallel to each other.

  Here, the signal line Yr allows a signal of a predetermined current value to flow sequentially to each of all the red subpixels Pr arranged in a line along the vertical direction, and the signal line Yg extends along the vertical direction. A signal having a predetermined current value is sequentially supplied to each of all the green subpixels Pg arranged in a line, and the signal line Yb is connected to all the blue subpixels Pb arranged in a line along the vertical direction. A signal having a predetermined current value is sequentially supplied to each of them. In the following description, in the case of the red subpixel Pr, the signal line Y represents the signal line Yr in FIG. 1, and in the case of the green subpixel Pg, the signal line Y represents the signal line Yg in FIG. In the case of Pb, the signal line Y represents the signal line Yb in FIG. 1, and the description of the signal line Y applies to any of the signal line Yr, the signal line Yg, and the signal line Yb.

  The common wiring 91 overlaps the signal line Y in plan view, but the signal line Y and the common wiring 91 are electrically insulated.

  A plurality of scanning lines X extend in the horizontal direction, and a plurality of supply lines Z and a plurality of power supply wirings 90 are provided in parallel so as to be staggered with respect to the scanning lines X. In plan view, the power supply wiring 90 overlaps the supply line Z, and the supply line Z and the power supply wiring 90 are electrically connected to each other. Between the scanning line X and the supply line Z, a plurality of pixels 3 are arranged in one row along the horizontal direction. If attention is paid to the arrangement order in the vertical direction, the scanning lines X, the columns of the pixels 3, and the supply lines Z are repeatedly arranged in this order.

  Here, the scanning line X supplies signals to all the sub-pixels Pr, Pg, Pb arranged in one row along the horizontal direction, and the supply line Z is also arranged in all the sub-pixels arranged in one row along the horizontal direction. Signals are supplied to the pixels Pr, Pg, and Pb.

  The colors of the subpixels Pr, Pg, and Pb are determined by the emission color of the organic EL element 20 (shown in FIG. 2 and the like) described later.

[Sub-pixel circuit configuration]
Next, the circuit configuration of the subpixels Pr, Pg, and Pb will be described with reference to the equivalent circuit diagram of FIG. 2 and the schematic plan view of FIG. All of the subpixels Pr, Pg, and Pb are configured in the same manner. For each subpixel P of one dot, the organic EL element 20 and an N-channel amorphous silicon thin film transistor (hereinafter simply referred to as a transistor) 21,22. 23 and a capacitor 24 are provided. Hereinafter, the transistor 21 is referred to as a switch transistor 21, the transistor 22 is referred to as a holding transistor 22, and the transistor 23 is referred to as a drive transistor 23.

Here, there are n signal lines Y, the extending direction of the signal lines Y _{1 to} Y _n is referred to as a vertical direction (column direction), and the extending direction of the scanning lines X _{1 to} X _m is defined as a horizontal direction (row direction). ). In addition, m and n are each a natural number of 2 or more, and n is a multiple of 3, and the number subscripted to the scanning line X represents the order of arrangement from the top in FIG. The numbers represent the order of arrangement from the top in FIG. 8, the numbers subscripted to the signal line Y represent the order of arrangement from the left in FIG. 8, and the front side of the numbers subscripted to the subpixel P represents the order of arrangement from the top. Represents the order of arrangement from the left. That is, when an arbitrary natural number of 1 to m is i and an arbitrary natural number of 1 to n is j, the scanning line X _i is the i-th row from the top, and the supply line Z _i is the left The signal line Y _j is the j-th column from the left, the sub-pixel P _{i, j} is the i-th row from the top, the j-th column from the left, and the sub-pixel P _{i, j} is the scanning line. It is connected to X _i , supply line Z _i and signal line Y _j .

  In the switch transistor 21, the source 21s is conducted to the signal line Y, the drain 21d is conducted to the subpixel electrode 20a of the organic EL element 20, the source 23s of the driving transistor 23 and the upper layer electrode 24B of the capacitor 24, and the gate 21g is held. The transistor 22 is electrically connected to the gate 22g and the scanning line X.

  In the holding transistor 22, the source 22 s is connected to the gate 23 g of the drive transistor 23 and the lower layer electrode 24 A of the capacitor 24, the drain 22 d is connected to the drain 23 d of the drive transistor 23 and the supply line Z, and the gate 22 g is connected to the switch transistor 21. It is electrically connected to the gate 21g and the scanning line X. The drain 22d of the holding transistor 22 may be connected to the scanning line X.

  In the drive transistor 23, the source 23 s is electrically connected to the subpixel electrode 20 a of the organic EL element 20, the drain 21 d of the switch transistor 21 and the upper layer electrode 24 B of the capacitor 24, and the drain 23 d is connected to the drain 22 d of the holding transistor 22 and the supply line Z. The gate 23g is electrically connected to the source 22s of the holding transistor 22 and the lower layer electrode 24A of the capacitor 24.

  The counter electrode 20 c serving as the cathode of the organic EL element 20 is electrically connected to the common wiring 91.

  The sources 21s of the switch transistors 21 of any red subpixel Pr arranged in a line along the vertical direction are conducted to the common signal line Yr, and any of the green subpixels Pg arranged in a line along the vertical direction. The source 21s of the switch transistor 21 is also conducted to the common signal line Yg, and the source 21s of the switch transistor 21 of any blue subpixel Pb arranged in a line along the vertical direction is also conducted to the common signal line Yb. .

  On the other hand, the gates 21g of the switch transistors 21 of any of the subpixels Pr, Pg, and Pb arranged in one row along the horizontal direction are electrically connected to the common scanning line X, and any of the gate transistors 21g arranged in one row along the horizontal direction. The gates 22g of the holding transistors 22 of the subpixels Pr, Pg, and Pb are also conducted to the common scanning line X, and the holding transistors 22 of any of the subpixels Pr, Pg, and Pb of the pixels 3 arranged in one row along the horizontal direction. The drains 22d of the sub-pixels Pr, Pg, Pb of the pixels 3 arranged in a row along the horizontal direction are also connected to the common supply line Z. doing.

[Planar layout of subpixels]
FIG. 3 is a plan view mainly showing electrodes of the subpixel P.

  As shown in FIG. 3, in any of the subpixels Pr, Pg, and Pb, the switch transistor 21 is disposed along the signal line Y in plan view, and the holding transistor 22 is a subpixel near the scanning line X. The driving transistor 23 is disposed along the adjacent signal line Y, and the capacitor 24 is disposed along the driving transistor 23.

  When the entire display panel 1 is viewed in plan and attention is paid only to the switch transistors 21 of all the subpixels Pr, Pg, Pb, a plurality of switch transistors 21 are arranged in a matrix, and all the subpixels Pr, Pg, Focusing only on the holding transistor 22 of Pb, a plurality of holding transistors 22 are arranged in a matrix, and focusing on only the driving transistors 23 of all the subpixels Pr, Pg, Pb, the plurality of driving transistors 23 are arranged in a matrix. Has been.

  In FIG. 1 and FIG. 3, in order to make the transistors 21 to 23 easier to see, the subpixel electrode 20a of the organic EL element 20 is not shown, but the subpixel electrode 20a is perpendicular to the signal line Y adjacent in the horizontal direction. It is arranged in a rectangular area surrounded by the supply line Z and the scanning line X adjacent in the direction. The subpixel electrode 20a is provided in a rectangular shape along the rectangular region. Therefore, when the entire display panel 1 is viewed in plan and attention is paid only to the subpixel electrodes 20a of all the subpixels Pr, Pg, Pb, a plurality of subpixel electrodes 20a are arranged in a matrix.

[Layer structure of display panel 1]
The layer structure of the display panel 1 will be described with reference to FIGS. 4 is a cross-sectional view taken in the direction of the thickness of the insulating substrate 2 along the cutting line IV-IV shown in FIG. 1, and FIG. 5 is a cutting line shown in FIG. FIG. 6 is a cross-sectional view taken along the line V-V in the thickness direction of the insulating substrate 2, and FIG. 6 is cut in the thickness direction of the insulating substrate 2 along the cutting line VI-VI shown in FIG. 1. 7 is a cross-sectional view taken in the direction of the thickness of the insulating substrate 2 along the cutting line VII-VII shown in FIG.

  The display panel 1 is obtained by laminating various layers on an insulating substrate 2 having optical transparency. The insulating substrate 2 is provided in the form of a flexible sheet or is provided in the form of a rigid plate.

  First, the layer structure of the transistors 21 to 23 will be described. As shown in FIG. 4, the switch transistor 21 includes a gate 21g formed on the insulating substrate 2, a gate insulating film 31 formed on the gate 21g, and a semiconductor facing the gate 21g with the gate insulating film 31 interposed therebetween. A film 21c, a channel protective film 21p formed on the central portion of the semiconductor film 21c, and impurity semiconductor films 21a formed on both ends of the semiconductor film 21c so as to be separated from each other and partially overlapping the channel protective film 21p, 21b, a drain 21d formed on the impurity semiconductor film 21a, and a source 21s formed on the impurity semiconductor film 21b. Note that the drain 21d and the source 21s may have a single-layer structure or a stacked structure of two or more layers.

  The driving transistor 23 includes a gate 23g formed on the insulating substrate 2, a gate insulating film 31 formed on the gate 23g, a semiconductor film 23c facing the gate 23g with the gate insulating film 31 interposed therebetween, and a semiconductor film 23c. Impurity protective film 23a, 23b formed on the both ends of the semiconductor film 23c and spaced apart from each other and partially overlapping the channel protective film 23p, and the impurity semiconductor film 23a The drain 23d formed above and the source 23s formed on the impurity semiconductor film 23b. When viewed in plan as shown in FIG. 3, the channel width of the drive transistor 23 is widened because the drive transistor 23 is provided in a U shape. The drain 23d and the source 23s may have a single layer structure or a stacked structure of two or more layers.

  As shown in FIG. 7, the holding transistor 22 includes a gate 22g formed on the insulating substrate 2, a gate insulating film 31 formed on the gate 22g, and a semiconductor facing the gate 22g with the gate insulating film 31 interposed therebetween. A film 22c, a channel protective film 22p formed on the central portion of the semiconductor film 22c, and impurity semiconductor films 22a formed on both ends of the semiconductor film 22c so as to be separated from each other and partially overlapping the channel protective film 22p, 22b, a drain 22d formed on the impurity semiconductor film 22a, and a source 22s formed on the impurity semiconductor film 22b.

  In any of the subpixels Pr, Pg, and Pb, the switch transistor 21, the holding transistor 22, and the driving transistor 23 have the same layer structure.

  Next, the layer structure of the capacitor 24 will be described. As shown in FIG. 4, the capacitor 24 is opposed to the lower layer electrode 24 </ b> A formed on the insulating substrate 2, the gate insulating film 31 formed on the lower layer electrode 24 </ b> A, and the lower layer electrode 24 </ b> A across the gate insulating film 31. The upper layer electrode 24B. The capacitor 24 has the same layer structure in any of the subpixels Pr, Pg, and Pb.

  Next, the relationship among the layers of the transistors 21 to 23 and the capacitor 24 and the signal line Y, the scanning line X, and the supply line Z will be described with reference to FIGS.

  The gate 21g of the switch transistor 21, the gate 22g of the holding transistor 22, the gate 23g of the driving transistor 23, the lower layer electrode 24A of the capacitor 24, and all the signal lines Yr, Yg, Yb of all the subpixels Pr, Pg, Pb are insulated. The conductive film formed on the entire surface of the substrate 2 is formed by patterning by a photolithography method and an etching method. Hereinafter, the gate 21g of the switch transistor 21, the gate 22g of the holding transistor 22, the gate 23g of the drive transistor 23, the lower layer electrode 24A of the capacitor 24, and the conductive film that is the source of the signal lines Yr, Yg, Yb are referred to as a gate layer.

  The gate insulating film 31 is an insulating film common to the switch transistor 21, the holding transistor 22, the driving transistor 23, and the capacitor 24 of all the subpixels Pr, Pg, and Pb, and is formed over the entire surface. Therefore, the gate insulating film 31 covers the gate 21g of the switch transistor 21, the gate 22g of the holding transistor 22, the gate 23g of the drive transistor 23, the lower layer electrode 24A of the capacitor 24, and the signal lines Yr, Yg, Yb.

  The drain 21d and source 21s of the switch transistor 21 of all the subpixels Pr, Pg, and Pb, the drain 22d and source 22s of the holding transistor 22, the drain 23d and source 23s of the driving transistor 23, the upper layer electrode 24B of the capacitor 24, and all the scans. The line X and the supply line Z are formed by patterning a conductive film formed on the entire surface of the gate insulating film 31 by a photolithography method or an etching method. In the following, the drain 21d and source 21s of the switch transistor 21, the drain 22d and source 22s of the holding transistor 22, the drain 23d and source 23s of the driving transistor 23, the upper layer electrode 24B of the capacitor 24, the source of the scanning line X and the supply line Z This conductive film is called a drain layer.

  One contact hole 92 is formed at a position overlapping the scanning line X of the gate insulating film 31 for each subpixel P of one dot. In any of the subpixels Pr, Pg, and Pb, the gate 21g and the holding transistor 22 of the switch transistor 21 are formed. The gate 22g is electrically connected to the scanning line X through the contact hole 92. One contact hole 94 is formed at a position overlapping the signal line Y of the gate insulating film 31 for each subpixel P of one dot, and the source 21s of the switch transistor 21 is the contact hole 94 in any subpixel Pr, Pg, Pb. To the signal line Y. One contact hole 93 is formed at a position overlapping the lower layer electrode 24A of the gate insulating film 31 for each dot subpixel P, and the source 22s of the holding transistor 22 is connected to the drive transistor 23 in any of the subpixels Pr, Pg, Pb. It is electrically connected to the gate 23g and the lower layer electrode 24A of the capacitor 24.

  The switch transistors 21, the holding transistors 22 and the drive transistors 23 of all the subpixels Pr, Pg, and Pb, and all the scanning lines X and the supply lines Z are covered with a protective insulating film 32 formed on the entire surface. In addition, although mentioned later for details, the protective insulating film 32 is divided | segmented into the rectangular shape in the location which overlaps with the supply line Z. FIG.

  A planarization film 33 is laminated on the protective insulating film 32, and unevenness due to the switch transistor 21, the holding transistor 22, the drive transistor 23, the scanning line X, and the supply line Z is eliminated by the planarization film 33. That is, the surface of the planarizing film 33 is flat. The flattened film 33 is preferably a film obtained by curing a photosensitive insulating resin such as polyimide. In addition, although mentioned later for details, the planarization film | membrane 33 is divided | segmented into the rectangular shape in the location which overlaps with the supply line Z. FIG.

  When the display panel 1 is used as a bottom emission type, that is, when the insulating substrate 2 is used as a display surface, a transparent material is used for the gate insulating film 31, the protective insulating film 32, and the planarizing film 33. A stacked structure from the insulating substrate 2 to the planarizing film 33 is referred to as a transistor array substrate 50.

  In the portions of the protective insulating film 32 and the planarizing film 33 that overlap the supply lines Z, a long groove 34 is recessed along the horizontal direction. The protective insulating film 32 and the planarizing film 33 are divided into rectangular shapes by the grooves 34, and the supply lines Z are exposed. A power supply wiring 90 is embedded in the groove 34, and the power supply wiring 90 is stacked on the supply line Z in the groove 34.

  Since the power supply wiring 90 is formed by electrolytic plating using the supply line Z as a base electrode, it is sufficiently thicker than the signal line Yr, signal line Yg, signal line Yb, scan line X, and supply line Z. Furthermore, the thickness of the power supply wiring 90 is substantially equal to the total thickness of the protective insulating film 32 and the planarization film 33, and the surface of the planarization film 33 and the surface of the power supply wiring 90 are substantially flush. The power supply wiring 90 preferably includes at least one of copper, aluminum, gold, or nickel.

A plurality of subpixel electrodes 20 a are arranged in a matrix on the surface of the planarizing film 33, that is, on the surface of the transistor array substrate 50. The subpixel electrode 20 a is an electrode that functions as an anode of the organic EL element 20. That is, it is preferable that the work function of the subpixel electrode 20a is relatively high and holes are efficiently injected into the organic EL layer 20b described later. In addition, the subpixel electrode 20a is transmissive to visible light in the case of bottom emission. As the subpixel electrode 20a, for example, tin-doped indium oxide (ITO), zinc-doped indium oxide, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), or cadmium-tin oxide ( CTO) is the main component.

  When the display panel 1 is used as a top emission type, that is, when the opposite side of the insulating substrate 2 is used as a display surface, conductive and visible light is interposed between the subpixel electrode 20a and the planarizing film 33. A reflective film having high reflectivity may be formed, or the subpixel electrode 20a itself may be a reflective electrode.

  Three contact holes 88 for each subpixel P of one dot are formed in the planarizing film 33 and a portion of the protective insulating film 32 that overlaps the subpixel electrode 20a, and a conductive pad 87 is embedded in the contact hole 88. In any subpixel Pr, Pg, Pb, the subpixel electrode 20a is electrically connected to the upper layer electrode 24B of the capacitor 24, the drain 21d of the switch transistor 21 and the source 23s of the drive transistor 23 through the contact hole 88. The conductive pad 87 is formed together with the power supply wiring 90, and is particularly preferably formed by electrolytic plating using the upper layer electrode 24B as a base electrode.

  These subpixel electrodes 20a are obtained by patterning a conductive film formed on the entire surface of the planarizing film 33 by a photolithography method or an etching method. The conductive line 51 is patterned on the surface of the power supply wiring 90, and the conductive line 51 is patterned together with the subpixel electrode 20a by etching the conductive film that is the source of the subpixel electrode 20a. is there.

  Between these subpixel electrodes 20a, a mesh-like insulating film 52 is patterned so as to surround each subpixel electrode 20a in plan view. The conductive line 51 is covered with an insulating film 52.

  A bank 71 that is sufficiently thicker than the film thickness of the subpixel electrode 20a is provided on a portion of the insulating film 52 that is formed in a grid pattern in the horizontal and vertical directions and that extends in the vertical direction. Yes. That is, the bank 71 is provided in the shape of a ridge extending along the vertical direction, and overlaps the signal lines Yr, Yg, Yb in plan view. Between vertical red subpixel Pr and green subpixel Pg columns, vertical green subpixel Pg and blue subpixel Pb columns, and vertical blue subpixel Pb. A bank 71 is arranged between the first row and the red subpixel Pr row. The bank 71 is made of a photosensitive resin such as polyimide.

  An organic EL layer 20b of the organic EL element 20 is formed on the subpixel electrode 20a. The organic EL layer 20b is a light-emitting layer in a broad sense, and the organic EL layer 20b contains a light-emitting material (phosphor) that is an organic compound. The organic EL layer 20b has a two-layer structure in which a hole transport layer and a narrow light-emitting layer are sequentially stacked from the subpixel electrode 20a. The hole transport layer is made of PEDOT (polythiophene) which is a conductive polymer and PSS (polystyrene sulfonic acid) which is a dopant, and the light-emitting layer in a narrow sense is made of a polyfluorene-based light-emitting material.

  In the case of the red subpixel Pr, the organic EL layer 20b emits red light, in the case of the green subpixel Pg, the organic EL layer 20b emits green light, and in the case of the blue subpixel Pb, the organic EL layer 20b. 20b emits blue light.

  Since the red subpixels Pr are arranged in a line in the vertical direction, a plurality of subpixel electrodes 20a arranged in a line in the vertical direction between the signal lines Yr and Yg are formed in a strip shape along the vertical direction. It is covered with a long common red light emitting organic EL layer 20b. Similarly, a plurality of subpixel electrodes 20a arranged in a line in the vertical direction between the signal line Yg and the signal line Yb are formed by a common green light-emitting organic EL layer 20b that is elongated in a strip shape along the vertical direction. A plurality of sub-pixel electrodes 20a that are covered and arranged in a line in the vertical direction between the signal line Yb and the signal line Yr are formed by a common blue light-emitting organic EL layer 20b that is elongated in a strip shape along the vertical direction. It is covered. In addition, when the organic EL layer 20b is provided independently for each subpixel electrode 20a and seen in a plan view, the plurality of organic EL layers 20b may be arranged in a matrix.

  The organic EL layer 20b is formed by a wet application method (for example, an ink jet method) after the bank 71 is formed. In this case, the organic compound-containing liquid is applied to the subpixel electrode 20a. However, since the bank 71 protrudes from the surface of the transistor array substrate 50 between the subpixel electrodes 20a adjacent in the horizontal direction, The organic compound-containing liquid applied to 20a does not leak to the adjacent subpixel electrode 20a.

  In addition to the two-layer structure, the organic EL layer 20b may have a three-layer structure that becomes a hole transport layer, a narrow light-emitting layer, and an electron transport layer in order from the subpixel electrode 20a, or a narrow light-emitting layer. It may be a single layer structure composed of the above, or a laminated structure in which an electron or hole injection layer is interposed between appropriate layers in these layer structures, or another laminated structure.

  On the organic EL layer 20b, a counter electrode 20c that functions as a cathode of the organic EL element 20 is formed. The counter electrode 20c is a common electrode formed in common to all the subpixels Pr, Pg, and Pb, and is formed on the entire surface. By forming the counter electrode 20c on the entire surface, the bank 71 is also covered with the counter electrode 20c.

  The counter electrode 20c is made of a material having a work function lower than that of the subpixel electrode 20a. For example, the counter electrode 20c is made of a simple substance or an alloy containing at least one of magnesium, calcium, lithium, barium, indium, and a rare earth metal. Is preferred. Further, the counter electrode 20c may have a laminated structure in which layers of the above various materials are laminated, and in addition to the above layers of various materials, a metal layer that is not easily oxidized is deposited in order to reduce sheet resistance. Specifically, it may have a laminated structure. Specifically, a low-work function high-purity barium layer provided on the interface side in contact with the organic EL layer 20b, and an aluminum layer provided so as to cover the barium layer; And a laminated structure in which a lower layer is provided with a lithium layer and an upper layer is provided with an aluminum layer. In the case of a top emission structure, the counter electrode 20c may be a transparent electrode in which a thin film having a low work function as described above and a transparent conductive film such as ITO are laminated thereon.

  On the counter electrode 20c, a common wiring 91 is provided so as to project the sheet resistance of the upper electrode of the organic EL element 20. Since the common wiring 91 overlaps the plurality of banks 71 along the column direction in plan view, the common wiring 91 is formed on the bank 71 with the counter electrode 20c interposed therebetween. Since the counter electrode 20c is in contact with the common wire 91, the counter electrode 20c is electrically connected to the common wire 91 as shown in the circuit diagram of FIG. Since the common wiring 91 group is formed by plating, it is sufficiently thicker than the counter electrode 20c and the electrodes of the transistors 21 to 23. Further, the common wiring 91 group is electrically connected by the lead wiring 95 extending in the horizontal direction in the non-pixel region outside the pixel region, and the lead wiring 95 is electrically connected to the plurality of terminal portions Tc at the peripheral portion of the insulating substrate 2. Yes. The common wiring 91 group and the counter electrode 20c are equipotential by the voltage Vcom applied from the external circuit to the terminal portion Tc. The common wiring 91 group preferably includes at least one of copper, aluminum, gold, and nickel, and all of them are thick enough to be opaque to the light emitted from the organic EL layer 20b.

  A sealing insulating film 56 is formed on the counter electrode 20c. The sealing insulating film 56 is an inorganic film or an organic film that covers the entire counter electrode 20 c and also covers the common wiring 91. Therefore, the deterioration of the common wiring 91 and the counter electrode 20 c is prevented by the sealing insulating film 56.

  When the display panel 1 is used as a top emission type, the counter electrode 20c and the sealing insulating film 56 are made thin, or the counter electrode 20c and the sealing insulating film 56 are made of a transparent material. Visible light transmittance of the electrode 20c and the sealing insulating film 56 is increased.

  Conventionally, an EL display panel having a top emission type structure uses a transparent electrode having a high resistance value, such as a metal oxide, at least a part of the counter electrode corresponding to the counter electrode 20c. Since the sheet resistance will not be sufficiently lowered unless the thickness is increased, the transmittance of the organic EL element is inevitably lowered by increasing the thickness, and the display characteristics are less likely to be uniform in the plane as the screen becomes larger. It was.

  However, in this embodiment, since a plurality of low resistance common wirings 91, 91,... Are provided for sufficient thickness in the vertical direction, the organic EL elements 20, 20,. The sheet resistance value of the entire cathode electrode can be lowered, and a large current can be sufficiently and uniformly supplied in the plane. Further, in such a structure, since the common wirings 91, 91,... Are arranged between the subpixel electrodes 20a, 20a, the sheet resistance of one electrode of the organic EL element 20 is lowered without impairing the pixel area (aperture ratio). Therefore, it is possible to improve the transmittance by making the counter electrode 20c overlapping with the subpixel electrode 20a in plan view as a thin film. In the top emission structure, the subpixel electrode 20a may be made of a reflective material.

  Since the power supply wiring 90 formed using a thick conductive layer other than the gate layer and the drain layer when forming the transistors 21 to 23 is provided so as to be electrically connected to the supply line Z, respectively. Until a write current or a drive current described later reaches a predetermined current value in the plurality of organic EL elements 20 due to a voltage drop in the supply line Z formed only by the gate layer and the drain layer when forming the transistors 21 to 23 It is possible to prevent the delay and to drive well.

  Furthermore, since the power supply wiring 90 is embedded in the groove 34, the thickness of the power supply wiring 90 does not cause a steric hindrance in the horizontal direction, and the organic compound containing the organic EL layer 20 b is formed over the plurality of organic EL elements 20 in the column direction. The film can be formed while the liquid spreads continuously and is partitioned by the bank 71 in the vertical direction.

[Driving method of display panel 1]
In the structure of the first display panel 1, as shown in FIG. 8, the selection driver 111 to which the scanning lines X _{1 to} X _m are connected is disposed on the first peripheral edge of the insulating substrate 2 and electrically connected to each other. A power supply driver 112 to which the insulated power supply wirings 90, 90,... (Supply lines Z _{1 to} Z _m ) are connected is disposed at a second peripheral edge that is a peripheral edge facing the first peripheral edge of the insulating substrate 2. ing. The first display panel 1 is driven by the active matrix method as follows. That is, as shown in FIG. 9, the scanning lines X ₁ to X by the connected selection driver 111 _m, the order from the scanning line X ₁ to scan line X _m (the next scan line X _m scanning lines X ₁₎ The scanning lines X _{1 to} X _m are sequentially selected by sequentially outputting high level shift pulses. In addition, a write power supply voltage VL for applying a write current is applied to the drive transistors 23 connected to the supply lines Z _{1 to} Z _m via the power supply lines 90 during the selection period, and the drive transistors 23 are used during the light emission period. A power supply driver 112 that applies a drive power supply voltage VH for causing a drive current to flow through the organic EL element 20 is connected to each power supply wiring 90. This feeding driver 112, to synchronize the selection driver 111, the counter electrode of the forward (following the supply lines Z ₁ of the supply line Z _m) to the low level (the organic EL element 20 to supply line Z _m from the supply line Z ₁ The supply lines Z _{1 to} Z _m are sequentially selected by sequentially outputting the write power supply voltage VL having a lower level than the voltage of the first voltage. Further, when the selection driver 111 selects each of the scanning lines X _{1 to} X _m , the data driver sends a write current (current signal) that is a write current between the source and drain of the drive transistor 23 in a predetermined row. Through all the signal lines Y _{1 to} Y _n . The counter electrode 20c and the common wiring 91 group are connected to the outside by the lead wiring 95 and the wiring terminal Tc, and are maintained at a constant common potential Vcom (for example, ground = 0 volts).

In each selection period, the potential of the data driver side, feed interconnections 90, 90, ... and the supply lines Z ₁ to Z _m output to the and below the write feed voltage VL the write feed voltage VL below the common potential Vcom Is set to Therefore, at this time, since the organic EL element 20 does not flow to the signal lines Y _{1 to} Y _n , as shown in FIG. 2, a write current (write current) having a current value corresponding to the gradation is indicated by an arrow by the data driver. As shown in A, the signal flows to the signal lines Y _{1 to} Y _n , and in the subpixel P _{i, j} , the power supply wiring 90 and the supply line Z _i pass through the source and drain of the drive transistor 23 and the source and drain of the switch transistor 21. Thus, a write current (write current) directed to the signal line Y _j flows. In this way, the current value of the current flowing between the source and drain of the drive transistor 23 is uniquely controlled by the data driver, and the data driver writes the write current (write current) according to the gradation input from the outside. Set the current value. While the write current (write current) is flowing, i-th row of P _i, 1 to P _i, the voltage between the gate 23g- source 23s of the driving transistor 23 of the _n each signal line Y ₁ to Y _The write current (write current) flowing between the drain 23d and the source 23s of the drive transistor 23 regardless of the current value of the write current (write current) flowing through _n , that is, the change in the Vg-Ids characteristic of the drive transistor 23 with time. The capacitor 24 is forcibly set so as to meet the current value of the current, and the capacitor 24 is charged with a charge having a magnitude according to the level of this voltage, so that the current value of the write current (write current) becomes the gate 23g of the drive transistor 23. -It is converted into the voltage level between the sources 23s. In the subsequent light emission period, the scanning line X _i becomes a low level, and the switch transistor 21 and the holding transistor 22 are turned off. However, the charge on the electrode 24A side of the capacitor 24 is confined by the holding transistor 22 in the off state and floats. Even when the voltage of the source 23s of the drive transistor 23 is modulated when the voltage shifts from the selection period to the light emission period, the potential difference between the gate 23g and the source 23s of the drive transistor 23 is maintained as it is. In this light emission period, the potential of the supply line Z _i and the power supply wiring 90 connected thereto becomes the drive power supply voltage VH, which is higher than the potential Vcom of the counter electrode 20c of the organic EL element 20, thereby connecting to the supply line Z _i and the supply line Z _i. A drive current flows from the power supply wiring 90 to the organic EL element 20 through the drive transistor 23 in the direction of arrow B, and the organic EL element 20 emits light. Since the current value of the drive current depends on the voltage between the gate 23g and the source 23s of the drive transistor 23, the current value of the drive current in the light emission period is equal to the current value of the write current (drawing current) in the selection period.

As shown in FIG. 10, the second display panel 1 has a structure in which a selection driver 111 to which the scanning lines X _{1 to} X _m are connected is arranged on the first peripheral edge of the insulating substrate 2, and the power supply wiring The lead-out wiring 99 formed integrally with the power supply wirings 90, 90,... So as to be electrically connected to each other is a peripheral portion facing the first peripheral portion of the insulating substrate 2. It arrange | positions at the 2nd peripheral part. The routing wiring 99 receives clock signals from both the terminal portion 90d and the terminal portion 90e located at the third peripheral portion and the fourth peripheral portion orthogonal to the first peripheral portion and the second peripheral portion, respectively. .

The active matrix driving method of the second display panel 1 is as follows. That is, as shown in FIG. 11, the external oscillation circuit outputs a clock signal to the power supply wirings 90, 90,... And the supply lines Z _{1 to} Z _m through the terminal portion 90d and the terminal portion 90e through the wiring 99. To do. The scanning lines X ₁ to X _m by sequentially outputting the high-level shift pulse sequentially (the next scan line X _m scanning lines X ₁₎ from the scanning line X ₁ by the selection driver 111 to the scan line X _m Are sequentially selected, but when the selection driver 111 outputs one of the scanning lines X _{1 to} X _m outputting a high level, that is, on-level shift pulse, the clock signal of the oscillation circuit becomes low level. Further, when the selection driver 111 selects each of the scanning lines X _{1 to} X _m , the data driver sends a drawing current (current signal) that is a write current to all the signal lines via the source and drain of the driving transistor 23. Flow from Y _{1 to} Y _n . The counter electrode 20c and the power supply wiring 90 are kept at a constant common potential Vcom (for example, ground = 0 volts).

In the selection period of the scan line X _i, from the shift pulse to the i-th scanning line X _i is output, the switch transistor 21 and holding transistor 22 are turned on. In each selection period, the potential of the data driver side, feed interconnections 90, 90, ... and the low level of the supply lines Z ₁ to Z _m and the clock signal following a low level of the clock signal output to the following common potential Vcom Is set to Therefore, at this time, since the organic EL element 20 does not flow to the signal lines Y _{1 to} Y _n , as shown in FIG. 2, the write current (drawing current) having a current value corresponding to the gradation is indicated by the arrow A by the data driver. As described above, the signal lines Y _{1 to} Y _n flow, and in the subpixels P _{i, j} , from the power supply wiring 90 and the supply line Z _i to between the source and drain of the drive transistor 23 and between the source and drain of the switch transistor 21. A write current (drawing current) toward the signal line Y _j flows. In this way, the current value of the current flowing between the source and drain of the drive transistor 23 is uniquely controlled by the data driver, and the data driver has a write current (drawing current) according to the gradation input from the outside. Set the current value. While the write current (drawing current) is flowing, the voltage between the gate 23g and the source 23s of each driving transistor 23 of the _i- th row P _{i, 1 to} P _{i, n} is the signal line Y _{1 to} Y _n , respectively. Current value of the write current (extraction current) flowing through the transistor 23, that is, the current value of the write current (extraction current) flowing between the drain 23d and the source 23s of the drive transistor 23 regardless of the change with time in the Vg-Ids characteristic of the drive transistor 23. The capacitor 24 is forcibly set to meet the voltage level, the capacitor 24 is charged with a charge, and the current value of the write current (drawing current) is between the gate 23g and the source 23s of the drive transistor 23. Is converted to the voltage level. In the subsequent light emission period, the scanning line X _i becomes a low level, and the switch transistor 21 and the holding transistor 22 are turned off. However, the charge on the electrode 24A side of the capacitor 24 is confined by the holding transistor 22 in the off state and floats. Even when the voltage of the source 23s of the drive transistor 23 is modulated when the voltage shifts from the selection period to the light emission period, the potential difference between the gate 23g and the source 23s of the drive transistor 23 is maintained as it is. During this light emission period, during which the row is not a selection period, that is, the clock signal is high when the potential of the power supply wiring 90 and the supply line Z _i is higher than the potential Vcom of the counter electrode 20 c of the organic EL element 20 and the power supply wiring 90. During the level, the drive current flows in the direction of the arrow B from the higher potential power supply line 90 and the supply line Z _i to the organic EL element 20 through the source and drain of the drive transistor 23, and the organic EL element 20 emits light. . Since the current value of the drive current depends on the voltage between the gate 23g and the source 23s of the drive transistor 23, the current value of the drive current in the light emission period is equal to the current value of the write current (drawing current) in the selection period. Further, in the light emission period, during the selection period of any row, that is, when the clock signal is at a low level, the potential of the power supply wiring 90 and the supply line Z _i is equal to or lower than the potential Vcom of the counter electrode 20c and the power supply wiring 90. Therefore, no drive current flows through the organic EL element 20 and no light is emitted.

  In any driving method, the switch transistor 21 functions to turn on (selection period) and off (light emission period) the current between the source 23s of the driving transistor 23 and the signal line Y. The holding transistor 22 is in a state in which a current can flow between the source 23s and the drain 23d of the driving transistor 23 during the selection period, and holds the voltage applied between the gate 23g and the source 23s of the driving transistor 23 during the light emission period. It functions as a thing. Then, when the supply line Z and the power supply line 90 are at a high level during the light emission period, the drive transistor 23 drives the organic EL element 20 by causing a current having a magnitude corresponding to the gradation to flow through the organic EL element 20. It functions as a thing.

As described above, the magnitude of the current flowing through each of the power supply wirings 90, 90,... Is the sum of the magnitudes of the drive currents flowing through the n organic EL elements 20 connected to the one line of supply lines Z _i . When the selection period for moving image driving with the number of pixels equal to or greater than VGA is set, the parasitic capacitance of each of the power supply wirings 90, 90,... Increases, and the gate electrode or source of a thin film transistor such as the transistors 21 to 23, In the wiring composed of a thin film constituting the drain electrode, the resistance is too high to cause a write current (that is, a drive current) to flow through the n organic EL elements 20, but in this embodiment, the subpixels P _{1,1 to} P _{m ,} the gate electrode and the source of the _n thin film transistors, each feed interconnections so constitute respective feed lines 90, 90, ... of the different conductive layer and the drain electrode 90, 90, ... voltage by Below is reduced to allow flow shorter a selection period without delay sufficient write current (pull-out current). Further, since the resistance of the power supply wirings 90, 90, ... is reduced by increasing the thickness of the power supply wirings 90, 90, ..., the width of the power supply wirings 90, 90, ... can be reduced. Therefore, in the case of bottom emission, the decrease in pixel aperture ratio can be minimized.

Similarly, the magnitude of the drive current flowing through the common wiring 91 during the light emission period is the same as the magnitude of the write current (drawing current) flowing through the power supply wiring 90 during the selection period, but the common wiring 91 includes the subpixel P _{1. , 1 to} P _{m, n} , the conductive layer different from the conductive layer constituting the gate electrode, the source and the drain electrode of the thin film transistor is used, so that the thickness of the common wiring 91 can be reduced. Further, even when the counter electrode 20c itself is thinned to have a higher resistance, the voltage of the counter electrode 20c can be made uniform in the plane. Therefore, even if the same potential is applied to all the subpixel electrodes 20a, the light emission intensity of any organic EL layer 20b becomes substantially equal, and the in-plane light emission intensity can be made uniform. Further, when the EL display panel 1 is used as a top emission type, the counter electrode 20c can be made thinner, so that light emitted from the organic EL layer 20b is not easily attenuated while being transmitted through the counter electrode 20c. Furthermore, since the common wiring 91 is provided between the subpixel electrodes 20a adjacent in the horizontal direction in plan view, a decrease in the pixel aperture ratio can be minimized.

Furthermore, since the common wiring 91 group is disposed above the signal lines Y _{1 to} Y _n disposed in the non-pixel region between the sub-pixel electrodes 20a and 20a, it is not necessary to reduce the area of the sub-pixel electrode 20a.

  In the display panel 1 of the two driving methods described above, in the display panel 1, the power supply wirings 90, 90,... Since the potential is equalized by the clock signal from the external oscillation circuit via the terminal 90d and the terminal portion 90e, current can be promptly supplied from the organic EL elements 20, 20,. .

The common wirings 91, 91,... Of the first and second EL display panels 1 are connected to each other by the lead wirings 95, 95 provided at the third peripheral edge and the fourth peripheral edge of the insulating substrate 2, and the common voltage Vcom. Is applied. Common wiring 91, ... and the lead wiring 95, 95, the scanning lines X ₁ to X _m, the signal lines Y ₁ to Y _n, and is electrically insulated from the supply lines Z ₁ to Z _m.

[Width, cross-sectional area and resistivity of power supply wiring and common wiring]
Hereinafter, the width, cross-sectional area, and resistivity of the power supply wiring and common wiring of the first and second display panels 1 are defined. Here, when the number of pixels of the display panel 1 is WXGA (768 × 1366), desirable widths and cross-sectional areas of the power supply wiring 90 and the common wiring 91 are defined. FIG. 12 is a graph showing current-voltage characteristics of the driving transistor 23 and the organic EL element 20 of each subpixel.

  In FIG. 12, the vertical axis represents the current value of the write current flowing between the source 23s and the drain 23d of one drive transistor 23 or the current value of the drive current flowing between the anode and the cathode of one organic EL element 20. The axis is the voltage between the source 23s and the drain 23d of one drive transistor 23 (at the same time, the voltage between the gate 23g and the drain 23d of one drive transistor 23). In the figure, solid line Ids max is a write current and drive current at the maximum luminance gradation (brightest display), and alternate long and short dash line Ids mid is an intermediate luminance between the highest luminance gradation and the lowest luminance gradation. The two-dot chain line Vpo is a threshold value, that is, a pinch-off voltage between the unsaturated region (linear region) and the saturated region of the driving transistor 23, and the three-dot chain line Vds is the driving transistor 23. The write current flowing between the source 23 s and the drain 23 d of the organic EL element 20, and the broken line Iel is the drive current flowing between the anode and the cathode of the organic EL element 20.

  Here, the voltage VP1 is a pinch-off voltage of the driving transistor 23 at the maximum luminance gradation, and the voltage VP2 is a source-drain voltage when a writing current of the maximum luminance gradation flows through the driving transistor 23. VELmax (voltage VP4−voltage VP3) is a voltage between the anode and the cathode when the organic EL element 20 emits light with the driving current of the maximum luminance gradation whose current value is equal to the writing current of the maximum luminance gradation. The voltage VP2 ′ is a source-drain voltage when the driving transistor 23 receives an intermediate luminance gradation write current, and the voltage (voltage VP4′−voltage VP3 ′) is an organic EL element 20 having an intermediate luminance gradation. This is the anode-cathode voltage when light is emitted with a drive current of an intermediate luminance gradation whose current value is equal to the write current.

  Since both the drive transistor 23 and the organic EL element 20 are driven in the saturation region, a value VX obtained by subtracting (the voltage Vcom during the light emission period of the common wiring 91) from (the voltage VH during the light emission period of the power supply wiring 90) is The following formula (2) is satisfied.

      VX = Vpo + Vth + Vm + VEL (2)

  Vth (equal to VP2−VP1 at the maximum luminance) is a threshold voltage of the drive transistor 23, VEL (equal to VELmax at the maximum luminance) is an anode-cathode voltage of the organic EL element 20, and Vm is The allowable voltage is displaced according to the gradation.

  As is apparent from the figure, the higher the luminance gradation of the voltage VX, the higher the voltage (Vpo + Vth) required between the source and drain of the transistor 23 and the voltage VEL required between the anode and cathode of the organic EL element 20. Becomes higher. Therefore, the allowable voltage Vm becomes lower as the luminance gradation becomes higher, and the minimum allowable voltage Vmmin becomes VP3−VP2.

  The organic EL element 20 generally deteriorates with time regardless of the low-molecular EL material and the high-molecular EL material, and increases in resistance. It has been confirmed that the anode-cathode voltage after 10,000 hours is about 1.4 times the initial voltage. That is, the voltage VEL increases with time even at the same luminance gradation. For this reason, the higher the allowable voltage Vm at the beginning of driving, the more stable the operation over a long period of time. Therefore, the voltage VX is set so that the voltage VEL is 8V or higher, more preferably 13V or higher.

  This allowable voltage Vm includes not only the increase in resistance of the organic EL element 20 but also the voltage drop due to the power supply wiring 90.

  When the voltage drop is large due to the wiring resistance of the power supply wiring 90, the power consumption of the display panel 1 is remarkably increased. Therefore, the voltage drop of the power supply wiring 90 is particularly preferably set to 1V or less.

The pixel width Wp, which is the length of one pixel in the row direction, the number of pixels in the row direction (1366), the extension from the first lead-out wiring to one wiring terminal outside the pixel region, As a result of considering the extended portion from the first routing wiring to the other wiring terminal, when the panel size of the display panel 1 is 32 inches and 40 inches, the total length of the first routing wiring is 706.7 mm and 895, respectively. .2mm. Here, when the line width WL of the power supply wiring 90 and the line width WL of the common wiring 91 are widened, the area of the organic EL layer 20b is structurally reduced, and further, a parasitic capacitance with other wiring is generated, resulting in further voltage drop. Therefore, it is desirable to suppress the width WL of the power supply wiring 90 and the line width WL of the common wiring 91 to one fifth or less of the pixel width Wp. Considering this, when the panel size of the display panel 1 is 32 inches and 40 inches, the width WL is within 34 μm and 44 μm, respectively. Further, the maximum film thickness Hmax of the power supply wiring 90 and the common wiring 91 is 1.5 times the minimum processing dimension 4 μm of the transistors 21 to 23, that is, 6 μm, in consideration of the aspect ratio. Thus the maximum cross-sectional area Smax of the feed interconnection 90 and common interconnection 91 is 32-inch 40-inch respectively 204Myuemu ^2, a 264μm ^2.

  For such a 32-inch display panel 1, in order to set the maximum voltage drop of the power supply wiring 90 and the common wiring 91 at 1 V or less when fully lit so that the maximum current flows, as shown in FIG. The wiring resistivity ρ / cross-sectional area S of each of the power supply wiring 90 and the common wiring 91 needs to be set to 4.7 Ω / cm or less. FIG. 14 shows the correlation between the cross-sectional area of each of the power supply wiring 90 and the common wiring 91 of the 32-inch display panel 1 and the current density. Note that the resistivity allowed at the time of the maximum cross-sectional area Smax of the power supply wiring 90 and the common wiring 91 is 9.6 μΩcm at 32 inches and 6.4 μΩcm at 40 inches.

  Then, for the 40-inch display panel 1, in order to set the maximum voltage drop of the power supply wiring 90 and the common wiring 91 to 1 V or less when all the lights are turned on so that the maximum current flows, as shown in FIG. The wiring resistivity ρ / cross-sectional area S of each of the wiring 90 and the common wiring 91 needs to be set to 2.4 Ω / cm or less. FIG. 16 shows the correlation between the cross-sectional area of each of the power supply wiring 90 and the common wiring 91 of the 40-inch display panel 1 and the current density.

  The failure life MTF that does not operate due to the failure of the power supply wiring 90 and the common wiring 91 satisfies the following formula (3).

MTF = A exp (Ea / K _b T) / ρJ ² (3)

Ea is the activation energy, K _b T = 8.617 × 10 ⁻⁵ eV, ρ is the resistivity of the power supply wiring 90 and the common wiring 91, and J is the current density.

The failure life MTF of the power supply wiring 90 and the common wiring 91 is limited by an increase in resistivity or electromigration. When the power supply wiring 90 and the common wiring 91 are set to be Al-based (Al alone or an alloy such as AlTi or AlNd) and the MTF is estimated for 10,000 hours at an operating temperature of 85 ° C., the current density J is 2.1 × 10 ⁴ A. / Cm ² or less. Similarly, when the power supply wiring 90 and the common wiring 91 are set to Cu, the power supply wiring 90 and the common wiring 91 need to be 2.8 × 10 ⁶ A / cm ² or less. It is assumed that materials other than Al in the Al alloy have a lower resistivity than Al.
In consideration of these points, in the 32-inch display panel 1, the cross-sectional areas of the Al-based power supply wiring 90 and the common wiring 91 are such that the power supply wiring 90 and the common wiring 91 do not fail in 10,000 hours in the fully lit state. S is required to be 57 μm ² or more from FIG. 14, and similarly, the cross sectional areas S of the Cu power supply wiring 90 and the common wiring 91 are required to be 0.43 μm ² or more from FIG.

In the 40-inch display panel 1, the cross-sectional areas S of the Al-based power supply wiring 90 and the common wiring 91 so that the power supply wiring 90 and the common wiring 91 do not fail in 10,000 hours in the fully lit state are shown in FIG. 92 μm ² or more is required, and similarly, the cross-sectional areas S of the Cu power supply wiring 90 and the common wiring 91 are required to be 0.69 μm ² or more from FIG.

If the Al-based power supply wiring 90 and the common wiring 91 have an Al-based resistivity of 4.00 μΩcm, the 32-inch display panel 1 has a wiring resistivity ρ / cross-sectional area S of 4.7 Ω / cm or less as described above. Therefore, the minimum cross-sectional area Smin is 85.1 μm ² . At this time, since the wiring width WL of the power supply wiring 90 and the common wiring 91 is within 34 μm as described above, the minimum film thickness Hmin of the power supply wiring 90 and the common wiring 91 is 2.50 μm.

Further, in the 40-inch display panel 1 of the Al-based power supply wiring 90 and the common wiring 91, the wiring resistivity ρ / cross-sectional area S is 2.4Ω / cm or less as described above, so the minimum cross-sectional area Smin is 167 μm ² . At this time, since the wiring width WL of the power supply wiring 90 and the common wiring 91 is within 44 μm as described above, the minimum film thickness Hmin of the power supply wiring 90 and the common wiring 91 is 3.80 μm.

In the Cu power supply wiring 90 and the common wiring 91, if the Cu resistivity is 2.10 μΩcm, the 32-inch display panel 1 has the wiring resistivity ρ / cross-sectional area S of 4.7 Ω / cm or less as described above. The minimum cross-sectional area Smin is 44.7 μm ² . At this time, since the wiring width WL of the power supply wiring 90 and the common wiring 91 is within 34 μm as described above, the minimum film thickness Hmin of the power supply wiring 90 and the common wiring 91 is 1.31 μm.

Further, in the 40-inch display panel 1 of the Cu power supply wiring 90 and the common wiring 91, the wiring resistivity ρ / cross-sectional area S is 2.4Ω / cm or less as described above, so the minimum cross-sectional area Smin is 87.5 μm ^2. . At this time, since the wiring width WL of the power supply wiring 90 and the common wiring 91 is within 44 μm as described above, the minimum film thickness Hmin of the power supply wiring 90 and the common wiring 91 is 1.99 μm.

  From the above, in order to operate the display panel 1 normally and with low power consumption, it is preferable to set the voltage drop in the power supply wiring 90 and the common wiring 91 to 1 V or less. When the wiring 90 and the common wiring 91 are an Al-based 32-inch panel, the film thickness H is 2.50 μm to 6 μm, the width WL is 14.1 μm to 34.0 μm, and the resistivity is 4.0 μΩcm to 9.6 μΩcm. In a 40-inch panel in which the wiring 90 and the common wiring 91 are Al-based, when the power supply wiring 90 and the common wiring 91 are Al-based, the film thickness H is 3.80 μm to 6 μm, the width WL is 27.8 μm to 44.0 μm, The resistivity is 4.0 μΩcm to 9.6 μΩcm.

In general, in the case of the Al-based power supply wiring 90 and the common wiring 91, the film thickness H is 2.50 μm to 6 μm, the width WL is 14.1 μm to 44 μm, and the resistivity is 4.0 μΩcm to 9.6 μΩcm.
Similarly, in a 32-inch panel in which the power supply wiring 90 and the common wiring 91 are Cu, the film thickness H is 1.31 μm to 6 μm, the width WL is 7.45 μm to 34 μm, and the resistivity is 2.1 μΩcm to 9.6 μΩcm. When the power supply wiring 90 and the common wiring 91 are 40-inch panels made of Cu, when the power supply wiring 90 and the common wiring 91 are Cu-based, the film thickness H is 1.99 μm to 6 μm, the width WL is 14.6 μm to 44.0 μm, The resistivity is 2.1 μΩcm to 9.6 μΩcm.

In general, in the case of the Cu power supply wiring 90 and the common wiring 91, the film thickness H is 1.31 μm to 6 μm, the width WL is 7.45 μm to 44 μm, and the resistivity is 2.1 μΩcm to 9.6 μΩcm.
Therefore, when an Al-based material or Cu is applied as the power supply wiring 90 and the common wiring 91, the power supply wiring 90 and the common wiring 91 of the display panel 1 have a film thickness H of 1.31 μm to 6 μm and a width WL of 7.45 μm. 44 μm and resistivity becomes 2.1 μΩcm to 9.6 μΩcm.

  As described above, the common wiring 91 protruding between the subpixel electrodes 20a adjacent in the horizontal direction is formed in a layer different from the electrodes of the transistors 21 to 23, and thus the common wiring 91 is made thick. Therefore, the resistance of the common wiring 91 can be reduced. Since the low-resistance common wiring 91 is electrically connected to the counter electrode 20c, the voltage of the counter electrode 20c can be made uniform in the plane even when the counter electrode 20c itself is thinned to have a higher resistance. . Therefore, even if the same potential is applied to all the subpixel electrodes 20a, the light emission intensity of any organic EL layer 20b becomes substantially equal, and the in-plane light emission intensity can be made uniform.

  Further, when the display panel 1 is used as a top emission type, the counter electrode 20c can be made thinner, so that light emitted from the organic EL layer 20b is not easily attenuated while being transmitted through the counter electrode 20c. Furthermore, since the common wiring 91 is provided between the subpixel electrodes 20a adjacent in the horizontal direction in plan view, a decrease in the pixel aperture ratio can be minimized.

  In addition, since the power supply wiring 90 embedded in the planarization film 33 and the protective insulating film 32 is formed in a layer different from the electrodes of the transistors 21 to 23 between the rows of the pixels 3 in the horizontal direction, A thick film can be formed, and the resistance of the power supply wiring 90 can be reduced. Since the low-resistance power supply wiring 90 is laminated on the thin-film supply line Z, the voltage drop of the supply line Z can be suppressed, and further, the signal delay of the supply line Z and the power supply wiring 90 can be suppressed. For example, if the display panel 1 is enlarged when the power supply wiring 90 is not provided, the in-plane emission intensity unevenness occurs due to the voltage drop of the supply line Z, or there is an organic EL element 20 that does not emit light. There is a fear. However, in this embodiment, since the low-resistance power supply wiring 90 is electrically connected to the supply line Z, unevenness of the in-plane light emission intensity can be suppressed, and the organic EL element 20 that does not emit light can be eliminated.

  Further, since the resistance of the power supply wiring 90 is reduced by increasing the thickness of the power supply wiring 90, the width of the power supply wiring 90 can be reduced. Therefore, it is possible to minimize the decrease in the pixel aperture ratio.

Since the common wiring 91 group is arranged above the signal lines Y _{1 to} Y _n arranged in the non-pixel region between the sub-pixel electrodes 20a and 20a, the area of the sub-pixel electrode 20a is set to the arrangement of the common wiring 91 group. Will not shrink.
In addition, since the thick film bank 71 is interposed between the signal line Y and the common wiring 91, the parasitic capacitance generated between the signal line Y and the common wiring 91 can be extremely reduced. Further, since the common wiring 91 and the bank 71 overlap in a plan view, a decrease in the pixel aperture ratio can be minimized.

[Second Embodiment]
A display panel 101 according to the second embodiment will be described with reference to FIGS. As shown in FIGS. 17 to 25, for the display panel 101 in the second embodiment, the same reference numerals are given to the same parts as any part of the display panel 1 in the first embodiment. Description of the same part is omitted.

  FIG. 17 is a schematic plan view of the pixel 3 of the display panel 101 in the second embodiment, and FIG. 18 is a plan view mainly showing electrodes of the subpixel P. As shown in FIGS. 17 and 18, the planar layout of the pixel 3, the sub-pixels Pr, Pg, and Pb, the signal lines Yr, Yg, Yb, the scanning line X, and the supply line Z is the same as the planar layout in the first embodiment. It is.

  19 is a cross-sectional view taken in the direction of the thickness of the insulating substrate 2 along the cutting line XIX-XIX shown in FIG. 17, and FIG. 20 is a cutting line XX-XX shown in FIG. FIG. 21 is a cross-sectional view taken in the direction of the thickness of the insulating substrate 2 along FIG. 21, and FIG. 21 is a view taken in the direction of the thickness of the insulating substrate 2 along the cutting line XXI-XXI shown in FIG. 22 is a cross-sectional view, and FIG. 22 is a cross-sectional view taken in the direction of the thickness of the insulating substrate 2 along the cutting line XXII-XXII shown in FIG. As shown in FIGS. 19 to 22, the transistor array substrate 50, the insulating film 52 patterned on the surface thereof, and the subpixel electrode 20 a are provided in the same manner as in the first embodiment.

  In the first embodiment, the power supply wiring 90 is embedded in the planarization film 33 and the protective insulating film 32. On the other hand, in the second embodiment, the power supply wiring 90A grown by the plating method is provided on the insulating film 52 so as to extend along the vertical direction as shown in FIG. The power supply wiring 90A is arranged between the vertical red subpixel Pr column and the green subpixel Pg column, between the vertical green subpixel Pg column and the blue subpixel Pb column, and It is arranged between the column of blue subpixels Pb and the column of red subpixels Pr in the vertical direction.

  Since the power supply wiring 90 </ b> A is provided on the insulating film 52, the bank 71 in the first embodiment is not provided in the second embodiment. That is, the power supply wiring 90 </ b> A is provided instead of the bank 71. In the first embodiment, the bank 71 is made of an insulating photosensitive resin. However, the power supply wiring 90A of the second embodiment preferably includes at least one of copper, aluminum, gold, and nickel. Therefore, the power supply wiring 90A must be insulated from the counter electrode 20c. Therefore, a hydrophobic insulating film 53A having water and oil repellency is formed on the surface of the power supply wiring 90A, and the hydrophobic insulating film 53A is interposed between the power supply wiring 90A and the counter electrode 20c.

  The hydrophobic insulating film 53A is made of a fluororesin electrodeposition paint and is formed by electrodeposition coating. The organic EL layer 20b of the organic EL element 20 is formed by a wet coating method (for example, an ink jet method) after the formation of the power supply wiring 90A and the hydrophobic insulating film 53A. Examples of the electrodeposition paint include Elecoat Nicelon, Elecoat Nicelon CTR, Elecoat AMF (manufactured by Shimizu Corporation), and the like. In this case, the organic compound-containing liquid is applied to the subpixel electrode 20a. However, since the hydrophobic insulating film 53A is formed on the surface of the power supply wiring 90A between the subpixel electrodes 20a adjacent in the horizontal direction, the subpixel electrode 20a. The organic compound-containing liquid applied to the liquid does not leak to the adjacent subpixel electrode 20a. Therefore, the organic EL layer 20b can be applied for each color by a wet coating method. Further, since the organic compound-containing liquid applied to the subpixel electrode 20a does not become thick at the periphery of the power supply wiring 90A due to the water and oil repellency of the hydrophobic insulating film 53A, the organic EL layer 20b is formed with a uniform film thickness. Can do.

17, 18, 20, as shown in FIG. 23, the power supply wiring 90A in plan view, 90A ... and the place where the supply lines Z ₁ to Z _m intersect, the planarization film 33 and protective insulating film 32 A contact hole 81 is formed, a conductive pad 82 is embedded in the contact hole 81, and a conductive film 51A is patterned on the surface of the conductive pad 82. The conductive film 51A is formed on the surface of the subpixel electrode 20a. The original conductive film is patterned together with the subpixel electrode 20a by etching. Further, a contact hole 83 is formed in the insulating film 52 at a portion where the power supply wiring 90 </ b> A and the supply line Z intersect in plan view, and a part of the power supply wiring 90 </ b> A is embedded in the contact hole 83. Thus, the power supply wiring 90 </ b> A is electrically connected to the supply line Z through the contact hole 81 and the contact hole 83. The supply lines Z _{1 to} Z _m are connected to a lead wiring 99 formed by patterning the same conductive layer as the power supply wiring 90A, and are electrically connected to the terminal portions 90d and 90e.

  Any power supply wiring 90A is electrically connected to all the supply lines Z. For this reason, the first display panel 1 driving method described with reference to FIG. 9 cannot drive the display panel 101 according to the second embodiment, but the second display panel 1 described with reference to FIG. In the driving method, the display panel 101 of the second embodiment can be driven.

In the first embodiment, a plurality of common wirings 91 are arranged on the counter electrode 20c. On the other hand, in the second embodiment, the common wiring 91A is patterned in a mesh shape as shown in FIG. Specifically, the common wiring 91A is arranged above the scanning lines X _{1 to} X _m and the signal line Y ₁ so as to fill the space between the subpixel electrodes 20a and 20a adjacent to each other in the vertical direction and the horizontal direction in plan view. It is patterned in a grid above and above the supply lines Z ₁ to Z _m of to Y _n. For this reason, as shown in FIG. 25, a part of the common wiring 91A overlaps the power supply wiring 90A, but since the hydrophobic insulating film 53A is formed on the surface of the power supply wiring 90A, the common wiring 91A becomes the power supply wiring 90A. Is insulated against. The common wiring 91A preferably includes at least one of copper, aluminum, gold, and nickel, and all of them are thick enough to be opaque to the light emitted from the organic EL layer 20b.

  Except for what has been described above, the display panel 101 in the second embodiment is configured in the same manner as the display panel 1 in the first embodiment. Of course, as with the width, cross-sectional area, and resistivity of the power supply wiring 90 and the common wiring 91 of the first embodiment, the film thickness H is 2.50 μm when the power supply wiring 90A and the common wiring 91A are an Al-based 32-inch panel. .About.6 .mu.m, width WL is 14.1 .mu.m to 34.0 .mu.m, and the resistivity is 4.0 .mu..OMEGA.cm to 9.6 .mu..OMEGA.cm. Is Al-based, the film thickness H is 3.80 μm to 6 μm, the width WL is 27.8 μm to 44.0 μm, and the resistivity is 4.0 μΩcm to 9.6 μΩcm. In general, in the case of the Al-based power supply wiring 90A and the common wiring 91A, the film thickness H is 2.50 μm to 6 μm, the width WL is 14.1 μm to 44 μm, and the resistivity is 4.0 μΩcm to 9.6 μΩcm. Similarly, in a 32-inch panel in which the power supply wiring 90A and the common wiring 91A are Cu, the film thickness H is 1.31 μm to 6 μm, the width WL is 7.45 μm to 34 μm, and the resistivity is 2.1 μΩcm to 9.6 μΩcm. In a 40-inch panel in which the power supply wiring 90A and the common wiring 91A are Cu, when the power supply wiring 90A and the common wiring 91A are Cu-based, the film thickness H is 1.99 μm to 6 μm, the width WL is 14.6 μm to 44.0 μm, The resistivity is 2.1 μΩcm to 9.6 μΩcm. In general, in the case of the Cu power supply wiring 90A and the common wiring 91A, the film thickness H is 1.31 μm to 6 μm, the width WL is 7.45 μm to 44 μm, and the resistivity is 2.1 μΩcm to 9.6 μΩcm. Therefore, when Al-based material or Cu is applied as the power supply wiring 90A and the common wiring 91A, the power supply wiring 90A and the common wiring 91A of the display panel 101 have a film thickness H of 1.31 μm to 6 μm and a width WL of 7.45 μm. 44 μm and resistivity becomes 2.1 μΩcm to 9.6 μΩcm.

  Also in this embodiment, since the common wiring 91A is formed thick by the plating method, the voltage of the counter electrode 20c is made uniform in the plane even if the counter electrode 20c itself is thinned to have a higher resistance. Can do. In addition, since the power supply wiring 90A is formed thick by plating, voltage drop of the supply line Z can be suppressed, and unevenness of emission intensity in the surface can be suppressed.

  In addition, since the common wiring 91A partially overlaps the power supply wiring 90A in plan view, it is possible to minimize the decrease in the pixel aperture ratio.

Then, the common wiring 91A group sub-pixel electrode 20a, the scanning line X ₁ arranged in non-pixel areas between 20a to X _m above, the signal lines Y ₁ to Y _n of the upper and supply lines Z ₁ to Z _m Since it is arranged in a lattice shape above, the area of the subpixel electrode 20a is not reduced by the arrangement of the common wiring 91A group.

[Third Embodiment]
A display panel 201 according to the third embodiment will be described with reference to FIGS. In addition, as shown in FIGS. 26-28, about the display panel 201 in 3rd Embodiment, the same code | symbol is attached | subjected with respect to the part corresponding to any part of the display panel 201 in 3rd Embodiment. Description of the corresponding parts is omitted.

  FIG. 26 is a schematic plan view of the pixel 3 of the display panel 201 in the third embodiment. As shown in FIG. 26, similarly to the display panel 1 in the first embodiment, the pixels 3 are arranged in a matrix in the display panel 201 of the third embodiment. However, in the first embodiment, the pixel 3 is configured by the subpixels Pr, Pg, and Pb arranged along the horizontal direction. However, in the third embodiment, the subpixels Pr, Pg arranged along the vertical direction. , Pb constitute a pixel 3.

  Accordingly, when paying attention to the order of arrangement in the horizontal direction, a plurality of red subpixels Pr are arranged in one row along the horizontal direction, a plurality of green subpixels Pg are arranged in one row along the horizontal direction, and a plurality of blue subpixels Pb are arranged. Are arranged in a line along the horizontal direction. On the other hand, when paying attention to the arrangement order in the vertical direction, the red subpixel Pr, the green subpixel Pg, and the blue subpixel Pb are repeatedly arranged in this order.

  In the first embodiment, since the red subpixel Pr, the green subpixel Pg, and the blue subpixel Pb are arranged in a line along the vertical direction for each color, the signal line Yr and the signal line extending in the vertical direction are arranged. Yg and the signal line Yb are provided in the row of the red subpixel Pr, the row of the green subpixel Pg, and the row of the blue subpixel Pb, respectively. On the other hand, in the third embodiment, the red sub-pixel Pr, the green sub-pixel Pg, and the blue sub-pixel Pb are arranged in a line along the vertical direction so as to repeat in this order. Three signal lines Yr, Yg, Yb are provided for one column of Pr, Pg, Pb. Here, the signal line Yr supplies a signal to all red subpixels Pr in the column of the pixels 3 in the vertical direction, and the signal line Yg is all green subs in the column of the pixels 3 in the vertical direction. A signal is supplied to the pixel Pg, and the signal line Yb supplies a signal to all the blue subpixels Pb in the column of the pixels 3 in the vertical direction. In consideration of the unit of the pixel 3, in the case of the first embodiment and the case of the second embodiment, three signal lines Yr, Yg, Yb are provided for each column of the pixels 3 in the vertical direction. Yes.

  In the first embodiment, one scanning line X and one supply line Z are provided for each row of pixels 3 in the horizontal direction. On the other hand, in the second embodiment, one scanning line XE and two supply lines ZC and ZD are provided for each row of pixels 3 in the horizontal direction. Specifically, the supply line ZC is arranged between the column of the red subpixel Pr and the column of the blue subpixel Pb in the horizontal direction, and the row of the green subpixel Pg and the row of the red subpixel Pr in the horizontal direction are arranged. A supply line ZD is arranged therebetween, and a scanning line X is arranged between the row of blue subpixels Pb and the row of green subpixels Pg in the horizontal direction.

  The two supply lines ZC and ZD in the row of the pixels 3 in the horizontal direction form a pair, and the two supply lines ZC and ZD are electrically connected to each other in the peripheral portion of the display panel 201.

  In the third embodiment, one contact hole 92C is provided for each pixel 3 of pixels. The contact hole 92C is common to the subpixels Pr, Pg, and Pb included in the pixel 3 of one pixel. In any of the subpixels Pr, Pg, and Pb, the gates 21g and 22g of the transistors 21 and 22 are connected to the contact hole 92C. Through the scanning line XE. Note that the contact hole 92C is formed at a location overlapping the scanning line XE of the gate insulating film 31, like the contact hole 92 in the first embodiment.

  In the red subpixel Pr, the drain 23d of the drive transistor 23 is provided integrally with the supply line ZC, and in the green subpixel Pg, the drain 23d of the drive transistor 23 is provided integrally with the supply line ZD. The drain 23d of the driving transistor 23 of the blue subpixel Pb is electrically connected to the supply line ZD through the connection line 96C. Here, the connection line 96 </ b> C is formed by patterning the gate layer, is covered with the gate insulating film 31, and is provided so as to vertically cut the pixels 3 in the vertical direction in plan view. A contact hole 97C is formed at a portion where the supply line ZD and the connection line 96C of the gate insulating film 31 overlap each other, and the connection line 96C is electrically connected to the supply line ZD through the contact hole 97C. In the blue subpixel Pb, the contact hole 98C is formed at a position where the connection line 96C of the gate insulating film 31 and the drain 23d of the drive transistor 23 overlap, and the connection line 96C and the drive transistor 23 are connected via the contact hole 98C. The drain 23d is conductive.

  The layer structure of the transistors 21 to 23 is the same as that in the first embodiment, but the planar layout of the transistors 21 to 23 is different from that in the first embodiment. That is, in the red subpixel Pr, the driving transistor 23 is arranged along the supply line ZC, the switch transistor 21 is arranged along the supply line ZD, and the holding transistor 22 is arranged near the supply line ZC. It arrange | positions at the corner | angular part of Pr. In the green subpixel Pg, the driving transistor 23 is arranged along the supply line ZD, the switch transistor 21 is arranged along the scanning line XE, and the holding transistor 22 is arranged in the green subpixel Pg near the supply line ZD. It is arranged at the corner. In the blue subpixel Pb, the drive transistor 23 is disposed along the scanning line XE, the switch transistor 21 is disposed along the supply line ZC of the adjacent pixel 3, and the holding transistor 22 is disposed near the scanning line XE. It is arranged at the corner of the blue subpixel Pb. In any subpixel Pr, Pg, Pb, the capacitor 24 is arranged along the adjacent signal line Yb.

  27 is a cross-sectional view taken in the direction of the thickness of the insulating substrate 2 along the cutting line XXVII-XXVII shown in FIG. 26, and FIG. 28 is a cutting line XXVIII-XXVIII shown in FIG. It is arrow sectional drawing cut | disconnected in the thickness direction of the insulation board | substrate 2 along line. As shown in FIG. 27 and FIG. 28, the grooves 34C, 34D, and 34E that are long in the horizontal direction are provided at portions of the protective insulating film 32 and the planarizing film 33 that overlap the supply lines ZC and ZD and the scanning line XE, respectively. Is recessed. In the grooves 34C, 34D, and 34E, a power supply wiring 90C, a power supply wiring 90D, and a selection wiring 89E are embedded, respectively. Each is stacked on the scanning line XE. As described above, the power supply wiring 90C, the power supply wiring 90D, and the selection wiring 89E are electrically connected to the supply line ZC, the supply line ZD, and the scanning line XE, respectively. The power supply wiring 90C, the power supply wiring 90D, and the selection wiring 89E are formed by plating, and are thicker than the supply line ZC, the supply line ZD, and the scanning line XE. The thicknesses of the power supply wiring 90 </ b> C, the power supply wiring 90 </ b> D, and the selection wiring 89 </ b> E are thinner than the total thickness of the protective insulating film 32 and the planarization film 33. The grooves 34C and 34D are first grooves, and the groove 34E is a second groove.

  Hydrophobic insulating films 53C, 53D, and 53E having water repellency and oil repellency are formed on the surfaces of the power supply wiring 90C, the power supply wiring 90D, and the selection wiring 89E, respectively, and the hydrophobic insulating films 53C, 53D, and 53E are planarized films. It protrudes from the surface of 33. As a result, the hydrophobic insulating films 53C, 53D, and 53E are exposed on the surface of the planarizing film 33. The hydrophobic insulating films 53C, 53D, and 53E are made of a fluororesin electrodeposition paint and are formed by electrodeposition coating. Using the water / oil repellency of the hydrophobic insulating films 53C, 53D, and 53E, the organic EL layer 20b of the organic EL element 20 is applied for each color by a wet coating method (for example, an inkjet method). A plurality of subpixel electrodes 20a arranged in a row in the horizontal direction between the supply line ZC and the supply line ZD are covered with a common red light emitting organic EL layer 20b that is elongated in a strip shape along the horizontal direction. A plurality of subpixel electrodes 20a arranged in a line along the horizontal direction between the supply line ZD and the scanning line XE are formed into a common green light emitting organic EL layer 20b that is elongated in a strip shape along the horizontal direction. A plurality of sub-pixel electrodes 20a that are covered with each other and arranged in a line along the horizontal direction between the scanning line XE and the supply line ZC are formed in a strip-like shape along the horizontal direction. It is covered with 20b.

  The common wiring 91C is formed along the respective hydrophobic insulating films 53C, 53D, and 53E on the counter electrode 20c, and the common wiring 91C overlaps the hydrophobic insulating films 53C, 53D, and 53E in plan view. For this reason, the common wiring 91C is electrically connected to the counter electrode 20c. The common wiring 91C is also formed by plating, and is thicker than the supply line ZC, the supply line ZD, and the scanning line XE. The common wiring 91 group preferably includes at least one of copper, aluminum, gold, and nickel, and all of them are thick enough to be opaque to the light emitted from the organic EL layer 20b.

  Note that the driving method of the display panel 201 of the third embodiment is the same as the driving method of the display panel 1 of the first embodiment. Of course, in a panel of 32 inches in which the power supply wiring 90C and the power supply wiring 90D are Al-based, the film thickness H is 2.50 μm to 6 μm, the width WL is 14.1 μm to 34.0 μm, and the resistivity is 4.0 μΩcm to 9.6 μΩcm. When the power supply wiring 90C and the power supply wiring 90D are Al-based 40-inch panels, when the power supply wiring 90C and the power supply wiring 90D are Al-based, the film thickness H is 3.80 μm to 6 μm and the width WL is 27.8 μm to 44. And a resistivity of 4.0 μΩcm to 9.6 μΩcm. In general, in the case of the Al-based power supply wiring 90C and power supply wiring 90D, the film thickness H is 2.50 μm to 6 μm, the width WL is 14.1 μm to 44 μm, and the resistivity is 4.0 μΩcm to 9.6 μΩcm. Similarly, in a 32-inch panel in which the power supply wiring 90C and the power supply wiring 90D are Cu, the film thickness H is 1.31 μm to 6 μm, the width WL is 7.45 μm to 34 μm, and the resistivity is 2.1 μΩcm to 9.6 μΩcm. In a 40-inch panel in which the power supply wiring 90C and the power supply wiring 90D are Cu, when the power supply wiring 90C and the power supply wiring 90D are Cu-based, the film thickness H is 1.99 μm to 6 μm, the width WL is 14.6 μm to 44.0 μm, The resistivity is 2.1 μΩcm to 9.6 μΩcm. In general, in the case of the Cu power supply wiring 90C and the power supply wiring 90D, the film thickness H is 1.31 μm to 6 μm, the width WL is 7.45 μm to 44 μm, and the resistivity is 2.1 μΩcm to 9.6 μΩcm. Therefore, when an Al-based material or Cu is applied as the power supply wiring 90C and the power supply wiring 90D, the power supply wiring 90C and the power supply wiring 90D of the display panel 201 have a film thickness H of 1.31 μm to 6 μm and a width WL of 7.45 μm. 44 μm and resistivity becomes 2.1 μΩcm to 9.6 μΩcm.

  Also in this embodiment, since the common wiring 91C is formed thick by a plating method, the voltage of the counter electrode 20c is made uniform in the plane even if the counter electrode 20c itself is thinned to have a higher resistance. Can do. In addition, since the power supply wirings 90C and 90D are thickly formed by a plating method, voltage drop of the supply lines ZC and ZD can be suppressed, and unevenness of the in-plane light emission intensity can be suppressed.

  Further, since the selection wiring 89E stacked on the scanning line XE is formed thick by plating, signal delay of the scanning line XE and the selection wiring 89E can be further suppressed. That is, when attention is paid to the row of the sub-pixels P in the horizontal direction, the shift pulse becomes high level at the same time without delaying any sub-pixel P.

  Further, since the hydrophobic insulating films 53C, 53D, and 53E have electrical insulation properties, it is possible to avoid a short circuit between the power supply wirings 90C and 90D, the selection wiring 89A, and the counter electrode 20c.

  Since the common lines 91C, 91C,... Are formed above the selection line 89E and the power supply lines 90C, 90D, the area of the subpixel electrode 20a is not reduced by the arrangement of the common lines 91C group.

[Modification 1]
The present invention is not limited to the above-described embodiments, and various improvements and design changes may be made without departing from the spirit of the present invention.

  In each of the above embodiments, the transistors 21 to 23 are described as N-channel field effect transistors. The transistors 21 to 23 may be P-channel field effect transistors. In that case, in the circuit configuration of FIG. 2, the relationship between the sources 21s, 22s, and 23s of the transistors 21 to 23 and the drains 21d, 22d, and 23d of the transistors 21 to 23 is reversed. For example, when the drive transistor 23 is a P-channel field effect transistor, the drain 23d of the drive transistor 23 is conducted to the subpixel electrode 20a of the organic EL element 20, and the source 23s is conducted to the supply line Z.

[Modification 2]
In each of the above embodiments, three transistors 21 to 23 are provided for one dot sub-pixel P. However, one or more transistors are provided for one dot sub-pixel P, and active using these transistors. The present invention can be applied to any display panel that can be driven.

[Modification 3]
In each of the above embodiments, the signal line Y is patterned from the gate layer, but the signal line Y may be patterned from the drain layer. In this case, the scanning line X and the supply line Z are patterned from the gate layer, and the signal line Y is higher than the scanning line X and the supply line Z.

[Modification 4]
In each of the above embodiments, the counter electrode 20c is the cathode of the organic EL element 20, and the subpixel electrode 20a is the anode of the organic EL element 20. However, the counter electrode 20c is the anode of the organic EL element 20, and the subpixel electrode 20a may be used as the cathode of the organic EL element 20.

DESCRIPTION OF SYMBOLS 1 Display panel 2 Insulating substrate 20a Subpixel electrode 20b Organic EL layer 20c Counter electrode 21 Switch transistor 22 Holding transistor 23 Drive transistor 21d, 22d, 23d Drain 21s, 22s, 23s Source 21g, 22g, 23g Gate 31 Gate insulating film 34C, 34D, 34E Groove 50 Transistor array substrate 53A, 53C, 53D, 53E Hydrophobic insulating film 71 Bank 89E Selection wiring 90A, 90C, 90D Power supply wiring 91, 91A, 91C Common wiring Pr, Pg, Pb Subpixel

Claims (4)

A transistor array substrate in which a plurality of subpixels are two-dimensionally arranged on one surface side, and a transistor is provided for each subpixel;
The one surface side of the transistor array substrate is provided in parallel with each other along the row direction, and a power supply voltage for operating the transistors is supplied, and the current paths of the transistors in each of the plurality of subpixels are supplied. A plurality of first power supply wirings electrically connected to one end;
A first insulating film provided on the one surface side of the transistor array substrate and covering each of the transistors and the plurality of first power supply wirings of the plurality of sub-pixels;
A plurality of second power supply lines provided in parallel to each other along the column direction on the first insulating film and electrically connected to the first power supply lines ;
A second insulating film covering a surface of the plurality of second power supply wirings;
Between each of the second power supply lines , formed on the upper surface of the first insulating film, arranged along each of the second power supply lines , provided for each subpixel, and at the other end of the current path of the transistor connected, and a plurality of sub-pixel electrodes,
A light emitting layer formed on each of the subpixel electrodes;
A counter electrode that covers the light emitting layer on the plurality of subpixel electrodes and covers the plurality of second power supply wirings via the second insulating film ;
A common line provided on the upper surface of the one surface side of the counter electrode on the second power supply line and electrically connected to the counter electrode;
With
The plurality of second power supply wirings are formed such that a height from an upper surface of the first insulating film is higher than a height of each subpixel electrode from an upper surface of the first insulating film. Yes,
The common wiring is formed thicker than the thickness of the counter electrode,
The plurality of first power supply wirings and the plurality of second power supply wirings correspond to each of the plurality of subpixels in a plan view in an area where the plurality of subpixels of the transistor array substrate are two-dimensionally arranged. A display panel, wherein the display panels intersect at a plurality of locations and are electrically connected to each other through contact holes provided in the first insulating film . The display panel according to claim 1 , wherein the second insulating film has water repellency and oil repellency. On the one surface side of the transistor array substrate, provided on the lower surface side of the first insulating film, along the column direction, a plurality of signal lines arranged parallel to each other,
2. The display panel according to claim 1 , wherein the plurality of second power supply wirings overlap each of the plurality of signal lines in a plan view . The common wiring display panel as claimed in any one of claims 1 to 3, characterized in that the opaque to the emitted light of the light emitting layer.

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