JP5070935B2 - Method for manufacturing silicon carbide semiconductor device - Google Patents

Description

  The present invention relates to a method of manufacturing a SiC semiconductor device, which includes a step of forming an oxide film by thermal oxidation on the surface of an impurity layer doped with impurities in silicon carbide (hereinafter referred to as SiC).

In SiC power devices, especially MOSFETs, the sacrificial oxidation and sacrificial oxide removal process for removing surface roughness generated by the ion implantation process and activation heat treatment before the gate oxide film formation, and the gate oxide film formation process are both used. Thermal oxidation at about 1000 ° C. is performed. When performing the sacrificial oxidation and the thermal oxidation in the sacrificial oxide film removing process and the gate oxide film process, there is a large difference in the rate of thermal oxidation between the region where impurities are implanted and the region where impurities are not implanted. For example, in a storage-type MOSFET, thermal oxidation of an n ⁺ -type source region into which impurities (phosphorus (P) or nitrogen (N)) are implanted and an n ^- type channel layer or p-type base layer constituting the channel region is performed. There is a big difference in speed. That is, accelerated oxidation is performed in which the thermal oxidation rate is higher in the implanted region than in the region where the impurity is not implanted, and therefore the implanted region is more oxidized than the region where the impurity concentration is not implanted. The thickness becomes thicker.

For this reason, the n ⁺ type source region is recessed as compared with the n ⁻ type channel layer, and the n ⁺ type source region becomes thin. The current path of the storage type MOSFET is as shown by the arrow in FIG. 6. However, since the n ⁺ type source region is longitudinally cut, the thinning of the n ⁺ type source region significantly reduces the device current characteristics. It becomes a factor to make.

To solve this problem, it is important how to suppress the accelerated oxidation of the n ⁺ -type source region. Accelerated oxidation amount is dependent on the impurity concentration and activation temperature of the n ⁺ -type source region, the impurity concentration of the n ⁺ -type source region, the contact resistance between the sheet resistance and the ohmic electrode of the n ⁺ -type source region It is determined. These resistance values are desirably 1/50 or less of the resistance value of the entire device. For this purpose, for example, the contact resistance needs to be 1 × 10 ⁻⁴ Ω · cm ² or less. FIG. 7 shows the relationship between the contact resistance and the impurity concentration of the n ⁺ -type source region. As shown in this figure, the impurity concentration of the n ⁺ -type source region is, for example, when the ohmic electrode is Ni. 3 × 10 ²⁰ cm ⁻³ or more is necessary. However, the relationship of the sort resistance ratio and the n ⁺ -type source region of the thermal oxide film on the n ⁺ -type source region to a thermal oxide film thickness formed on the ^n-type channel layer is expressed as shown in FIG. 8, n ^When the impurity concentration of the ⁺ type source region is set to the above value, since the n ⁺ type source region is thinned, the ratio of the thermal oxide film thickness becomes 7 times or more as shown in FIG. 8 (see the first axis). ), The sheet resistance of the n ⁺ -type source region increases as the impurity concentration increases (see the second axis).

To solve this problem, in Patent Document 1, the impurity of the n ⁺ -type source region has been proposed to form by epitaxial growth ^n-type channel layer after ion implantation and activation.

Further, in Patent Document 2, on the n ⁺ -type source region and ^n-type channel layer, has been proposed to further epitaxially growing the ^n-type channel layer.
JP 2002-270837 A JP 2002-270838 A

However, the technique disclosed in Patent Document 1 has a problem that the current path is structurally long and the on-resistance of the device is increased. In addition, since it is necessary to perform sacrificial oxidation substantially for high quality epitaxial growth before the formation of the n ^- type channel layer, it is inevitable to reduce the thickness of the n ⁺ type source region at that time.

On the other hand, in the method disclosed in Patent Document 2, the number of n ^- type channel layer forming steps is increased, and, as in Patent Document 1, high-quality epitaxial growth is performed before the formation of the n ^- type channel layer. Therefore, it is necessary to perform sacrificial oxidation substantially, and at that time, thinning of the n ⁺ -type source region due to accelerated oxidation is inevitable.

  Although the case where the gate oxide film is thermally oxidized has been described here, the same problem as in the case where the gate oxide film is formed by thermal oxidation also occurs with respect to sacrificial oxidation before the gate oxide film is formed.

  The present invention has been made in view of the above points, and it is an object of the present invention to prevent the source region from being thinned while preventing an increase in on-resistance and an increase in manufacturing processes.

  To achieve the above object, according to the present invention, in a method for manufacturing a silicon carbide semiconductor device having a storage MOS structure, a region (4a) located in a lower layer of source region (4) is formed with a first impurity concentration. Forming a region (4b) located above the region (4a) located in the lower layer of the source region (4) at a second impurity concentration lower than the first impurity concentration, 4), a region (4b) located in the upper layer and a channel layer (5) are thermally oxidized to form a gate oxide film (7).

  As described above, the region (4b) located in the upper layer of the source region (4) serving as the base, that is, the region to be oxidized is lower in concentration than the region (4a) located in the lower layer, ie, the region left unoxidized Therefore, it is possible to suppress the accelerated oxidation when the source region (4) is oxidized. Thereby, it becomes possible to suppress an increase in sheet resistance due to the thinning of the source region (4). Then, when forming the source region (4), it can be performed only by adjusting the concentration of impurity ion implantation, and there is no structural difference from the conventional structure. Such effects can be obtained.

  For example, after the drift layer (2) is formed on the substrate (1) and the base region (3) is formed in the drift layer (2), the surfaces of the drift layer (2) and the base region (3) are formed. Forming a channel layer (5) on the surface, and ion-implanting a first conductivity type impurity from above the channel layer (5), thereby forming a region (4a) located in the lower layer of the source region (4) At the same time, the step of forming the upper region (4b) of the source region (4) may be performed, and then the step of forming the gate oxide film (7) by thermal oxidation may be performed.

  Although a method for manufacturing a silicon carbide semiconductor device having a storage MOS structure has been described here, the same can be said for a method for manufacturing a silicon carbide semiconductor device having an inverted MOS structure.

  Further, in the step of forming the upper region (4b) of the source region (4), it is preferable that the thickness of the region (4b) is ½ or more of the thickness of the gate oxide film (7).

  When SiC is oxidized, the thickness of the oxide film is twice that of the original SiC layer. Therefore, the thickness of the upper region (4b) of the source region (4) is set to the gate oxide film (7). ) Or more of the thickness can be prevented from being oxidized to the region (4a) located in the lower layer due to thermal oxidation of the gate oxide film (7) in a later step. Thereby, the speed-up oxidation in the area | region (4a) located in a lower layer can be prevented.

Thus, the impurity concentration of the region (4b) located in the upper layer of the source region (4) that is set to a low impurity concentration can be 1 × 10 ²⁰ cm ⁻³ or less. Further, the impurity concentration of the region (4a) located in the lower layer of the source region (4), which is set to a high concentration, can be 3 × 10 ²⁰ cm ⁻³ or more.

  In the above description, the case where the gate oxide film (7) is thermally oxidized has been described. However, the sacrificial oxidation before forming the gate oxide film (7) is the same as that of the gate oxide film (7). In other words, by providing the features of the present invention, it is possible to obtain the same effects as described above.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments shown in the drawings will be described below. FIG. 1 is a cross-sectional view of a normally-off type n-channel type planar MOSFET (vertical power MOSFET) manufactured by the method of manufacturing an SiC semiconductor device shown in this embodiment. This device is suitable when applied to a rectifier for an inverter or an alternator for a vehicle. The structure of the vertical power MOSFET will be described with reference to FIG.

The n ⁺ type substrate 1 made of silicon carbide has an upper surface as a main surface 1a and a lower surface opposite to the main surface as a back surface 1b. On the main surface 1 a of the n ⁺ type substrate 1, an n ⁻ type epitaxial layer (hereinafter referred to as an n ⁻ type epi layer) 2 as a drift layer made of silicon carbide having an impurity concentration lower than that of the substrate 1 is laminated. ing.

A p-type base region 3 is formed in the surface layer portion of the n ⁻ -type epi layer 2. The p-type base region 3 is formed using B, Al, or Ge as a dopant, and has an impurity concentration of about 1 × 10 ¹⁷ cm ⁻³ or more. Further, in the central portion of the p-type base region 3 (the left and right end positions in FIG. 1), the P-type impurity concentration is partially increased and functions as a contact region. This portion may be formed deeper than other regions, and in this case, it functions as a deep base region.

Further, an n ⁺ type source region 4 shallower than the p type base region 3 is formed in the surface layer portion of the p type base region 3. The n ⁺ type source region 4 has an impurity concentration of about 1 × 10 ²¹ cm ⁻³ , for example. An n ⁻ type channel layer 5 is extended on the surface portion of the p type base region 3 so as to connect the n ⁺ type source region 4 and the n ⁻ type epi layer 2. This n ⁻ -type channel layer 5 is formed by epitaxial growth, and functions as a channel formation layer during device operation. For example, the low impurity concentration is about 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ .

A gate oxide film 7 is formed on the upper surface of the n ⁻ -type channel layer 5 and the upper surface of the n ⁺ -type source region 4 by thermal oxidation, and a gate electrode 8 is formed on the gate oxide film 7. The gate electrode 8 is covered with an insulating film 9 made of LTO (Low Temperature Oxide) or the like, and a source electrically connected to the n ⁺ -type source region 4 and the p-type base region 3 on the insulating film 9. An electrode 10 is formed. A drain electrode 11 is formed on the back surface 1b of the n ⁺ type substrate 1 to constitute a vertical power MOSFET.

The vertical power MOSFET configured as described above operates in a normally-off accumulation mode, and operates as follows. First, if no voltage is applied to the gate electrode, n ^- carrier in type channel layer 5, p ^- type base region 3 and the n ^- difference in electrostatic potential between the type channel layer 5, and the n ^- -type channel The entire region is depleted by the potential generated by the work function difference between the layer 5 and the gate electrode 8.

In this state, by applying a voltage to the gate electrode 8, the potential difference caused by the sum of the work function difference between the n ⁻ type channel layer 5 and the gate electrode 8 and the externally applied voltage can be changed. Thus, the channel state can be controlled.

In the off state, the depletion region is formed in the n ⁻ type channel layer 5 by the electric field generated by the p ⁻ type base region 3 and the gate electrode 8. When a positive bias is supplied, a channel region extending from the n ⁺ -type source region 4 toward the n ⁻ -type epi layer 2 is formed at the interface between the gate oxide film 7 and the n ⁻ -type channel layer 5 and switched to the on state. Is done. As a result, after passing through the n ⁺ -type source region 4 → n ⁻ -type channel layer 5 → n ⁻ -type epi layer 2 in order, the n ⁻ -type epi layer 2 (drift region) and the n ⁺ -type substrate 1 (n ⁺ drain) Electrons flow so as to be perpendicular to.

Thus, by applying a positive voltage to the gate electrode 8, an accumulation channel can be induced in the n ⁻ -type channel layer 5, and carriers can flow between the source electrode 10 and the drain electrode 11. .

  Next, the manufacturing process of the vertical power MOSFET shown in FIG. 1 will be described with reference to FIGS.

[Step shown in FIG. 2 (a)]
First, a semiconductor substrate made of n-type 4H, 6H, or 3C—SiC, that is, an n ⁺ -type substrate 1 is prepared. For example, an n ⁺ type substrate 1 having a thickness of about 400 μm is prepared. Then, an n ⁻ type epi layer 2 having a thickness of 5 μm is epitaxially grown on the main surface 1 a of the n ⁺ type substrate 1. In this case, the n ⁻ type epi layer 2 is obtained with the same crystal as the underlying substrate 1 and becomes an n type 4H or 6H or 3C—SiC layer.

[Steps shown in FIGS. 2B and 2C]
After the LTO film 20 is arranged on the n ⁻ type epi layer 2, the LTO film 20 is patterned to expose the formation position of the p ⁻ type base region 3. Using this as a mask, ions of B, Al, or Ge that are p-type impurities are implanted. The ion implantation conditions at this time are, for example, a temperature of 700 ° C. and a dose of 1 × 10 ¹⁶ cm ⁻² . Thereafter, activation heat treatment is performed to form p ⁻ type base region 3. Thereafter, the LTO film 20 is removed.

[Step shown in FIG. 3 (a)]
An n ⁻ type channel layer 5 is epitaxially grown on the n ⁻ type epi layer 2 including the p ⁻ type base region 3 by chemical vapor deposition (CVD).

At this time, in order to make the vertical power MOSFET normally-off type, the thickness (film thickness) of the n ⁻ type channel layer 5 is changed from the p type base region 3 to the n ⁻ type when no voltage is applied to the gate electrode 8. The amount of elongation of the depletion layer extending to the channel layer 5 and the amount of elongation of the depletion layer extending from the gate oxide film 7 to the n ⁻ -type channel layer 5 are made smaller.

Specifically, the extension amount of the depletion layer extending from the p-type base region 3 to the n ⁻ -type channel layer 5 is determined by the built-in voltage of the PN junction between the n ⁻ -type channel layer 5 and the p-type base region 3, and The extension amount of the depletion layer extending from the oxide film 7 to the n ⁻ type channel layer 5 is determined by the charge of the gate oxide film 7 and the work function difference between the gate electrode 8 (metal) and the n ⁻ type channel layer 5 (semiconductor). Therefore, the film thickness of the n ⁻ type channel layer 5 is determined based on these.

  Such a normally-off type vertical power MOSFET can prevent current from flowing even when a voltage cannot be applied to the gate electrode due to a failure or the like. Safety can be ensured.

[Step shown in FIG. 3B]
After the LTO film 21 is disposed on the n ⁻ -type channel layer 5, the LTO film 21 is patterned to expose the formation position of the n ⁺ -type source region 4. Then, an n-type impurity such as N (nitrogen) is ion-implanted using the LTO film 21 as a mask, and an n-type impurity is implanted into a region where the n ⁺ -type source region 4 is formed. At this time, of the n ⁺ type source region 4, the upper layer side region 4 a that remains as the n ⁺ type source region 4 without being oxidized at the time of thermal oxidation for forming the gate oxide film 7 performed in a later step, The concentration of the n-type impurity is made different between the lower region 4b for oxidation.

Specifically, the impurity concentration of the region 4a to be left as the n ⁺ -type source region 4 without being oxidized is 3 × 10 ²⁰ cm ⁻³ or more, preferably about 1 × 10 ²¹ cm ⁻³ . The impurity concentration is set to be 1 × 10 ²⁰ cm ⁻³ or less, preferably 1 × 10 ¹⁹ cm ⁻³ or less, which is one digit or more smaller than that. The thickness of the region 4b to be oxidized is about ½ of the gate oxide film 7 formed in a later step in consideration of the fact that the thickness doubles when SiC is oxidized. In order to prevent the accelerated oxidation from being performed by oxidizing up to 4a, it is preferable to make it 1/2 or more.

Thereafter, an activation heat treatment is performed at, for example, 1400 ° C. or higher (preferably 1500 ° C. or higher, more preferably 1600 ° C. or higher), whereby the n ⁺ -type source region 4 is formed.

[Step shown in FIG. 3 (c)]
Subsequently, after removing the LTO film 21, the LTO film 22 is disposed in a predetermined region on the n ⁻ type channel layer 5 by using a photoresist method, and the LTO film 22 is patterned, whereby the p ⁻ type base region is obtained. 3, the n ⁻ -type channel layer 5 formed at a position to be a contact region with the source electrode 10 is exposed.

[Step shown in FIG. 4 (a)]
By ion-implanting B ⁺ into the n ⁻ type channel layer 5 on the p ⁻ type base region 3 using the LTO film 22 as a mask, the base region is partially located so as not to overlap the n ⁺ type source region 4. A contact region having a high concentration of the p-type impurity 3 is formed.

[Step shown in FIG. 4B]
After removing the LTO film 22, the p ⁻ type base region 3 and the n ⁺ type source region 4 and the n ⁻ type are obtained by wet oxidation (including a pyrogenic method using H ₂ + O ₂ ) at an atmospheric temperature of 1080 ° C., for example. A gate oxide film 7 is formed on the channel layer 5.

At this time, the p ⁻ type base region 3, the n ⁺ type source region 4, and the n ⁻ type channel layer 5 have different impurity concentrations, so that accelerated oxidation occurs at a portion where the impurity concentration is high. However, as described above, since the low concentration compared to the region 4a to leave space 4b without oxidizing for oxidizing of the n ⁺ -type source region 4 serving as a base, oxidizing the n ⁺ -type source region 4 It is possible to suppress the accelerated oxidation at the time. When the experiment was performed, as described above, when the region 4b was set to 1 × 10 ²⁰ cm ⁻³ or less (preferably 1 × 10 ¹⁹ cm ⁻³ or less), 1400 ° C. or more, 1500 ° C. or more, 1600 ° C. or more. When the gate oxide film 7 is formed with respect to those subjected to the activation heat treatment at the respective temperatures, the accelerated oxidation is suppressed, and the oxide films on the n ⁻ type channel layer 5 and the n ⁺ type source region 4 are substantially suppressed. The result that thickness was made equal was obtained.

For this reason, it is possible to suppress an increase in sheet resistance due to the thinning of the n ⁺ type source region 4. Then, it can be performed only by adjusting the concentration of impurity ion implantation at the time of forming the n ⁺ -type source region 4, and there is no structural difference from the conventional structure, so that there is no increase in on-resistance or manufacturing process. Such an effect can be obtained.

[Step shown in FIG. 4 (c)]
A polysilicon layer is deposited on the gate oxide film 7 by, for example, LPCVD. The film forming temperature at this time is set to 600 ° C., for example. Then, the gate electrode 8 is formed by patterning the polysilicon layer.

[Step shown in FIG. 5A]
Subsequently, after unnecessary portions of the gate oxide film 7 are removed, an insulating film 9 made of LTO is formed at 425 ° C., for example, and further annealed at about 1000 ° C. to cover the gate electrode 8. Then, the insulating film 9 is patterned to form contact holes.

[Step shown in FIG. 5B]
Thereafter, after the source electrode 10 and the drain electrode 11 are arranged by metal sputtering at room temperature, annealing is performed at 1000 ° C. after the film formation, whereby the vertical power MOSFET shown in FIG. 1 is completed.

As described above, in this embodiment, since the region 4b to be oxidized in the n ⁺ type source region 4 serving as the base is lower in concentration than the region 4a that remains without being oxidized, the n ⁺ type source It is possible to suppress accelerated oxidation when the region 4 is oxidized. Thereby, it is possible to suppress an increase in sheet resistance due to the thinning of the n ⁺ type source region 4. This can be performed only by adjusting the concentration of ion implantation at the time of forming the n ⁺ -type source region 4, and there is no structural difference from the conventional structure. Such effects can be obtained.

In the case of the manufacturing method as in the present embodiment, the surface layer region 4 b of the n ⁺ -type source region 4 may remain partially oxidized even after the gate oxide film 7 is formed. In such a case, in the step of FIG. 5A, after forming a contact hole in the insulating film 9, an ion implantation and heat treatment step for increasing the impurity concentration of the surface layer portion of the n ⁺ type source region 4 is performed. In other words, the step of etching and removing the surface layer portion of the n ⁺ -type source region 4 may be performed as necessary.

(Other embodiments)
In the above embodiment, the case where the n ⁺ -type source region 4 is formed by ion implantation of n-type impurities has been described as an example, but may be formed by epitaxial growth. For example, after the step of FIG. 2C, the regions 4a and 4b are epitaxially grown in order with different impurity concentrations, and then the regions 4a and 4b are etched in the region for forming the n ⁻ -type channel layer 5. . After the mold channel layer 5 is epitaxially grown, for example, n by CMP (Chemical Mechanical Polishing) or the like ^{- -} n in this state by flattening the type channel layer 5, so that the surface of the region 4b remains. Thereafter, a semiconductor device having the same structure as described above can be manufactured by performing the steps after FIG. Thus, the n ⁺ type source region 4 may be formed by epitaxial growth. However, it is considered that accelerated oxidation is particularly promoted by defects caused by impurity ion implantation. Therefore, it is more effective to apply the present invention when the n ⁺ -type source region 4 is formed by ion implantation.

In each of the above-described embodiments, the case where the present invention is applied to an n-channel type MOSFET in which the n ⁻ -type layer is the n ⁻ -type channel layer 5 has been described. Of course, the p-channel type in which the conductivity type of each component is reversed. It is also possible to apply to this MOSFET.

In the above embodiment, the gate oxide film is formed by a thermal oxidation process. However, even when the gate oxide film is formed by depositing TEOS or the like by CVD or the like, it can be applied when performing thermal oxidation in the sacrificial oxidation process. . That is, in the above-described embodiment, the case where the n ⁺ type source region 4 is prevented from being thinned when the gate oxide film 7 is thermally oxidized has been described. However, the sacrificial oxidation before the gate oxide film is formed also includes the gate oxidation. The same problem as when the film is formed by thermal oxidation occurs. For this reason, also in the case of performing sacrificial oxidation, similarly to the above, since the region 4b to be oxidized in the n ⁺ -type source region 4 serving as the base is lower in concentration than the region 4a that remains without being oxidized, It is possible to suppress accelerated oxidation when the n ⁺ -type source region 4 is sacrificial oxidized. In this case, the above effect can be obtained even when the gate oxide film 7 is formed by CVD or the like. Of course, if the gate oxide film 7 is formed by thermal oxidation, the n ⁺ -type source serving as a base is taken into account by taking into account the amount oxidized by sacrificial oxidation and the amount oxidized thermally when forming the gate oxide film 7. What is necessary is just to determine the thickness of the area | region 4b for oxidizing among the area | regions 4. FIG.

Further, in the above embodiment, the storage type MOSFET having the n ⁻ type channel layer 5 is taken as an example, but the structure in which the n ⁻ type channel layer 5 is not formed, that is, the surface layer portion of the p ⁻ type base region 3 is used. Of these, the problem of thinning the n ⁺ -type source region 4 due to the difference in impurity concentration when forming the gate oxide film 7 is also applied to the inversion-type MOSFET in which the channel region is set in the portion facing the gate electrode 8. Therefore, the present invention can be applied. In this case, the gate oxide film 7 is formed by thermal oxidation of the n ⁻ type epi layer 2 and the n ⁺ type source region 4 serving as a drift layer, but the region on the upper layer side of the n ⁺ type source region 4 If the impurity concentration of 4b is lower than that of the lower region 4a, the same effect as described above can be obtained. In this case, it is of course possible to apply to a p-channel type MOSFET in which the conductivity type of each component is inverted.

Although the MOSFET has been described here as an example, the present invention is also applied to an IGBT (insulated gate bipolar transistor) obtained by inverting the conductivity type of the n ⁺ type substrate 1 to the p type. Can do.

It is sectional drawing of the planar type MOSFET manufactured by the manufacturing method of the SiC semiconductor device concerning 1st Embodiment of this invention. FIG. 7 is a cross-sectional view showing a manufacturing process of the vertical power MOSFET shown in FIG. 1. FIG. 3 is a cross-sectional view showing a manufacturing step of the vertical power MOSFET following that of FIG. 2. FIG. 4 is a cross-sectional view showing the manufacturing process of the vertical power MOSFET continued from FIG. 3. FIG. 5 is a cross-sectional view showing the manufacturing process of the vertical power MOSFET continued from FIG. 4. It is sectional drawing which showed a mode when an n ⁺ type | mold source region was thinned. It is the figure which showed the relationship of the contact resistance with respect to the impurity concentration of an n ^<+> type source region. It is the figure which showed the relationship of the ratio of the thermal oxide film on an n ^<+> type source region with respect to a thermal oxide film thickness, and the sort resistance of an n ^<+> type source region.

Explanation of symbols

1 ... ^{n +} -type substrate, 1a ... main surface, 1b ... rear surface, 2 ... n ^over type epitaxial layer, 3 ... p ^over type base region, 4 ... ^{n +} -type source region, 5 ... n ^- -type channel layer, 7 ... Gate oxide film, 8 ... gate electrode, 9 ... insulating film, 10 ... source electrode, 11 ... drain electrode, 20-22 ... LTO film, 23 ... resist

Claims (12)

A substrate (1) made of silicon carbide;
A drift layer (2) made of silicon carbide of the first conductivity type formed on the substrate (1);
A base region (3) of a second conductivity type formed in a surface layer portion of the drift layer (2) in the drift layer (2);
A first conductivity type source region (4) formed in the base region (3) and made of silicon carbide having a higher impurity concentration than the drift layer (2);
First conductivity made of silicon carbide formed on the surface of the base region (3) and the drift layer (2) and formed to connect the drift layer (2) and the source region (4). A mold channel layer (5);
A gate oxide film (7) provided on the surface of the channel layer (5) and the source region (4);
A gate electrode (9) formed on the gate oxide film (7);
A source electrode (10) electrically connected to the source region (4);
A drain electrode (11) formed on the back side of the substrate (1),
A channel formed in the channel layer (5) is controlled by controlling a voltage applied to the gate electrode (8), and the source electrode is interposed via the source region (4) and the drift layer (2). (10) and a method for manufacturing a silicon carbide semiconductor device in which a semiconductor element for passing a current is configured between the drain electrode (11),
Forming a region (4a) located in a lower layer of the source region (4) at a first impurity concentration;
Forming a region (4b) located above the region (4a) located in the lower layer of the source region (4) at a second impurity concentration lower than the first impurity concentration;
Forming the gate oxide film (7) by thermally oxidizing the upper layer (4b) of the source region (4) and the channel layer (5). A method for manufacturing a silicon carbide semiconductor device. After the drift layer (2) is formed on the substrate (1) and the base region (3) is formed in the drift layer (2), the drift layer (2) and the base region (3) are formed. Forming the channel layer (5) on the surface of
By ion-implanting a first conductivity type impurity from above the channel layer (5), a region (4a) located in the lower layer of the source region (4) is formed, and the source region (4) A step of forming a region (4b) located in the upper layer of
2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, further comprising a step of forming the gate oxide film by the thermal oxidation. A substrate (1) made of silicon carbide;
A drift layer (2) made of silicon carbide of the first conductivity type formed on the substrate (1);
A base region (3) of a second conductivity type formed in a surface layer portion of the drift layer (2) in the drift layer (2);
A first conductivity type source region (4) formed in the base region (3) and made of silicon carbide having a higher impurity concentration than the drift layer (2);
A gate oxide film (7) provided on the surfaces of the drift layer (2) and the source region (4);
A gate electrode (9) formed on the gate oxide film (7);
A source electrode (10) electrically connected to the source region (4);
A drain electrode (11) formed on the back side of the substrate (1),
By controlling the voltage applied to the gate electrode (8), a channel is formed in the surface layer portion of the base region (3) facing the gate electrode (9), and the source region (4) and the drift layer ( 2), a method for manufacturing a silicon carbide semiconductor device in which a semiconductor element for passing a current between the source electrode (10) and the drain electrode (11) is configured,
Forming a region (4a) located in a lower layer of the source region (4) at a first impurity concentration;
Forming a region (4b) located above the region (4a) located in the lower layer of the source region (4) at a second impurity concentration lower than the first impurity concentration;
Forming the gate oxide film (7) by thermally oxidizing the upper region (4b) of the source region (4) and the drift layer (2). A method for manufacturing a silicon carbide semiconductor device. Forming the drift layer (2) on the substrate (1) and forming the base region (3) in the drift layer (2);
By ion-implanting the first conductivity type impurity into the base region (3), a region (4a) located in the lower layer of the source region (4) is formed, and the source region (4) The step of forming the region (4b) located in the upper layer is performed,
2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, further comprising a step of forming the gate oxide film by the thermal oxidation. In the step of forming the region (4b) located in the upper layer of the source region (4), the thickness of the region (4b) is set to ½ or more of the thickness of the gate oxide film (7). The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the silicon carbide semiconductor device is manufactured. The step of forming the region (4b) located in the upper layer of the source region (4) has an impurity concentration of the region (4b) of 1 × 10 ²⁰ cm ⁻³ or less. 6. A method for manufacturing a silicon carbide semiconductor device according to any one of items 1 to 5. The step of forming a region (4a) located in the lower layer of the source region (4) has an impurity concentration of the region (4a) of 3 × 10 ²⁰ cm ⁻³ or more. 7. A method for manufacturing a silicon carbide semiconductor device according to any one of items 6 to 6. The step of forming the region (4a) located in the lower layer and the step of forming the region (4b) located in the upper layer of the source region (4) include a step of performing an activation heat treatment at 1400 ° C. or higher. A method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein: The step of forming the region (4a) located in the lower layer and the step of forming the region (4b) located in the upper layer of the source region (4) include a step of performing an activation heat treatment at 1500 ° C. or higher. A method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein: The step of forming the region (4a) located in the lower layer and the step of forming the region (4b) located in the upper layer of the source region (4) include a step of performing an activation heat treatment at 1600 ° C. or higher. A method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein: A substrate (1) made of silicon carbide;
A drift layer (2) made of silicon carbide of the first conductivity type formed on the substrate (1);
A base region (3) of a second conductivity type formed in a surface layer portion of the drift layer (2) in the drift layer (2);
A first conductivity type source region (4) formed in the base region (3) and made of silicon carbide having a higher impurity concentration than the drift layer (2);
First conductivity made of silicon carbide formed on the surface of the base region (3) and the drift layer (2) and formed to connect the drift layer (2) and the source region (4). A mold channel layer (5);
A gate oxide film (7) provided on the surface of the channel layer (5) and the source region (4);
A gate electrode (9) formed on the gate oxide film (7);
A source electrode (10) electrically connected to the source region (4);
A drain electrode (11) formed on the back side of the substrate (1),
A channel formed in the channel layer (5) is controlled by controlling a voltage applied to the gate electrode (8), and the source electrode is interposed via the source region (4) and the drift layer (2). (10) and a method for manufacturing a silicon carbide semiconductor device in which a semiconductor element for passing a current is configured between the drain electrode (11),
Forming a region (4a) located in a lower layer of the source region (4) at a first impurity concentration;
Forming a region (4b) located above the region (4a) located in the lower layer of the source region (4) at a second impurity concentration lower than the first impurity concentration;
And carbonizing the region (4b) located in the upper layer of the source region (4) and the channel layer (5) by thermal oxidation and then removing the sacrificial oxide film. A method for manufacturing a silicon semiconductor device. A substrate (1) made of silicon carbide;
A drift layer (2) made of silicon carbide of the first conductivity type formed on the substrate (1);
A base region (3) of a second conductivity type formed in a surface layer portion of the drift layer (2) in the drift layer (2);
A first conductivity type source region (4) formed in the base region (3) and made of silicon carbide having a higher impurity concentration than the drift layer (2);
A gate oxide film (7) provided on the surfaces of the drift layer (2) and the source region (4);
A gate electrode (9) formed on the gate oxide film (7);
A source electrode (10) electrically connected to the source region (4);
A drain electrode (11) formed on the back side of the substrate (1),
By controlling the voltage applied to the gate electrode (8), a channel is formed in the surface layer portion of the base region (3) facing the gate electrode (9), and the source region (4) and the drift layer ( 2), a method for manufacturing a silicon carbide semiconductor device in which a semiconductor element for passing a current between the source electrode (10) and the drain electrode (11) is configured,
Forming a region (4a) located in a lower layer of the source region (4) at a first impurity concentration;
Forming a region (4b) located above the region (4a) located in the lower layer of the source region (4) at a second impurity concentration lower than the first impurity concentration;
A step of sacrificing the region (4b) located in the upper layer of the source region (4) and the drift layer (2) by thermal oxidation and then removing the sacrificial oxide film. A method for manufacturing a silicon semiconductor device.

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