JP3836252B2 - Substrate plating method - Google Patents

Description

【００３４】
一方、第２のめっき液の組成は、以下の通りである。
ＣｕＳＯ₄・５Ｈ₂Ｏ ２００ｇ／ｌ
Ｈ₂ＳＯ₄ ５０ｇ／ｌ
ＮａＣｌ １００ｍｇ／ｌ
有機添加物 ５ｍｌ／ｌ
また、めっき条件は、以下の通りである。

これにより、図６（ａ）に示すように、半導体基板Ｗの微細窪み１０内をバリア層１１との間にめっき未着部を生じることなく、ボイドフリーの銅めっき膜１４で埋めることができた。
【００３５】
（比較例１）
比較例１として、前記と同様な前処理を施した半導体基板Ｗに、前記第１のめっき液のみによるめっき処理を施したところ、図６（ｂ）に示すように、微細窪み１０内の銅めっき膜１４の内部にボイド３０が生じていたことが確認された。
【００３６】
（比較例２）
比較例２として、前記と同様な前処理を施した半導体ウエハに、前記第２のめっき液のみでめっき処理を施したところ、図６（ｃ）に示すように、微細窪み１０の底部の隅部にバリア層１１との間のめっき未着部３１が生じたことが確認された。
【００３７】
【発明の効果】
以上説明したように、本発明によれば、第１段めっき処理で、微細窪みを覆うバリア層との間にめっき未着部のない均一な初期めっき膜を形成し、第２段めっき処理で、この初期めっき膜の表面にボイドフリーで表面を平坦にした表面めっき膜を形成することで、微細な配線用の溝等の微細窪みに銅又は銅合金等の電気抵抗の小さい材料を隙間なく均一に、かつ表面を平坦に充填することができる。
【図面の簡単な説明】
【図１】本発明の基板のめっき方法によって製造される半導体素子の製造工程を示す断面図である。
【図２】本発明の実施の形態のめっき方法のプロセスを示す工程図である。
【図３】同じく、図２のプロセスの説明に付する断面図である。
【図４】レベリング性の説明に付する断面図である。
【図５】本発明の実施の形態のめっき装置を示す概略図である。
【図６】本発明の実施例１と比較例１及び２との差異を示す断面図である。
【符号の説明】
１０ 微細窪み
１１ バリア層
１２ 初期めっき膜
１３ 表面めっき膜
１４ めっき膜
２０ めっき槽
２１ 第１のめっき液
２２ａ，２２ｂ めっき液供給手段
２３ 第２のめっき液
２５ａ，２５ｂ 開閉弁
２６ａ，２６ｂ タイマ（切換手段）[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a plating how the substrate, particularly relates to a plating how application of a substrate such as filling the metal of copper (Cu) or the like in the depression for wiring formed on a semiconductor substrate.
[0002]
[Prior art]
Conventionally, in order to form a wiring circuit on a semiconductor substrate, after forming a conductor film on the substrate surface by sputtering or the like, an unnecessary portion of the film is further formed by chemical dry etching using a pattern mask such as a resist. Had been removed.
[0003]
Aluminum (Al) or an aluminum alloy has been used as a material for forming the wiring circuit. However, as the degree of semiconductor integration increases, the wiring becomes thinner and the current density increases, causing thermal stress and temperature rise. This becomes more conspicuous as Al or the like becomes thinner due to stress migration or electromigration, and finally there is a risk of disconnection or short circuit.
[0004]
Therefore, in order to avoid excessive heat generation due to energization, it is required to employ a material such as copper having higher conductivity for wiring formation. However, copper or an alloy thereof is difficult to dry-etch, and it is difficult to adopt the above-described method of forming a pattern after the entire surface is formed. Therefore, a process of forming a wiring groove having a predetermined pattern in advance and filling copper or an alloy thereof therein may be considered. According to this, the process of removing the film by etching is unnecessary, and a polishing process for removing the surface step may be performed. Further, there is an advantage that portions called plugs that connect the upper and lower sides of the multilayer circuit can be formed simultaneously.
[0005]
[Problems to be solved by the invention]
However, the shape of such a wiring groove or plug becomes a considerably high aspect ratio (ratio of depth to width) as the wiring width becomes finer, and uniform metal filling is difficult in sputtering film formation. In addition, a vapor deposition (CVD) method is used as a film forming means for various materials. However, it is difficult to prepare an appropriate gas source with copper or an alloy thereof, and when an organic source is used. However, there is a problem in that carbon (C) is mixed into the deposited film and migration is improved.
[0006]
Therefore, a method of performing electroless or electrolytic plating by immersing the substrate in a plating solution has been proposed. In film formation by such plating, it becomes possible to uniformly fill the high-aspect-ratio wiring grooves with metal.
[0007]
Here, for example, in electrolytic copper plating, a copper sulfate plating solution containing copper sulfate and sulfuric acid in its composition is generally used as the plating solution. However, the periphery and bottom surface of the fine depression of the substrate are generally covered with a barrier layer such as TiN or TaN, and the sheet resistance value of this barrier layer is very large compared to the resistance value of the copper sulfate plating solution. For this reason, when copper is filled in the fine recesses covered with the barrier layer by the plating process using the copper sulfate plating solution, there is a problem that a plating film having poor adhesion is formed.
[0008]
On the other hand, copper pyrophosphate plating solution with excellent adhesion is widely used due to the property of layered precipitation, but this pyrophosphate plating solution is inferior in leveling property, and therefore, copper pyrophosphate plating When copper is filled into the fine pits by plating using a liquid, there is a problem that the entrance of the fine pits is closed first and so-called voids are easily generated.
[0009]
The present invention has been made in view of the above circumstances so that a material having a small electrical resistance such as copper or a copper alloy can be uniformly filled in a minute recess such as a groove for fine wiring without gaps and the surface can be filled flat. and to provide a plating how the substrate was.
[0010]
[Means for Solving the Problems]
In the substrate plating method of the present invention, a semiconductor substrate having a fine depression with a width of 1.0 μm or less covered with a barrier layer is immersed in a copper pyrophosphate plating solution to perform a first stage plating treatment, and the barrier An initial plating film is formed on the wall surface and bottom surface of the fine depression covered with the layer, and the second plating process is performed by immersing the semiconductor substrate on which the initial plating film is formed in a copper sulfate plating solution. A surface plating film is formed on the surface of the substrate. That is, in a method for plating a substrate in which a substrate having a fine depression with a barrier layer formed thereon is subjected to electrolytic plating and filling the fine depression with a metal, the substrate has a composition with excellent adhesion to the barrier layer of the substrate. It is characterized in that after the first plating process is performed by immersing in the first plating solution, the second plating process is performed by immersing in the second plating solution having an excellent leveling property.
[0011]
As a result, a uniform initial plating film having no unplated portion is formed on the wall surface and bottom surface of the fine depression covered with the barrier layer in the first stage plating process, and this initial plating film is formed in the second stage plating process. It is possible to form a surface plating film with a void-free surface and a flat surface.
[0012]
Further, a copper pyrophosphate plating solution is used as the first plating solution, and a copper sulfate plating solution is used as the second plating solution, respectively. The copper pyrophosphate plating solution is excellent in adhesion to the barrier layer such as TiN due to its layered precipitation property, and the copper sulfate plating solution with high copper sulfate concentration and low sulfuric acid concentration is leveling property. Is excellent. Thereby, the copper plating which filled the copper uniformly in the fine hollow covered with the barrier layer without a gap, and made the surface flat can be performed.
[0013]
Furthermore, as the copper sulfate plating solution, one having a composition of copper sulfate 100 to 300 g / l and sulfuric acid 10 to 100 g / l is used.
[0014]
Further, the substrate plating apparatus includes a plating tank, a first plating solution supply means for supplying the plating tank with a first plating solution having a composition having excellent adhesion to the barrier layer of the substrate, and the plating tank. A second plating solution supply means for supplying a second plating solution having a composition excellent in leveling properties; and a switching means for switching the supply of the plating solution by the first plating solution supply means and the second plating solution supply means; It is characterized by having.
[0015]
Thereby, first, the first plating solution having a composition excellent in adhesion to the barrier layer of the substrate is supplied into the plating tank to perform the first stage plating treatment of the substrate, and then the supply of the plating solution is switched. By supplying the second plating solution having a composition with excellent leveling property and performing the second stage plating process of the substrate, the first stage plating process and the second stage plating process are continuously performed in the same facility. Can do.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The plating method of this embodiment is used to obtain a semiconductor device in which a wiring made of a copper layer is formed by performing copper plating on the surface of a semiconductor substrate. This process is described with reference to FIG. I will explain.
[0017]
That is, the semiconductor the substrate W, as shown in FIG. 1 (a), an insulating film 2 made of SiO ₂ is deposited on a conductive layer 1a on a semiconductor substrate 1 on which semiconductor devices are formed, lithography etching A contact hole 3 and a wiring groove 4 are formed by a technique, and a barrier layer 5 made of TiN or the like is formed thereon.
[0018]
Then, as shown in FIG. 1B, the copper layer 6 is filled in the contact holes 3 and the grooves 4 of the semiconductor substrate 1 by performing copper plating on the surface of the semiconductor substrate W, and the insulating film 2 A copper layer 6 is deposited thereon. Thereafter, the copper layer 6 on the insulating film 2 is removed by chemical mechanical polishing (CMP), and the surface of the copper layer 6 filled in the contact hole 3 and the wiring groove 4 and the surface of the insulating film 2 Are almost coplanar. As a result, a wiring made of the copper layer 6 is formed as shown in FIG.
[0019]
Hereinafter, a process for performing electrolytic copper plating on the semiconductor substrate W shown in FIG. 1A will be described with reference to FIG. First, a pretreatment for activating the semiconductor substrate W by immersing the semiconductor substrate W in, for example, an aqueous sulfuric acid solution is performed.
[0020]
Next, after washing this with water, it is immersed in a first plating solution, for example, a copper pyrophosphate plating solution, and a first stage plating treatment is performed. As a result, as shown in FIG. A uniform initial plating film 12 is formed on the surface including the barrier layer 11 covering the side surface and the bottom surface of the fine recess 10.
[0021]
Thus, the copper pyrophosphate plating solution is excellent in adhesion with the barrier layer 11 such as TiN from the property of layered precipitation, thereby obtaining an initial plating film 12 with good uniform electrodeposition, It is possible to prevent an unattached portion from being formed between the barrier layer 11 covering the fine recess 10.
[0022]
Then, after washing this with water, it is immersed in a second plating solution, for example, a copper sulfate plating solution, to perform a second stage plating treatment, thereby, as shown in FIGS. 3 (b) and (c), A flat surface plating film 13 is formed on the surface of the initial plating film 12. Here, as a copper sulfate plating solution, a copper sulfate plating solution having a high copper sulfate concentration and a low sulfuric acid concentration and excellent leveling properties, for example, a composition of copper sulfate 100 to 300 g / l, sulfuric acid 10 to 100 g / l Use one.
[0023]
Here, the leveling property means the property with respect to the surface flatness, and when the leveling property is good, as shown in FIG. A plating film 16a can be obtained. On the other hand, if the leveling property is poor, a plating film 16b is obtained in which the shape of the recess 15 on the surface of the substrate W remains on the surface as shown in FIG. be able to.
[0024]
Thus, in the plating solution excellent in leveling property, as shown in FIG. 3B, the film growth at the entrance of the fine depression 10 is slowed, thereby preventing the generation of voids, The fine recess 10 can be filled with copper uniformly without any gaps, and the surface can be flattened.
[0025]
After that, it is washed with water and dried to finish the plating process, so that there is no occurrence of an unplated portion with the barrier layer 11 covering the fine depression 10, and it is void-free. In addition, the plating film 14 having a flat surface can be obtained.
[0026]
A plating apparatus suitable for the plating process is shown in FIG.
In this plating apparatus, a plating tank 20, a first plating solution supply means 22 a for supplying the first plating solution 21 to the inside of the plating tank 20, and a second for supplying the second plating solution 23. The plating solution supply means 22b is provided.
[0027]
The first plating solution supply means 22a is provided with a pump 24a for sending the first plating solution 21 to the plating tank 20, and an on-off valve 25a is disposed upstream of the pump 24a. A timer 26a is provided as switching means for opening and closing 25a.
[0028]
Similarly, the second plating solution supply means 22b is provided with a pump 24b for sending the second plating solution 23 to the plating tank 20, and an opening / closing valve 25b is disposed upstream of the pump 24b. A timer 26b is provided as switching means for opening and closing 25b.
[0029]
Furthermore, a washing water supply pipe 27 for introducing washing water into the plating tank 20 and a drain pipe 28 for draining the washing water in the plating tank 20 to the outside are connected to the plating tank 20. The pump 29 is connected.
[0030]
Then, the semiconductor substrate that has been pretreated as described above is placed in the plating tank 20, and after washing water is first introduced into the plating tank 20, the first washing is performed via the timer 26 a. The on-off valve 25a of the plating solution supply means 22a is opened, and the first plating solution 21 is supplied into the plating tank 20 to perform the first stage plating process. Then, after a lapse of a certain time, the on-off valve 25a is closed, washing water is introduced into the plating tank 20 and washing is performed, and then the second plating solution supply means 22b is opened and closed via the timer 26b. The valve 26b is opened, the second plating solution 23 is supplied into the plating tank 20, and the second-stage plating process is performed. Thus, the first-stage plating process and the second-stage plating process are continuously performed with the same equipment. Can be done.
[0031]
In this example, an example is shown in which a timer is used as the switching means for switching the supply of the plating solution, but it is needless to say that any means other than the timer may be used.
[0032]
【Example】
Example 1
A fine depression 10 having a width of 1.0 μm or less is formed on the semiconductor substrate W, this fine depression 10 is covered with a barrier layer 11 and immersed in a 100 g / l sulfuric acid aqueous solution maintained at 50 ° C. for 15 seconds. After the pretreatment, the first stage plating process using the first plating solution was performed, and the second stage plating process using the second plating solution was performed after washing with water. Then, it was washed with water and dried.
[0033]
Here, the composition of the first plating solution is as follows.
Cu ₂ P ₂ O ₇ · 3H ₂ O 90g / l
H ₄ P ₂ O ₇ 340 g / l
Ammonia 3ml / l
Organic additive 0.5ml / l
The plating conditions are as follows.

[0034]
On the other hand, the composition of the second plating solution is as follows.
CuSO ₄ · 5H ₂ O 200g / l
H ₂ SO ₄ 50 g / l
NaCl 100 mg / l
Organic additive 5ml / l
The plating conditions are as follows.

As a result, as shown in FIG. 6A, the inside of the fine recess 10 of the semiconductor substrate W can be filled with the void-free copper plating film 14 without generating a plating unattached portion between the semiconductor substrate W and the barrier layer 11. It was.
[0035]
(Comparative Example 1)
As Comparative Example 1, a semiconductor substrate W subjected to the same pretreatment as described above was subjected to a plating treatment using only the first plating solution, and as shown in FIG. It was confirmed that the void 30 was generated inside the plating film 14.
[0036]
(Comparative Example 2)
As Comparative Example 2, a semiconductor wafer that had been subjected to the same pretreatment as described above was subjected to a plating treatment using only the second plating solution. As shown in FIG. It was confirmed that an unplated portion 31 between the barrier layer 11 and the barrier layer 11 was generated.
[0037]
【The invention's effect】
As described above, according to the present invention, in the first stage plating process, a uniform initial plating film without a plating unattached portion is formed between the barrier layer covering the fine depressions, and the second stage plating process. By forming a void-free surface plating film on the surface of this initial plating film, a material with low electrical resistance such as copper or copper alloy can be placed in a fine recess such as a groove for fine wiring without any gaps. The surface can be uniformly and evenly filled.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor device manufactured by a substrate plating method of the present invention.
FIG. 2 is a process diagram showing a process of a plating method according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view for explaining the process of FIG. 2;
FIG. 4 is a cross-sectional view for explaining leveling properties.
FIG. 5 is a schematic view showing a plating apparatus according to an embodiment of the present invention.
6 is a cross-sectional view showing a difference between Example 1 of the present invention and Comparative Examples 1 and 2. FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Fine hollow 11 Barrier layer 12 Initial plating film 13 Surface plating film 14 Plating film 20 Plating tank 21 1st plating solution 22a, 22b Plating solution supply means 23 2nd plating solution 25a, 25b On-off valve 26a, 26b Timer (switching) means)

Claims (2)

A semiconductor substrate having a fine depression with a width of 1.0 μm or less covered with a barrier layer is immersed in a copper pyrophosphate plating solution to perform a first stage plating process, and the wall surface of the fine depression covered with the barrier layer An initial plating film is formed on the bottom surface and the semiconductor substrate on which the initial plating film is formed is immersed in a copper sulfate plating solution to perform a second stage plating process, and a surface plating film is formed on the surface of the initial plating film A method for plating a substrate. As the copper sulfate plating solution, the plating method of a substrate according to claim 1, wherein the use of those compositions of copper sulfate 100 to 300 g / l, sulfuric acid 10 to 100 g / l.

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