JP2007084891A - Method for forming plating film for wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a wiring layer or a via in which the generation of voids in a plating layer is suppressed when copper electroplating is performed to a trench or a via hole with a high aspect ratio formed at an insulating layer. <P>SOLUTION: A film containing an additive accelerating electroplating is selectively formed on the bottom face part of a trench or a via hole, and then, copper electroplating is performed. The plating acceleration additive-containing film at the bottom face part is formed by performing aeration as an opening board for plating formation is dipped into a plating acceleration additive-containing solution, so as to remove bubbles in the opening part, and thereafter performing a spin rinsing process and drying treatment. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for forming a plating film on a wiring board, and in particular, when copper wiring such as wiring grooves (trench) and wiring connection holes (vias) having a fine and high aspect ratio is formed in an insulating layer on the board, The present invention relates to a copper electroplating method that can effectively suppress the generation of voids.

  The electroplating method of copper is widely used in electronic products because of the excellent electrical characteristics and cost performance of the plated film produced. Particularly in recent years, a technique called a damascene process, which forms a fine wiring pattern by copper electroplating on various wiring boards such as a semiconductor integrated circuit forming board, a high-density multilayer wiring board, or a head component board of a hard disk drive, has attracted attention. .

  An example of the damascene process will be described with reference to the substrate cross-sectional view of FIG. For example, a wiring trench (trench) or a wiring connection hole (via hole) is formed in an insulating film 102 such as an interlayer insulating film formed on a substrate 101 such as a semiconductor substrate having a lower structure in which a device is formed. Open. Next, a laminated film 104 including a barrier layer for preventing the diffusion of the wiring material and a seed layer for facilitating the plating growth of the wiring material is formed on the insulating film 102 including the inside of the groove and the hole. In general, as a additive to sulfuric acid / copper sulfate solution, a polymeric surfactant (for surface plating suppression effect), a sulfuric acid-containing unsaturated organic compound (for hole plating promotion effect), and halogen ions (enhance each of the above effects) For example, after embedding a copper wiring material in a groove or a hole by electroplating using a plating solution made of a suitable amount of an additive, a copper film formed on the insulating layer 102 is subjected to chemical mechanical polishing (CMP). ; Removal and planarization by performing chemical mechanical polishing, and, for example, a copper via 103 is formed in the insulating film 102.

  Originally, electroplating of copper or the like has good plating metal embedding performance with respect to a substrate having a step such as embedding in a hole or groove as described above, and an organic additive contained in the electroplating solution. The level difference is also flattened by adjusting the density.

  However, with the miniaturization and high functionality of semiconductor devices, etc., as the wiring and vias become finer and denser, the groove width and via hole diameter become smaller and the aspect ratio (groove depth / via The ratio of the groove width / via hole diameter to the hole depth) increases. When forming a film by copper electroplating in a recess such as a groove or hole having a high aspect ratio (that is, filling and filling with copper), there is a problem that voids are likely to be generated inside the groove or hole. ing.

  The reason why such a void occurs will be described with reference to FIG. FIGS. 7A and 7B are cross-sectional views of the substrate in the copper electroplating process in the damascene process. In FIG. 7A, a via hole 106 is formed in a high aspect ratio in an insulating film 102 formed on a substrate 101, and a laminate composed of a barrier layer and a seed layer is formed on the insulating film 102 and in the via hole 106. A film 104 is formed. Here, a copper plating layer 105 is deposited and grown by copper electroplating. The copper plating layer 105 deposited / grown on the laminated film 104 is deposited / grown in the via hole 106 not only from the bottom but also from the side as shown by the arrow A in the figure. Since the growth in each surface is not uniform, the copper plating films deposited and grown from the side surface before the inside of the via hole 106 is completely filled are brought into contact with each other. As a result, FIG. As shown in FIG. 2, a void 107 is formed in the buried copper of the via 103. The generation of such voids 107 in the buried copper is more likely to occur as the aspect ratio of the grooves and holes is higher, and causes an increase in wiring resistance and eventually a disconnection failure.

Until now, various proposals have been made to avoid the generation of such voids. For example, a method for improving the adhesion of plating on the bottom surface by irradiating an energy beam toward the bottom surface of a groove or hole (Patent Document 1). After forming a copper plating film, the whole is heated in a high-pressure gas atmosphere to form pores. A method of forming a wiring film that does not contain (vacancy) (Patent Document 2), electrochemically monitoring using a specific test piece, and controlling the concentration of an accelerator or inhibitor of an electrolytic copper plating solution A method for forming a uniform copper plating film (Patent Document 3), or a plating solution composition containing a certain amount of polymer components and halogen ions as additives without using a sulfuric acid-containing unsaturated organic compound. There has been proposed a method of forming a plated buried layer without any problem (Patent Document 4).
JP-A-11-87276 JP 2000-200809 A JP 2002-368384 A JP 2003-321792 A

  However, the proposed method as described above is a special apparatus for applying the method, a point that many processing steps are required (the method of Patent Documents 1 to 3), and a plating solution. There is still a problem that the yield cannot be increased because there is still a point that it is difficult to maintain and control the component ratio of the additive in the composition during the plating process in which it is consumed (Patent Document) Method 4).

  Therefore, an object of the present invention is to use an apparatus used in a normal semiconductor manufacturing process, and can be easily implemented, and suppresses generation of voids due to electrolytic copper plating in a high aspect ratio groove or via hole. It is an object of the present invention to provide a method for forming a copper plating film that can be used.

  An object of the present invention is to provide a first step of forming a wiring groove or / and a wiring connection hole in an insulating film on a substrate, and a barrier on the insulating film and the wiring groove or / and the wiring connection hole. A second step of forming a film; a third step of depositing a plating accelerating additive-containing film containing a plating accelerating additive in the wiring groove or / and the wiring connecting hole in which the barrier film is formed; Plating a wiring board, characterized by having a fourth step of filling a copper film or a copper alloy film by plating into the wiring groove or / and wiring connection hole where the plating promoting additive-containing film is deposited. This is made possible by the film forming method.

  The plating promoting additive is sodium 3-mercapto-1-propanesulfonate, sodium 2-mercaptoethanesulfonate, or bis- (3-sulfopropyl) -disulfide.

  Further, the third step is a step in which the plating promoting additive-containing film is selectively deposited on the wiring groove or / and the bottom surface of the wiring connection hole in which the barrier film is formed. Features.

  The third step is a chamber in which the substrate on which the barrier film is formed is immersed in a solution containing the plating accelerating additive in a container and the container is evacuated after the second step. A fifth step of removing the substrate on which the barrier film is formed from the solution, and a sixth step of removing the solvent in the solution adhering to the substrate on which the barrier film is formed. It is characterized by having.

  Further, the third step further includes a seventh step of selectively leaving the solution on the bottom surface by a spin-rinse method after the fifth step.

  By applying the above method, when copper is embedded in an opening such as a wiring groove or / and a wiring connection hole formed on the substrate by a copper electroplating method, a film containing a plating accelerating additive is formed on the bottom of the opening Therefore, in the initial stage of the electroplating process, the plating promoting additive-containing film dissolves, the concentration of the promoting additive in the plating solution in the vicinity thereof increases, and the deposition rate of the copper plating film on the bottom surface portion increases. It is relatively higher than other parts. This effect can solve the problem that voids (holes) are generated inside the grooves and holes, which has been conventionally observed in grooves and holes having a high aspect ratio. Further, this method can be performed with an apparatus usually used in a semiconductor manufacturing process, and can be performed relatively easily.

  Embodiments of the present invention will be described below with reference to the accompanying drawings.

(Embodiment)
1 to 5 are process cross-sectional views for explaining an embodiment of the present invention. In FIG. 1, an interlayer made of SiO2, SiN, SiON, a low dielectric film or the like is formed on a substrate 1 such as a semiconductor substrate having a lower structure such as a MOS transistor by, for example, a CVD method, a sputtering method, or a coating method. An insulating film 2 constituting an insulating film or the like is formed. Next, after applying a resist and performing exposure and development by photolithography to form a resist pattern, a trench (wiring groove) or a via hole (wiring connection hole) is formed in this insulating film 2 using known dry etching. 3 is opened. In FIG. 1, two openings having the shape of the via hole 3 are arranged. In this opening, a trench and a via hole are arbitrarily arranged, or a trench is formed above the via hole. For example, an opening having a structure in which a via and a wiring layer are integrally formed using a dual damascene process may be disposed. Then, a barrier layer for preventing the diffusion of the wiring material Cu, which is composed of a single layer of Ti, TiN, Ta, TaN, WN or the like, or two or more layers that are a combination thereof, is formed thereon by using a sputtering method. Then, a Cu seed layer that facilitates the plating growth of Cu as a wiring material is formed, and a laminated film 4 made of these films is formed to obtain a barrier film laminated substrate on which a barrier layer and the like are formed.

  Next, 5% by weight of 3-mercapto-1-propanesulfonic acid, which is a plating accelerating additive, is added to pure water to prepare a plating accelerating additive aqueous solution. Then, the aforementioned barrier film laminated substrate is immersed. At this time, as shown in FIG. 2A, in the case of a groove or via hole having a particularly high aspect ratio, the plating accelerating additive aqueous solution 5 reaches the inside of the opening such as the via hole 3 of the barrier film laminated substrate. The air bubbles 6 are inherently present in the via hole 3 without entering. In order to remove the bubbles 6, the container in which the barrier film laminated substrate is immersed is placed in a chamber that can be evacuated and decompressed, thereby removing the bubbles 6 as shown in FIG. The plating promoting additive aqueous solution 5 is surely entered into the bottom surface of the opening of the hole 3.

  Next, the substrate in the solution from which bubbles in the opening have been removed is taken out and placed on a wafer (substrate) mounting table of a spin coater used for coating a photoresist film or the like. A 1 minute rotation was applied. By this rotation operation, as shown in FIG. 3A, the plating promoting additive aqueous solution 5 remains on the bottom surface of the via hole 3, and the plating promoting additive adhering to the vicinity of the substrate surface, the surface inside the trench or via hole is adhered. The aqueous agent solution 5 can be scattered. Such a method of immersing the substrate or the like in the solution and then removing the solution unnecessarily adhered to the substrate by spinning is called a spin rinse method or spin rinsing.

  Then, this spin rinsing method is applied, and the substrate in which the plating promoting additive aqueous solution 5 remains on the bottom surface of the via hole 3 is placed in a thermostatic bath and dried at, for example, 80 ° C. for 2 minutes to obtain a solvent (in this case 3), the plating promoting additive (in this case, 3-mercapto-1-propanesulfonic acid) was selectively deposited on the bottom surface of the via hole 3 as shown in FIG. A plating promoting additive-containing film 7 is formed.

  As described above, the above-mentioned methods for performing the spin-rinse method using a solution and heat-drying are both methods that use an apparatus that is usually frequently used in a semiconductor manufacturing process and can be easily applied. It is.

  Next, after returning a board | substrate to room temperature, copper electroplating is performed using a well-known copper electroplating liquid and an electroplating apparatus. In an initial stage after the start of copper electroplating, the plating promoting additive-containing film 7 formed on the bottom surface of the via hole 3 is dissolved, and the concentration of the plating promoting additive in the plating solution near the bottom surface of the via hole 3 is reduced. Relatively high. As a result, as illustrated by arrow B in FIG. 4A, the deposition rate of the copper plating film 8 from the vicinity of the bottom surface portion of the via hole 3 becomes faster than that of the side surface portion of the via hole 3, Growth of the copper plating film 8 from the bottom surface precedes with a constant thickness. Thereafter, the normal copper plating film 8 is continuously deposited and grown. In this way, generation of voids that are likely to be formed in deep portions of via holes having a particularly high aspect ratio was suppressed, and as shown in FIG. 4B, a copper plating film 8 having no voids in the vias 9 could be obtained. .

  Then, by performing well-known chemical mechanical polishing (CMP), the copper plating film 8 formed on the insulating layer 2 is removed and planarized. As shown in FIG. A so-called superfilled via 9 completely free of voids and completely filled with copper could be formed.

  The experiment by the above method is, for example, that the insulating film thickness 2 is about 1 μm, the diameter of the via hole 3 or the wiring groove is about 200 nm to 300 nm, and accordingly, the aspect ratio is 3.3 to 5.0. It was confirmed that each of the openings was formed in a superfilling situation.

  As described above, the method of the present invention is particularly effective in the process of embedding copper by electrolytic copper plating in a groove or hole having a high aspect ratio, in which the generation of voids (holes) is effectively suppressed. Can be formed relatively easily without using a special apparatus.

  In the above-described embodiment, an example in which sodium 3-mercapto-1-propanesulfonate is used as a plating accelerating additive has been described. Instead, sodium 2-mercaptoethanesulfonate or bis- (3 Even when -sulfopropyl) -disulfide was used, the same effective results could be obtained by applying the method of the present invention.

  Further, in the above-described embodiments, the wiring formation related to copper has been described. However, the same effect can be obtained even in a copper alloy by applying the method of the present invention.

  In addition, although the above embodiment has basically been described in the case of applying a so-called single damascene process, it goes without saying that it can also be applied to a so-called dual damascene process in which vias and wirings are formed simultaneously.

  Furthermore, although the example which applied pure water as a solvent of a plating acceleration additive was described, it is not restricted to this, Organic solvents (For example, alcohols, such as ethyl alcohol, methyl alcohol, isopropylol alcohol, or these aqueous solution) ) Can also be applied. However, when forming the plating accelerating additive-containing film, attention should be paid to fire when the organic solvent is evaporated at a high temperature and dried. When pure water is used, it is simple in this respect and no special attention is required.

  When complete evaporation of the solvent is difficult or as a result is insufficient, there may be a case where a part of the solvent remains in the plating accelerating additive-containing film. Since the solvent component of the copper electroplating solution used is water, if the same pure water is used as the solvent for the plating acceleration additive solution, the water component remains in the plating acceleration additive-containing film. However, in the electroplating process using the plating solution performed thereafter, there is an advantage that no particular inconvenience occurs.

  The concentration of the solution containing the plating accelerating additive is not limited to the above-mentioned 5% by weight, and an appropriate film containing a plating accelerating additive for appropriately embedding the width of the groove, the diameter of the groove, the aspect ratio, and copper. The concentration can be changed as appropriate depending on the thickness and the composition of the plating solution. Further, the rotation speed and the rotation time in the spin / rinse method are not limited to the above-mentioned numerical values, and can be appropriately changed according to various conditions in forming the plating film.

  Regarding the embodiment including the above examples, the following additional notes are disclosed.

(Appendix 1) a first step of forming a wiring groove or / and a wiring connection hole in an insulating film on a substrate;
A second step of forming a barrier film on the insulating film and in the wiring groove or / and the wiring connection hole;
A third step of depositing a plating accelerating additive-containing film containing a plating accelerating additive in the wiring groove or / and the wiring connecting hole in which the barrier film is formed;
Plating a wiring board, characterized by having a fourth step of filling a copper film or a copper alloy film by plating into the wiring groove or / and wiring connection hole where the plating promoting additive-containing film is deposited. Film forming method.

  (Appendix 2) The plating accelerator additive is sodium 3-mercapto-1-propanesulfonate, sodium 2-mercaptoethanesulfonate, or bis- (3-sulfopropyl) -disulfide. The method for forming a plating film on a wiring board according to appendix 1.

  (Additional remark 3) The said 3rd process is a process in which the said plating acceleration additive containing film | membrane is selectively deposited in the bottom face part of the said groove | channel for wiring and / or wiring connection hole in which the said barrier film was formed. The method for forming a plating film on a wiring board according to appendix 1 or 2, wherein:

  (Additional remark 4) The said 3rd process can immerse the board | substrate with which the said barrier film was formed in the solution containing the said plating acceleration additive in a container after the said 2nd process, and can exhaust the said container A fifth step of removing the substrate on which the barrier film is formed from the solution, and a sixth step of removing the solvent in the solution adhering to the substrate on which the barrier film is formed. The method for forming a plating film on a wiring board according to any one of appendices 1 to 3, further comprising the steps of:

  (Additional remark 5) The said 3rd process has the 7th process which selectively leaves the said solution on the said bottom face part by the spin rinse method after the said 5th process, The additional remark 4 characterized by the above-mentioned. A method for forming a plating film on a wiring board as described.

  (Additional remark 6) The plating film formation method of the wiring board in any one of Additional remark 1 thru | or 5 which forms a seed film | membrane in said 2nd process further.

  (Additional remark 7) The solvent of the said solution is a pure water, The plating film formation method of the wiring board of Additional remark 4 or 5 characterized by the above-mentioned.

  (Supplementary note 8) The method for forming a plating film on a wiring board according to supplementary note 1, wherein the wiring groove and / or the wiring connection hole has a high aspect ratio.

Process sectional drawing for demonstrating embodiment of this invention (the 1) Process sectional drawing for demonstrating embodiment of this invention (the 2) Process sectional drawing for demonstrating embodiment of this invention (the 3) Process sectional drawing in order to demonstrate embodiment of this invention (the 4) Process sectional drawing in order to demonstrate embodiment of this invention (the 5) Substrate cross-sectional view for explaining the damascene process Diagram for explaining void generation in wiring

Explanation of symbols

1, 101 Substrate 2, 102 Insulating layer 3, 106 Via hole 4, 104 Laminated film (barrier layer and seed layer)
5 Plating accelerating additive aqueous solution 6 Air bubbles 7 Plating accelerating additive containing film 8, 105 Copper plating film 9, 103 Via

Claims (5)

A first step of forming a wiring groove or / and a wiring connection hole in an insulating film on the substrate;
A second step of forming a barrier film on the insulating film and in the wiring groove or / and the wiring connection hole;
A third step of depositing a plating accelerating additive-containing film containing a plating accelerating additive in the wiring groove or / and the wiring connecting hole in which the barrier film is formed;
Plating a wiring board, characterized by having a fourth step of filling a copper film or a copper alloy film by plating into the wiring groove or / and wiring connection hole where the plating promoting additive-containing film is deposited. Film forming method.   The plating promoting additive is sodium 3-mercapto-1-propanesulfonate, sodium 2-mercaptoethanesulfonate, or bis- (3-sulfopropyl) -disulfide. For forming a plating film on a wiring board.   The third step is a step in which the plating accelerating additive-containing film is selectively deposited on a bottom surface portion of the wiring groove or / and the wiring connection hole in which the barrier film is formed. The method for forming a plating film on a wiring board according to claim 1 or 2.   In the third step, after the second step, the substrate on which the barrier film is formed is immersed in a solution containing the plating accelerating additive in a container, and the container is evacuated in a chamber that can be evacuated. And a fifth step of removing the substrate on which the barrier film is formed from the solution and a sixth step of removing the solvent in the solution adhering to the substrate on which the barrier film is formed. The method for forming a plating film on a wiring board according to any one of claims 1 to 3.   5. The wiring according to claim 4, wherein the third step further includes a seventh step of selectively leaving the solution on the bottom surface by a spin-rinse method after the fifth step. A method for forming a plating film on a substrate.

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