KR100363847B1 - Method of forming a metal wiring in a semiconductor device - Google Patents
Method of forming a metal wiring in a semiconductor device Download PDFInfo
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- KR100363847B1 KR100363847B1 KR1019990023928A KR19990023928A KR100363847B1 KR 100363847 B1 KR100363847 B1 KR 100363847B1 KR 1019990023928 A KR1019990023928 A KR 1019990023928A KR 19990023928 A KR19990023928 A KR 19990023928A KR 100363847 B1 KR100363847 B1 KR 100363847B1
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- copper
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- diffusion barrier
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- 238000000034 method Methods 0.000 title claims abstract description 130
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 36
- 239000002184 metal Substances 0.000 title claims abstract description 36
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 239000010949 copper Substances 0.000 claims abstract description 137
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 130
- 229910052802 copper Inorganic materials 0.000 claims abstract description 130
- 230000004888 barrier function Effects 0.000 claims abstract description 44
- 238000009792 diffusion process Methods 0.000 claims abstract description 44
- 238000009713 electroplating Methods 0.000 claims abstract description 44
- 230000008569 process Effects 0.000 claims abstract description 39
- 230000015572 biosynthetic process Effects 0.000 claims abstract 5
- 239000010410 layer Substances 0.000 claims description 136
- 238000007747 plating Methods 0.000 claims description 35
- 238000004140 cleaning Methods 0.000 claims description 16
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 12
- 239000011229 interlayer Substances 0.000 claims description 12
- 239000001257 hydrogen Substances 0.000 claims description 10
- 229910052739 hydrogen Inorganic materials 0.000 claims description 10
- 238000005240 physical vapour deposition Methods 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- 230000009467 reduction Effects 0.000 claims description 7
- 239000011810 insulating material Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 4
- 239000000654 additive Substances 0.000 claims description 3
- 239000003792 electrolyte Substances 0.000 claims description 3
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
- 238000001035 drying Methods 0.000 claims description 2
- 230000009977 dual effect Effects 0.000 claims description 2
- 239000008151 electrolyte solution Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 238000002156 mixing Methods 0.000 claims description 2
- 238000007517 polishing process Methods 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 238000004544 sputter deposition Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract description 14
- 230000008021 deposition Effects 0.000 abstract description 9
- 238000005137 deposition process Methods 0.000 abstract description 6
- 239000010408 film Substances 0.000 description 8
- 230000000996 additive effect Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- -1 or the like Substances 0.000 description 1
- 125000002524 organometallic group Chemical group 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 전기 도금법을 이용한 구리(Cu) 증착법으로 금속 배선을 형성할 때, 필수 공정인 구리 시드층 증착 공정을 제거할 수 있는 기술이다. 구리 시드층 증착 공정 없이 전기 도금법으로 구리 금속 배선을 형성하기 위하여, 본 발명은 콘택홀 및 트렌치가 형성된 웨이퍼의 표면에 확산 장벽층을 형성한 후, 확산 장벽층에 미세 전류가 흐르도록 전압을 설정한 상태에서 전기 도금법으로 구리층을 얇게 증착하고, 확산 장벽층 상에 얇게 형성된 구리층은 기존의 구리 시드층 역할을 하므로 정상적인 전기 도금 증착 조건의 전압과 전류를 설정하여 콘택홀 및 트렌치를 매립시키는 구리층을 형성한다. 이와 같이 별도의 공정 없이 구리 시드층 역할을 하는 얇은 구리층 및 배선 역할을 하는 구리층을 연속적으로 형성하므로써, 공정 단계의 감소로 생산성을 향상시킬 수 있을 뿐만 아니라, 금속 배선에 대한 신뢰성, 안정성 및 성능을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device, and is a technique capable of removing a copper seed layer deposition process, which is an essential process when forming a metal wiring by a copper (Cu) deposition method using an electroplating method. In order to form a copper metal wiring by electroplating without a copper seed layer deposition process, the present invention forms a diffusion barrier layer on the surface of the wafer on which the contact holes and trenches are formed, and then sets a voltage so that a fine current flows through the diffusion barrier layer. In one state, a thin copper layer is deposited by electroplating, and a thin copper layer formed on a diffusion barrier layer serves as a conventional copper seed layer, thereby filling contact holes and trenches by setting voltage and current under normal electroplating deposition conditions. A copper layer is formed. As a result of the continuous formation of a thin copper layer serving as a copper seed layer and a copper layer serving as a wiring without a separate process, productivity can be improved by reducing process steps, and reliability, stability and It can improve performance.
Description
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 전기 도금법을 이용한 구리(Cu) 증착법으로 금속 배선을 형성할 때, 필수 공정인 구리 시드층 증착 공정을 제거할 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices. In particular, when forming metal wirings by a copper (Cu) deposition method using an electroplating method, a metal wiring of a semiconductor device capable of removing a copper seed layer deposition process, which is an essential process, can be removed. It relates to a forming method.
반도체 산업이 초대규모 집적 회로(Ultra Large Scale Integration; ULSI)로 옮겨 가면서 소자의 지오메트리(geometry)가 서브-하프-마이크로(sub-half-micron) 영역으로 계속 줄어드는 반면, 성능 향상 및 신뢰도 측면에서 회로 밀도(circuit density)는 증가하고 있다. 이러한 요구에 부응하여, 반도체 소자의 금속 배선을 형성함에 있어서 구리 박막은 알루미늄에 비해 녹는점이 높아 전기이동도(electro-migration; EM)에 대한 저항이 커서 반도체 소자의 신뢰성을 향상시킬 수 있고, 비저항이 낮아 신호전달 속도를 증가시킬 수 있어, 집적 회로(integration circuit)에 유용한 배선 재료(interconnection material)로 사용되고 있다.As the semiconductor industry moves to Ultra Large Scale Integration (ULSI), the geometry of the device continues to shrink to the sub-half-micron region, while improving circuitry in terms of performance and reliability. Circuit density is increasing. In response to these demands, the copper thin film has a higher melting point than aluminum in forming metal wirings of the semiconductor device, and thus has high resistance to electro-migration (EM), thereby improving reliability of the semiconductor device and providing a specific resistance. This low rate can increase the signal transfer rate, making it a useful interconnection material for integration circuits.
구리 금속 배선 형성 방법에서, 구리 증착 공정은 고속 소자 및 고집적 소자를 실현하는데 중요한 공정으로, 물리기상증착(Physical Vapor Deposition; PVD)법, 전기 도금(Electroplating)법, 무전해 전기 도금법(Electroless-plating), 유기금속 화학기상증착(MOCVD)법 등 여러 증착 기술이 적용되고 있다. 이러한 구리 증착 기술중 전기 도금법은 안정하고 깨끗한 구리 시드층 증착이 필수적인 공정으로 되어 있다.In the copper metal wiring forming method, the copper deposition process is an important process for realizing high-speed devices and high-density devices, such as physical vapor deposition (PVD), electroplating, and electroless-plating. ) And various deposition techniques such as organometallic chemical vapor deposition (MOCVD). Among these copper deposition techniques, electroplating is a process in which stable and clean copper seed layer deposition is essential.
전기 도금법을 이용한 일반적인 구리 증착 방법은 물리기상증착 장비 및 화학기상증착 장비에서 확산 방지막 및 구리 시드층을 증착한 후에 구리 전기 도금 장비에서 구리 전기 도금을 진행한다. 이 경우, 구리 시드층 증착 후에 진공 파괴과정을 거치고, 구리층 형성을 위한 전기 도금을 진행하기 때문에 구리 시드층에 산화막이 형성되는 문제점을 가지고 있으며, 또한 전기 도금 장비에서 프리-클리닝(pre-cleaning) 공정 후에 구리 전기 도금이 진행되어 공정 단계가 늘어나는 문제점을 가지고 있다. 이러한 문제점들 뿐만 아니라, 전기 도금법을 이용하여 도금되는 구리층은 구리 시드층의 막질 상태에 따라 매우 큰 영향을 받기 때문에 실제 구리 시드층의 정확한 제어가 없는 한 안정한 재현성을 확보하기에는 어려움이 따른다.The general copper deposition method using the electroplating method is to deposit the diffusion barrier film and the copper seed layer in the physical vapor deposition equipment and chemical vapor deposition equipment and then copper electroplating in the copper electroplating equipment. In this case, an oxide film is formed on the copper seed layer because vacuum plating is performed after the copper seed layer deposition, and electroplating is performed to form the copper layer. Also, pre-cleaning is performed in the electroplating equipment. After the electroplating process, the copper electroplating process has a problem of increasing process steps. In addition to these problems, since the copper layer to be plated using the electroplating method is greatly affected by the film quality of the copper seed layer, it is difficult to secure stable reproducibility without accurate control of the copper seed layer.
따라서, 본 발명은 전기 도금법을 이용한 구리 증착법으로 금속 배선을 형성할 때, 필수 공정인 구리 시드층 증착 공정을 제거하여 생산성을 향상시킬 수 있을 뿐만 아니라, 금속 배선에 대한 신뢰성, 안정성 및 성능을 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법을 제공함에 그 목적이 있다.Therefore, the present invention not only improves productivity by removing the copper seed layer deposition process, which is an essential process, when forming metal wirings by copper deposition using an electroplating method, but also improves reliability, stability, and performance of metal wirings. It is an object of the present invention to provide a method for forming a metal wiring of a semiconductor device.
이러한 목적을 달성하기 위한 본 발명의 반도체 소자의 금속 배선 형성 방법은 하지층상에 층간 절연막을 형성한 후, 상기 층간 절연막의 일부분을 식각하여 콘택홀 및 트렌치를 형성하는 단계; 클리닝 공정을 실시한 후, 상기 콘택홀 및 트렌치를 포함한 상기 층간 절연막 표면에 확산 장벽층을 형성하는 단계; 상기 확산 장벽층에 제 1 전압을 인가하여 전류가 흐르게 한 상태에서 제 1 구리 전기 도금 공정으로 상기 확산 장벽층상에 제 1 구리층을 형성하는 단계; 상기 제 1 구리층에 제 2 전압을 인가하여 전류가 흐르게 한 상태에서 제 2 구리 전기 도금 공정으로상기 제 1 구리층상에 제 2 구리층을 형성하는 단계; 및 상기 제 2 구리층을 수소환원 열처리를 하고, 화학적 기계적 연마 공정 및 포스트-클리닝 공정을 실시하여 구리 금속 배선을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, a method of forming a metal wiring of a semiconductor device according to the present invention includes forming a contact hole and a trench by forming an interlayer insulating film on an underlayer, and etching a portion of the interlayer insulating film; After the cleaning process, forming a diffusion barrier layer on a surface of the interlayer insulating layer including the contact hole and the trench; Forming a first copper layer on the diffusion barrier layer by a first copper electroplating process in a state in which a current is applied by applying a first voltage to the diffusion barrier layer; Forming a second copper layer on the first copper layer by a second copper electroplating process in a state in which a current flows by applying a second voltage to the first copper layer; And performing a hydrogen reduction heat treatment on the second copper layer, and performing a chemical mechanical polishing process and a post-cleaning process to form a copper metal wiring.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도.1A to 1D are cross-sectional views of a device for explaining a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11: 하지층 12: 층간 절연막11: base layer 12: interlayer insulating film
13: 콘택홀 14: 트렌치13: contact hole 14: trench
15: 확산 장벽층 16: 구리층15: diffusion barrier layer 16: copper layer
16a: 제 1 구리층 16b: 제 2 구리층16a: first copper layer 16b: second copper layer
160: 구리 금속 배선160: copper metal wiring
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1D are cross-sectional views of devices for describing a method for forming metal wirings in a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 하지층(11)상에 층간 절연막(12)을 형성한 후, 층간 절연막(12)의 일부분을 식각하여 콘택홀(13) 및 트렌치(14)를 형성한다. 클리닝(cleaning) 공정을 실시한 후, 콘택홀(13) 및 트렌치(14)를 포함한 층간 절연막(12) 표면에 확산 장벽층(15)을 형성한다.Referring to FIG. 1A, after forming the interlayer insulating layer 12 on the base layer 11, a portion of the interlayer insulating layer 12 is etched to form the contact hole 13 and the trench 14. After performing the cleaning process, the diffusion barrier layer 15 is formed on the surface of the interlayer insulating film 12 including the contact hole 13 and the trench 14.
상기에서, 하지층(11)은 반도체 기판, 폴리실리콘(poly-Si), 텅스텐(W), 알루미늄(Al), 구리(Cu) 등과 같은 전도성 물질로 형성된 층이거나, 절연 물질로 형성된 층이다. 층간 절연막(12)은 낮은 유전 상수(low k)를 갖는 절연 물질로 형성한다. 콘택홀(13) 및 트렌치(14)는 듀얼 다마신(dual damascene) 방식으로 형성한다. 클리닝 공정은 하지층(11)이 텅스텐(W)이나 알루미늄(Al)과 같은 금속일 경우 고주파 플라즈마(RF plasma)를 이용하고, 하지층(11)이 구리(Cu)일 경우 리액티브 클리닝(reactive cleaning) 방식을 적용하며, 하지층(11)이 절연 물질일 경우 스퍼터링(sputtering) 방식을 적용한다. 확산 장벽층(15)은 이온화(ionized) PVD TiN,CVD TiN, MOCVD TiN, 이온화 PVD Ta, 이온화 PVD TaN, CVD Ta, CVD TaN, CVD WN 중 적어도 어느 하나로 형성한다. 이러한 물질로 형성되는 확산 장벽층(15)은 구리(Cu)에 비하여 저항이 높으나 어느 정도의 전도성을 갖는다. 확산 장벽층(15)의 증착 두께는 기존의 구리 전기 도금법으로 구리 금속 배선을 형성할 때 적용되는 확산 장벽층의 두께와 구리 시드층(Cu seed layer)의 두께를 합한 두께보다 두껍지 않게 형성한다. 즉, 기존의 확산 장벽층이 약 500Å의 두께로 형성되고, 구리 시드층이 약 1500Å의 두께로 형성될 경우, 본 발명의 확산 장벽층(15)은 최소의 저항 감소 및 기존의 공정보다 안정성을 높이기 위해 500 내지 2000Å의 두께로 형성한다.In the above, the base layer 11 is a layer formed of a conductive material such as a semiconductor substrate, polysilicon (poly-Si), tungsten (W), aluminum (Al), copper (Cu), or the like, or a layer formed of an insulating material. The interlayer insulating film 12 is formed of an insulating material having a low dielectric constant (low k). The contact hole 13 and the trench 14 are formed by a dual damascene method. The cleaning process uses RF plasma when the base layer 11 is a metal such as tungsten (W) or aluminum (Al), and reactive cleaning when the base layer 11 is copper (Cu). cleaning) method is applied, and when the base layer 11 is an insulating material, a sputtering method is applied. The diffusion barrier layer 15 is formed of at least one of ionized PVD TiN, CVD TiN, MOCVD TiN, ionized PVD Ta, ionized PVD TaN, CVD Ta, CVD TaN, and CVD WN. The diffusion barrier layer 15 formed of such a material has a higher resistance than copper (Cu) but has some degree of conductivity. The deposition thickness of the diffusion barrier layer 15 is not thicker than the sum of the thickness of the diffusion barrier layer and the thickness of the copper seed layer applied when the copper metal wiring is formed by conventional copper electroplating. That is, when the existing diffusion barrier layer is formed to a thickness of about 500 GPa, and the copper seed layer is formed to a thickness of about 1500 GPa, the diffusion barrier layer 15 of the present invention is reduced in the minimum resistance and more stable than the conventional process In order to increase the thickness of 500 to 2000Å.
도 1b를 참조하면, 확산 장벽층(15)을 형성하는 증착 장비로 부터 웨이퍼를 전기 도금 장비로 이송시킨 후에, 전해액을 챔버로 유입시켜 프리-플레이팅(pre-plating)을 포함하는 표면 클리닝 단계와 구리 전기 도금 단계로 진행하는 제 1 구리 전기 도금 공정을 실시하여 기존의 구리 시드층 역할을 하는 얇은 두께의 제 1 구리층(16a)을 형성한다.Referring to FIG. 1B, after the wafer is transferred from the deposition equipment forming the diffusion barrier layer 15 to the electroplating equipment, the surface cleaning step includes pre-plating by introducing electrolyte into the chamber. And a first copper electroplating process proceeding to a copper electroplating step to form a thin first copper layer 16a serving as a conventional copper seed layer.
상기에서, 전해액은 1 내지 100g/liter의 CuSO4, 1 내지 200g/liter의 H2SO4, 1 내지 500ppm의 HCl등과 1 내지 20ml/liter의 첨가제(additive)등이 포함되며, 전기 도금 온도는 10 내지 40℃로 한다. 프리-플레이팅을 포함하는 표면 클리닝 단계는 전해액이 챔버로 유입되어 웨이퍼에 닿는 시점으로 부터 2분 이하의 동안 휴지 시간(dwell time)을 갖는 단계이다. 구리 전기 도금 단계는 웨이퍼를 회전시키면서 확산 장벽층(15)에 제 1 전압을 인가하여 미세한 제 1 전류를 흘려 제 1 구리층(16a)을 얇게 형성한다. 이때, 웨이퍼의 회전속도는 5 내지 100rpm으로 하고, 확산 장벽층(15)에 흘리는 전력 공급 전류(power supply current)인 제 1 전류는 0.1mA 내지 20A로 하며, 이러한 제 1 전류를 확산 장벽층(15)에 흘리기 위해 인가되는 제 1 전압은 확산 장벽층(15)을 형성하는 재료에 따라 적절하게 설정한다. 이러한 조건으로 형성된 제 1 구리층(16a)은 기존의 구리 시드층 역할을 수행할 수 있을 정도의 두께를 갖는다.In the above, the electrolyte solution contains 1 to 100g / liter CuSO 4 , 1 to 200g / liter H 2 SO 4 , 1 to 500ppm HCl and the like and 1 to 20ml / liter additive (additive), the electroplating temperature is Let it be 10-40 degreeC. The surface cleaning step including pre-plating is a step having a dwell time for not more than 2 minutes from the time when the electrolyte enters the chamber and reaches the wafer. In the copper electroplating step, a first voltage is applied to the diffusion barrier layer 15 while the wafer is rotated to flow a fine first current to form the first copper layer 16a thinly. At this time, the rotational speed of the wafer is 5 to 100rpm, the first current which is the power supply current flowing through the diffusion barrier layer 15 is 0.1mA to 20A, and the first current is the diffusion barrier layer ( The first voltage applied to flow to 15) is appropriately set according to the material of which the diffusion barrier layer 15 is formed. The first copper layer 16a formed under these conditions has a thickness sufficient to serve as a conventional copper seed layer.
제 1 구리층(16a)을 형성하는 제 1 구리 전기 도금 공정에서 확산 장벽층(15)에 흘리는 전류의 공급 방식은 DC 플레이팅(DC plating)법, 2-스텝 DC 플레이팅(2-step DC plating)법, 멀티-스텝 DC 플레이팅(multi-step DC plating)법, 유니폴라 펄스 플레이팅(unipolar pulse plating)법, 바이폴라 리버스 플레이팅(bipolar reverse plating)법 등이 가능하다.In the first copper electroplating process of forming the first copper layer 16a, the current is supplied to the diffusion barrier layer 15 by a DC plating method or a 2-step DC plating method. plating method, multi-step DC plating method, unipolar pulse plating method, bipolar reverse plating method and the like are possible.
예를 들어, 멀티-스텝 DC 플레이팅법을 적용할 경우, 웨이퍼를 계속 회전시킨 상태에서 1 내지 100ms 동안 0.1mA 내지 20A의 제 1 전류를 확산 장벽층(15)에 흘리다가 전류 공급을 중단하고, 다시 전류를 공급 하는 과정을 수차례 반복하여 제 1 구리층(16a)을 형성한다.For example, when the multi-step DC plating method is applied, the first current of 0.1 mA to 20 A flows into the diffusion barrier layer 15 for 1 to 100 ms while the wafer is continuously rotated, and then the current supply is stopped. The process of supplying the current again is repeated several times to form the first copper layer 16a.
도 1c를 참조하면, 제 1 구리층(16a) 형성 공정으로 부터 연속적으로 제 2 구리 전기 도금 공정을 실시하여 콘택홀(13) 및 트렌치(14)를 완전히 매립시키는 두꺼운 제 2 구리층(16b)을 제 1 구리층(16a)상에 형성한다. 이때, 확산 장벽층(15)에 미세한 제 1 전류가 흐르도록 인가된 제 1 전압을 조정하여 정상적인 전기 도금 증착 조건인 제 2 전압을 제 1 구리층(16a)에 인가하여 제 1 구리층(16a)에 0.1mA 내지 20A의 제 2 전류가 흐르도록 한다. 제 1 구리층(16a)에 이러한 제 2 전류가 흐르도록 하기 위해 제 2 전압을 0.01mV 내지 10V로 설정한다.Referring to FIG. 1C, a thick second copper layer 16b which completely fills the contact hole 13 and the trench 14 by performing a second copper electroplating process continuously from the first copper layer 16a forming process. Is formed on the first copper layer 16a. At this time, by adjusting the first voltage applied to the diffusion barrier layer 15 to flow a fine first current, a second voltage, which is a normal electroplating deposition condition, is applied to the first copper layer 16a, thereby providing a first copper layer 16a. ), A second current of 0.1 mA to 20 A flows. The second voltage is set to 0.01 mV to 10 V to allow this second current to flow through the first copper layer 16a.
이와 같이 전압을 조정하는 것은 확산 장벽층(15)이 제 1 구리층(16a)을 이루는 구리와 비교하여 비교적 저항이 높은 물질로 형성되기 때문이다. 즉, 제 1 구리층(16a)에 인가하는 제 2 전압이 0.01mV 내지 10V일 경우 확산 장벽층(15)에 인가하는 제 1 전압은 제 2 전압보다 높게 설정하여야 0.1mA 내지 20A의 제 1 전류를 확산 장벽층(15)에 흐르게 할 수 있다.The voltage is adjusted in this way because the diffusion barrier layer 15 is formed of a material having a relatively high resistance compared to the copper forming the first copper layer 16a. That is, when the second voltage applied to the first copper layer 16a is 0.01 mV to 10 V, the first voltage applied to the diffusion barrier layer 15 should be set higher than the second voltage to be the first current of 0.1 mA to 20 A. Can flow into the diffusion barrier layer 15.
제 2 구리층(16b)을 형성하는 제 2 구리 전기 도금 공정에서 제 1 구리층(16a)에 흘리는 전류의 공급 방식은 DC 플레이팅(DC plating)법, 2-스텝 DC 플레이팅(2-step DC plating)법, 멀티-스텝 DC 플레이팅(multi-step DC plating)법, 유니폴라 펄스 플레이팅(unipolar pulse plating)법, 펄스드 리버스 플레이팅(pulsed reverse plating)법 등이 가능하다.In the second copper electroplating process of forming the second copper layer 16b, a current supplying method flowing through the first copper layer 16a may be DC plating or 2-step DC plating. DC plating, multi-step DC plating, unipolar pulse plating, pulsed reverse plating and the like are possible.
예를 들어, 멀티-스텝 DC 플레이팅법을 적용할 경우, 웨이퍼를 계속 회전시킨 상태에서 1 내지 100ms 동안 0.1mA 내지 20A의 제 2 전류를 제 1 구리층(16a)에 흘리다가 전류 공급을 중단하고, 다시 전류를 공급 하는 과정을 수차례 반복하여 제 2 구리층(16b)을 형성한다. 또한, 펄스드 리버스 플레이팅법을 적용할 경우, 웨이퍼를 계속 회전시킨 상태에서, 0.1mA 내지 20A의 순방향 전류(forward current)를 제 2 전류로 1 내지 200ms 동안 제 1 구리층(16a)에 흘리고, 1 내지 30ms 동안 오프 타입(off time)을 가진 후 0.1mA 내지 10A의 역방향 전류(reverse current)를 제 2 전류로 5 내지 50ms 동안 제 1 구리층(16a)에 흘리고, 1 내지 30ms 동안 오프 타입(off time)을 가진다.For example, when the multi-step DC plating method is applied, the second current of 0.1 mA to 20 A flows in the first copper layer 16a for 1 to 100 ms while the wafer is continuously rotated, and then the current supply is stopped. Then, the process of supplying the current again is repeated several times to form the second copper layer 16b. In addition, when the pulsed reverse plating method is applied, while the wafer is continuously rotated, a forward current of 0.1 mA to 20 A flows into the first copper layer 16a as a second current for 1 to 200 ms. After having an off time for 1 to 30 ms, a reverse current of 0.1 mA to 10 A flows into the first copper layer 16a for 5 to 50 ms as a second current, and for off type for 1 to 30 ms. off time).
도 1b 및 도 1c에서 전술한 확산 장벽층(15) 및 제 1 구리층(16a)에 공급되는 전류는 10 내지 50mA/cm2의 평균 웨이퍼 전류 밀도(wafer current density)가 유지되도록 한다.The current supplied to the diffusion barrier layer 15 and the first copper layer 16a described above in FIGS. 1B and 1C allows the average wafer current density of 10 to 50 mA / cm 2 to be maintained.
도 1d를 참조하면, 제 1 구리층(16a)과 제 2 구리층(16b)으로 된 구리층(16)을 순수(DI water)를 이용하여 웨이퍼의 회전 속도를 100 내지 2500rpm의 조건에서 스핀 및 린스 드라이(spin and rinse dry) 공정을 진행한다. 이후, 수소환원 분위기에서 상온 내지 350℃의 온도 범위로 30분 내지 3시간 열처리하여 그레인 형태 (grain morphology)를 바꾸는 과정을 실시한다. 이때의 수소환원 분위기는 H2가스만을 적용하는 경우와, H2가스에 Ar가스를 1 내지 95% 혼합한 수소혼합가스, H2가스에 N2가스를 1 내지 95% 혼합한 수소혼합가스를 사용한다. 열처리후 구리층(16)을 화학적 기계적 연마(CMP)법으로 연마하는 공정 및 포스트-클리닝(post-cleaning) 공정을 실시하여 구리 금속 배선(160)을 형성한다. 구리 매립 공정후 열처리 공정은 시간 지연 없이(no time delay), 인-시튜(in-situ) 공정으로 진행되도록 한다.Referring to FIG. 1D, the copper layer 16 including the first copper layer 16a and the second copper layer 16b is spin-dried at 100 to 2500 rpm using a pure water (DI water). Spin and rinse dry process. Thereafter, heat treatment is performed for 30 minutes to 3 hours in a temperature range of room temperature to 350 ° C. in a hydrogen reduction atmosphere to change the grain morphology. Hydrogen reducing atmosphere at this time when applying only the H 2 gas and an Ar gas is from 1 to 95% mixing the hydrogen mixed gas, N 2 gas from 1 to 95% of a mixture of the hydrogen mixed gas to the H 2 gas to H 2 gas use. After the heat treatment, the copper layer 16 is polished by a chemical mechanical polishing (CMP) method and a post-cleaning process is performed to form the copper metal wiring 160. After the copper buried process, the heat treatment process is performed in an in-situ process, with no time delay.
상기한 본 발명은 확산 장벽층(15)을 형성한 후, 확산 장벽층(15)에 미세한 제 1 전류를 흘리면서 기존의 구리 시드층 역할을 하는 제 1 구리층(16a)을 형성하고, 정상적인 전기 도금 증착 조건인 인가 전압과 제 2 전류를 설정하되, 시간 지연 없이 연속적인 전기 도금법으로 콘택홀(13) 및 트렌치(14)를 매립하는 제 2 구리층(16b)을 형성한다. 여기서, 제 1 구리층(16a) 형성 공정과 제 2 구리층(16b) 형성 공정 사이에 인가 전압 조건을 변화시키는 이유는 TiN, Ta, TaN, WN 등과 같은 물질로 형성되는 확산 장벽층(15)이 구리로 형성되는 제 1 구리층(16a)보다 저항 값이 훨씬 높기 때문에 이러한 확산 장벽층(15)에 제 1 전류를 흘리기 위해서는 인가 전압을 높게 해야 하고, 이후 제 1 구리층(16a)이 형성된 후에는 제 1 구리층(16a)이 구리 시드층 역할을 하기 때문에 높게 설정된 인가 전압을 정상적인 전기 도금 증착 조건인 인가 전압으로 조정한다.After the diffusion barrier layer 15 is formed, the present invention forms a first copper layer 16a that serves as a conventional copper seed layer while flowing a fine first current through the diffusion barrier layer 15, and the normal electrical While setting the applied voltage and the second current, which are the plating deposition conditions, the second copper layer 16b filling the contact hole 13 and the trench 14 by a continuous electroplating method without time delay is formed. Here, the reason for changing the applied voltage condition between the first copper layer 16a forming process and the second copper layer 16b forming process is that of the diffusion barrier layer 15 formed of a material such as TiN, Ta, TaN, WN, or the like. Since the resistance value is much higher than that of the first copper layer 16a formed of copper, in order to flow the first current through the diffusion barrier layer 15, the applied voltage must be high, and then the first copper layer 16a is formed. After that, since the first copper layer 16a serves as a copper seed layer, the applied voltage set high is adjusted to the applied voltage which is a normal electroplating deposition condition.
상술한 바와 같이, 본 발명은 확산 방지막 형성 후에 구리 시드층 증착 공정이 필요 없고, 기존에 전기 도금 전에 실시하는 프리-클리닝 공정이 필요 없어 공정 단계의 감소로 생산성을 향상시킬 수 있다. 또한, 전기 도금시 구리 시드층 역할을 하는 제 1 구리층이 별도의 공정 없이 자발적으로 형성되므로 깨끗하고 안정한 구리 시드층 역할을 하는 제 1 구리층을 얻을 수 있어 전기 도금법의 재현성이 향상되어 콘택홀 및 트렌치를 매립시키는 제 2 구리층을 보이드(void) 및 갈라진 틈(seam) 없이 안정하게 형성할 수 있다.As described above, the present invention does not require a copper seed layer deposition process after forming the diffusion barrier layer, and does not require a pre-cleaning process performed before electroplating, thereby improving productivity by reducing process steps. In addition, since the first copper layer serving as the copper seed layer spontaneously formed during electroplating without a separate process, a first copper layer serving as a clean and stable copper seed layer can be obtained, and thus the reproducibility of the electroplating method is improved and the contact hole is improved. And a second copper layer filling the trench can be stably formed without voids and cracks.
Claims (26)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990023928A KR100363847B1 (en) | 1999-06-24 | 1999-06-24 | Method of forming a metal wiring in a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990023928A KR100363847B1 (en) | 1999-06-24 | 1999-06-24 | Method of forming a metal wiring in a semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010003575A KR20010003575A (en) | 2001-01-15 |
| KR100363847B1 true KR100363847B1 (en) | 2002-12-06 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990023928A KR100363847B1 (en) | 1999-06-24 | 1999-06-24 | Method of forming a metal wiring in a semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100363847B1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100425999B1 (en) * | 2001-12-27 | 2004-04-06 | 동부전자 주식회사 | via hole rinsing method of semiconductor device |
| KR100456259B1 (en) * | 2002-07-15 | 2004-11-09 | 주식회사 하이닉스반도체 | Method of forming a copper wiring in a semiconductor device |
| KR100988783B1 (en) | 2008-07-29 | 2010-10-20 | 주식회사 동부하이텍 | Semiconductor device and method for manufacturing the device |
| KR101005740B1 (en) | 2003-07-18 | 2011-01-06 | 매그나칩 반도체 유한회사 | Method of forming copper wiring in semiconductor device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100467495B1 (en) * | 2002-06-18 | 2005-01-24 | 동부전자 주식회사 | Method for forming metal line of semiconductor device |
| KR20150028701A (en) | 2013-09-05 | 2015-03-16 | (주) 씨쓰리 | Heat exchanger apparatus and method of producing the same |
-
1999
- 1999-06-24 KR KR1019990023928A patent/KR100363847B1/en not_active IP Right Cessation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100425999B1 (en) * | 2001-12-27 | 2004-04-06 | 동부전자 주식회사 | via hole rinsing method of semiconductor device |
| KR100456259B1 (en) * | 2002-07-15 | 2004-11-09 | 주식회사 하이닉스반도체 | Method of forming a copper wiring in a semiconductor device |
| KR101005740B1 (en) | 2003-07-18 | 2011-01-06 | 매그나칩 반도체 유한회사 | Method of forming copper wiring in semiconductor device |
| KR100988783B1 (en) | 2008-07-29 | 2010-10-20 | 주식회사 동부하이텍 | Semiconductor device and method for manufacturing the device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010003575A (en) | 2001-01-15 |
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