KR20060070767A - Metal wiring formation method of semiconductor device - Google Patents

Abstract

The present invention provides a method of forming an insulating film pattern having a double damascene structure including a via hole, a metal wiring trench, and an etch stop layer on a semiconductor substrate including an underlying metal layer, and forming a diffusion barrier layer on a surface of the insulating film pattern. Etching the diffusion barrier layer to form a spacer in sidewalls of the via hole and the metal interconnect trench, while removing the exposed barrier layer under the via hole not covered by the spacer, etching the lower portion of the via hole. Exposing the underlying metal layer by over-etching a stop layer, removing an oxide film formed on the surface of the exposed underlying metal layer, and forming a metal wiring using the surface of the removed underlying metal layer as a seed layer. It provides a method for forming metal wiring of a semiconductor device comprising. Thereby, it is possible to form the metal wiring of the semiconductor device without depositing a separate seed layer for forming the metal plating layer and without forming a void inside the via.

Transient Etching, Etch Stopping Layer, Base Metal Layer, Seed Layer

Description

METHOD FOR FORMING METAL LINE OF SEMICONDUCTOR DEVICE

1A to 1F are cross-sectional views showing a metal wiring formation method of a semiconductor device according to the present invention.

<Description of the symbols for the main parts of the drawings>

100, 130, 135: insulation layer

100a: base metal layer 105, 115: etch stop layer

110: via hole 120: metal wiring trench

125: hard mask 140: diffusion barrier layer

150: spacer 160: metal oxide film

170: metal plating layer 180: etch stop layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming metal wirings in semiconductor devices in which vias and trenches of an insulating film pattern can be completely embedded in a metal layer without internal voids.                         

In forming a metal wiring in a semiconductor device, various metal deposition methods such as an electrolytic plating method, an electroless plating method, a PVD method, and a CVD method have been conventionally applied.

In particular, the electroless plating method is a method of forming a film (for example, a copper film) by spontaneous oxidation / reduction reaction of materials existing in the electroless plating solution without applying electricity from the outside. In this case, the electroless plating solution may contain additives for solution stabilization or pH control, or may contain a reducing agent for suppressing the liquid phase reaction. In the case of electroless plating, the surface must be activated because the oxidation / reduction reaction occurs spontaneously on the surface to be plated, and the surface must be activated. For this activation, the surface is immersed in an activation bath and activated such as Pd. To form particles.

However, Pd particles act as impurities in the copper film, thereby increasing the specific resistance of the copper film. In order to solve this problem, a method of depositing Al as a protective film has been proposed, which causes the Al deposited on the surface to dissolve due to the high pH of the electroless plating solution so that the surface of the copper film is exposed so that no additional surface activation is required. to be.

In the case of the metal wire filling process using the conventional electroless plating method as described above, there is a problem in that an abnormal metal film is grown on the upper surface of the insulating film pattern to be activated. Therefore, there is a limit in depositing a metal wiring using only the electroless plating method as in the prior art.

In order to overcome this limitation, a method of depositing a copper diffusion barrier layer and a copper seed layer by PVD method, forming a copper film by electroplating method, filling a via or trench, and finishing a multi-layer metal wiring process by CMP process is proposed. have. However, because the PVD copper seed layer is poor in layer coverage, overhangs are formed in narrow vias and trenches having high step ratios, or deposition discontinuities occur. This causes a problem in that voids are formed inside the vias in subsequent copper electroplating processes. As an alternative to this, researches on a technique of forming a copper seed layer by CVD have been conducted, but the situation has not been suggested due to poor adhesiveness, process stability, and high cost.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device in which vias and trenches of an insulating film pattern can be completely filled with a metal layer without internal voids.

In order to achieve the above object, the metal wiring forming method of the semiconductor device according to the present invention, forming an insulating film pattern of a double damascene structure including a via hole, a metal wiring trench and an etch stop layer on a semiconductor substrate including a base metal layer. Doing; Forming a diffusion barrier layer on a surface of the insulating film pattern; Etching the diffusion barrier layer to form a spacer in sidewalls of the via hole and the metal interconnect trench, while removing the exposed diffusion barrier layer under the via hole not covered by the spacer; Overetching the etch stop layer under the via hole to expose the underlying metal layer; Removing an oxide film formed on a surface of the exposed underlying metal layer; And forming a metal wiring using the surface of the base metal layer from which the oxide film is removed as a seed layer.

According to the present invention, the diffusion barrier layer is etched to form a spacer while the diffusion barrier layer under the spacer hole is not etched together to expose the etch stop layer, and then the etch stop layer is over-etched to partially etch the underlying metal layer. After exposing the oxide film, the oxide film is removed on the surface thereof, so that the underlying metal layer can be used as the seed layer. As a result, even if the electroless plating method is performed without a separate seed layer deposition process, the metal plating layer may be selectively bottom-up grown. Therefore, the present invention can solve the problems of the prior art of electroplating after forming the seed layer by the above-described PVD method, it is possible to improve the process stability.

EMBODIMENT OF THE INVENTION Hereinafter, preferred embodiment of this invention is described in detail with reference to an accompanying drawing. 1A to 1F are cross-sectional views showing a metal wiring formation method of a semiconductor device according to the present invention.

First, referring to FIG. 1A, an insulating layer 100 including a base metal layer 100a is laminated on a semiconductor substrate (not shown), and an etching stop layer 105, a via level insulating layer 130, The trench level etch stop layer 115, the trench level insulating layer 135, and the hard mask 125 are stacked. A double damascene insulating layer pattern including the via hole 110 and the trench 120 is formed through a process such as via first or trench first, and then a diffusion barrier is formed on the surface of the pattern. Form layer 140. In the case of the diffusion barrier layer 140, it is preferable to form by depositing 100 kV or more by the PVD method, and to deposit 10 kPa or more on the via pattern sidewalls. The diffusion barrier layer 140 may be a metal diffusion barrier layer such as a Ti series, a W series, or a Ta series, and may be an oxide film or a nitride film based thereon.

Next, referring to FIG. 1B, a spacer 150 is formed on the diffusion barrier layer 140 by, for example, performing a plasma etching process. In this case, the diffusion barrier layer 140 formed on the upper surface of the insulating layer pattern and the diffusion barrier layer 140 existing in the portion without the spacer 150 under the via hole 110 are removed together during plasma etching. As a result, the etch stop layer 180 is exposed. In addition, the plasma etching step may be performed by a method known in the art, such as, for example, a plasma etching step using Ar.

Referring to FIG. 1C, the exposed diffusion barrier layer 180 is excessively etched to expose a portion of the underlying metal layer 100a. Due to the excessive etching, the metal oxide film 160 (for example, Cu _x O _1-x ) formed by contact with the outside air is formed while the surface of the underlying metal layer 100a is exposed.

Referring to FIG. 1D, the metal oxide film 150 is removed. As the oxide film removal method, for example, in the case of the copper oxide film 160, a dual frequency etching method or a reactive cleaning method may be used.

Next, referring to FIG. 1E, an electroplating method such as an electroless plating method using a surface of the over-etched underlying metal layer 100a as a seed layer is performed. 170 represents the metal plating layer 170 formed by the implementation of the electroplating method. The electroless plating method is preferably performed immediately after removing the metal oxide film 160 without time delay. In electroless plating, the electroless plating solution may include, for example, a material containing a copper cation such as CuSO ₄ or a reducing agent such as HCHO and additives for pH control and solution stability. In this case, the electroless plating solution is such that the concentration of Cu ²⁺ ions is 10 ⁻⁴ to 10M, the pH of the plating solution is 10 to 13, and the temperature of the plating solution is preferably maintained at 20 to 100 ° C.

Referring to FIG. 1F, surface treatment is carried out, for example, via hydrogen annealing, followed by subsequent landfill processes. As the subsequent electroplating process is performed, as shown in FIG. 1F, when the metal buried layer 170 fills the via hole 110 and the trench 120, electroplating is stopped. Thereafter, a CMP process is performed to perform a finishing process such as removing the over-plated layer portion to form a metal wiring.

According to the metallization forming method of the present invention, the metallization layer can be formed by performing an electroless plating method without a separate seed layer deposition process, and the insulating film without forming voids in the vias during the metallization formation process The interior of the pattern can be embedded.

Claims (6)

Forming an insulating film pattern having a dual damascene structure including a via hole, a metal wiring trench, and an etch stop layer on the semiconductor substrate including the underlying metal layer; Forming a diffusion barrier layer on a surface of the insulating film pattern; Etching the diffusion barrier layer to form a spacer in sidewalls of the via hole and the metal interconnect trench, while removing the exposed diffusion barrier layer under the via hole not covered by the spacer; Over-etching the etch stop layer below the via hole to expose the underlying metal layer; Removing an oxide film formed on a surface of the exposed underlying metal layer; And And forming a metal wiring using the surface of the base metal layer from which the oxide film has been removed as a seed layer. The method of claim 1, After forming the metal wirings, performing an annealing process in a hydrogen, helium or argon atmosphere. The method of claim 1, The diffusion barrier layer is formed by one of the PVD method, the CVD method, and the ALD method. The method of claim 1, And forming the spacers by a plasma etching process using argon. The method of claim 1, And the oxide film is removed by a dual frequency etching method or a reactive cleaning method. The method of claim 1, Removing the oxide film and forming the metal wirings are performed continuously without time delay.

Images