JP3697827B2 - Flat panel type sensor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is used for, for example, a non-destructive inspection apparatus such as a food or a printed circuit board, a two-dimensional X-ray sensor array used for a medical X-ray imaging apparatus or the like, or a reading apparatus (image scanner) for documents, images, etc. The present invention relates to a flat panel type sensor in which data lines and gate lines are arranged in a matrix on a single substrate, such as a three-dimensional photosensor array.
[0002]
[Prior art]
In response to the recent multimedia boom and digital orientation, filmlessness is progressing in the field of image capturing. The emergence of digital cameras and digital video cameras in the field of consumer equipment, and the rise of research on flat panel X-ray sensors in the medical field are its manifestations. In the field of consumer equipment, a key device having this tendency is also important for compactness, so that CCD surface sensors are now widely used.
[0003]
On the other hand, in the case of X-rays, different from light, it cannot be reduced by a lens system, and a method of directly converting X-rays into an electrical signal with a flat panel of the chest size from the viewpoint of emphasizing sensitivity has become the mainstream of research.
[0004]
This method is further classified into indirect conversion (in this case, X-rays are converted into light by the phosphor layer and the intensity distribution is converted into electric signals by the two-dimensional photosensor array) and direct conversion. Also, the TFT matrix elements are arranged in a planar shape for reading out stored charges from each storage capacitor in time series.
[0005]
A conventional configuration example of the TFT matrix element is shown in FIG.
In FIG. 1, TFT elements D11,... D77,... Arranged one by one for each pixel have a structure having three terminals of a drain, a gate and a source. They are connected to the same data line S. On the other hand, the gate terminals Dg on the row array are connected to the same gate line G. A gate signal for selecting a pixel array for one row is sequentially sent from the gate control circuit 3 to the corresponding gate line G. For example, the gate signal is sequentially sent to the corresponding gate line G from the selection of the top row (first row) to the selection of the bottom row (seventh row). Each data line S is connected to a charge sensitive amplifier A ·· A, which simultaneously collects accumulated charge signals of each pixel for one row. These are time-division processed in the signal processing circuit 2 and transferred and accumulated as accumulated charge data.
[0006]
In the panel structure shown in FIG. 1, the data line S is connected to a pixel group for one column extending over the entire panel, and the gate line G is also connected to a pixel group for one row extending over the entire panel. Yes.
[0007]
[Problems to be solved by the invention]
By the way, in the TFT matrix element shown in FIG. For example, in the following document (1), the amplifier noise proportional to the data line capacitance (= gate-drain capacitance (Cgd) × Nc (number of rows)) is the main factor of noise that appears in the integrated signal of accumulated charge. Are listed.
[0008]
Literature (1) Jpn.J.Appl.Phys.Vol.32 (1993) pp.198-204 Fujieda et.al
High Sensitivity Readout of 2D a-Si Image Sensors
Amplifier noise due to such data line capacitance increases as the number of pixels on the panel increases, so when building a large flat panel sensor of the chest size, reduce the amplifier noise. Is a critical point.
[0009]
In addition, in this type of TFT matrix element, the larger the number of TFT elements connected to the gate line, the greater the delay and waveform distortion until the gate signal reaches each TFT element, and the quality of the accumulated charge signal is improved. There is also the problem of getting worse.
[0010]
As one of those improvement measures, Japanese Patent Application Laid-Open No. 7-274068 discloses a structure in which the entire panel is divided into four parts, and the four divided panels are fitted with high precision. By mounting a gate control circuit and a signal processing circuit (including a charge sensitive amplifier group) on the non-side, the data line capacity of each divided panel is halved to reduce noise, and each divided panel has a TFT. A technique for reducing the delay of the gate signal and waveform distortion by reducing the number of elements by half has been proposed.
[0011]
However, according to the proposed technique, a physically divided panel is manufactured, and there is a disadvantage that the manufacturing process is increased by the number of divided parts. In addition, the problem of the machining accuracy of the mating part and the influence (artifact) caused by subtle expansion and contraction between each divided panel after mating and mounting are the high image quality required for this type of flat panel sensor. In particular, in the case of medical images, considering that strict image quality is required, it can be a big problem.
[0012]
The present invention has been made in view of such circumstances, and an object thereof is to provide a high-performance flat panel sensor in which signal readout noise, delay of a gate signal to a pixel TFT element, and the like are reduced. .
[0013]
[Means for Solving the Problems]
In order to achieve the above object, according to a first invention (corresponding to the invention of claim 1), a plurality of sensors are arranged in a matrix on an insulating substrate so as to form a two-dimensional pixel arrangement, and the sensors are arranged. A data line and a gate line for reading out each pixel signal of the sensor are arranged in a matrix on the substrate, and a charge sensitive amplifier and a gate control circuit are connected to the data line and the gate line, respectively. In the panel-type sensor, as illustrated in FIG. 2, the data line arranged for each pixel row (or column) is divided into two on the panel 1 (divided into Sa1 ·· Sa7 and Sb1 ·· Sb7). Correspondingly, charge sensitive amplifiers Aa1... Aa7 and Ab1... Ab7 are arranged on both sides of the panel 1, and the data lines The split boundary is uneven, and by adopting such a structure, the number of pixel rows (or the number of columns) handled by one data line is the conventional (structure of FIG. 1). On the other hand, the data line capacity of each data line is halved.
[0014]
The second invention (corresponding to the invention of claim 2) is a flat panel sensor in which data lines and gate lines are arranged in a matrix, as shown in FIG. Each gate line is divided into two on the panel 1 (divided into Ga1 ·· Ga7 and Gb1 ·· Gb7), and the gate control circuits 3a and 3b are arranged on both sides of the panel 1 correspondingly. In addition, the dividing boundary of the gate line is uneven, and by adopting such a structure, the distance from the gate control circuit to the farthest TFT element is conventional (FIG. 1). The delay until the gate signal sent from the gate control circuit reaches the pixel TFT element and the waveform distortion are reduced.
[0015]
The third invention (corresponding to the invention of claim 3) is a combination of the technical ideas of the two inventions described above, and as shown in FIG. 9, data arranged for each column or row of pixels. The line and the gate line arranged for each row or column of pixels are divided into two on the panel, and the charge sensitive amplifiers Aa1,... Aa7 and Ab1,. The gate control circuits 3a and 3b are arranged on both sides of the panel 1 so as to be orthogonal to the arrangement of the amplifiers, and the division boundaries of the data lines and the gate lines are uneven. Characterized.
[0016]
Here, in the flat panel sensor of the present invention, when the two-dimensional pixel array is an odd number column / row, as shown in FIG. 3, the division boundaries of the data line / gate line are as shown in FIG. If the concave / convex shape is provided, the pixel arrangement on both sides of the division boundary is almost symmetrical, and the accuracy of calibration at the time of data processing can be improved.
[0017]
Further, in the flat panel type sensor of the present invention, when the data line is divided, as shown in FIG. 7, two sets of charge sensitive amplifier groups Aa1... Aa7 and Ab1. The pixel signal from Ab7 is configured to be processed by a common signal processing circuit, and the connection of one amplifier group Aa1,... Aa7 to the signal processing circuit and the signal processing of the other amplifier group Ab1,. A configuration in which means 4 for selectively switching the connection to the circuit is provided may be employed.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 2 is a diagram showing the structure of the embodiment of the first invention.
The flat panel sensor 1 shown in FIG. 2 is an indirect conversion type X sensor in which photosensors (not shown) are arranged in a matrix so as to form a two-dimensional pixel array, and each pixel P11.・ P17, ..., P71 ... P77, ... corresponding to TFT elements (FET) D11 ... D17, ..., D71 ... D77, ... arranged in a matrix Has been.
[0019]
.. Of the TFT elements D11... D77,... Are connected to the same gate line G1... G6 or G7. Each of the gate lines G1... G7 is connected to a gate control circuit 3 disposed on the side of the panel 1.
[0020]
The gate control circuit 3 is configured to sequentially send a gate signal for selecting a pixel array for one row to the corresponding gate line G1,... G6 or G7.
On the other hand, each drain terminal Dd of each TFT element D11... D77 is connected to a data line, but this embodiment is characterized in that the data line is divided on the panel.
[0021]
That is, in this embodiment, as shown in FIG. 2, the data line group is divided between the fourth row and the fifth row of the pixel array, and the TFT elements located in the first row to the fourth row are arranged. For D11... D47, each drain terminal Dd is connected to the same data line Sa1... Sa6 or Sa7 for each row arrangement, and TFT elements located in the fifth to seventh rows. For D51... D77, each drain terminal Dd is connected to the same data line Sb1... Sb6 or Sb7 for each row.
[0022]
The data lines Sa1... Sa7 connected to the TFT elements D11... D47 located in the first to fourth rows among the data lines divided as described above are connected to the upper side of the panel 1 in FIG. The data lines Sb1... Sb7 connected to the TFT elements D51... D77 located in the 5th to 7th rows are connected to the signal processing circuit 2a arranged in FIG. Connected to the signal processing circuit 2b.
[0023]
According to the embodiment having the above structure, the number of pixel rows (or the number of columns) handled by one data line is substantially halved compared to the conventional structure (structure of FIG. 1), and the data line capacity of each data line is halved. As a result, noise can be reduced.
[0024]
Here, in the data division as shown in FIG. 2, the number of rows handled by each data line is different in the upper half (4 rows) and the lower half (3 rows), and even if calibration is properly performed, There may be discrepancies between the half and bottom half.
[0025]
A method for alleviating this will be described below with reference to FIGS.
In the example shown in FIG. 3, in order to alleviate the above-described problem, the division between the third row and the fourth row of the pixel array and the division between the fourth row and the fifth row are performed for each data line. A configuration is adopted in which the division boundary of the data lines is made uneven by repeating alternately.
[0026]
In the case of this example, the gate signal for row selection from the gate signal circuit selects a pixel group (pixel group P41 to P47 in the fourth row) located on the panel center line. As shown in the sending sequence of FIG. 4, first, a gate signal is output to the pixels on the panel center line at to, and then two gate signals for selecting the upper and lower rows are simultaneously output at t1. Subsequently, the row selection is sequentially advanced upward and downward at the same timing t2. Accordingly, in this example, at the time of the first data collection, the pixels P41, P43, P45, and P47 arranged in the odd columns among the pixels arranged in the fourth row are the pixels P42, P44 arranged in the even columns in the upper signal processing circuit 2a. , P46 are subjected to data collection processing in the lower signal processing circuit 2b.
[0027]
Here, since the data obtained when the signal processing circuit is different in this type of data collection may cause a slight discrepancy in terms of gain and linearity, in the example shown in FIGS. If the data of the pixels arranged on the center line of the panel is calibrated, a higher quality image can be obtained.
[0028]
The data processing method will be described with reference to FIGS.
In FIG. 5, “×” marks are actually measured values of odd-numbered pixels P41, P43, P45, and P47 arranged on the center line of the panel, and “◯” marks are actually measured values of even-numbered pixels P42, P44, and P46. is there. In the curve shown in FIG. 5, the “Δ” mark value obtained by interpolating the “×” mark pixel data coincides with the “O” mark actual measurement value, and conversely, the “○” mark pixel data is interpolated. If the process in which the obtained “+” mark value matches the “×” mark actual measurement value, that is, the process in which the two curves shown in FIG. You can calibrate for differences in gain and linearity in the data.
[0029]
An example of the specific method will be described.
As shown in FIG. 6, assuming that the measured values of the pixels P41 and P43 are da1 and da3 and the measured values of the pixels P42 and P44 are db2 and db4, respectively, the pixel data db2 'and the pixel P43 of the pixel P42, for example. The pixel data da3 ′ of
db2 '= (2db2 + da1 + da3) / 4
da3 '= (2da3 + db2 + db4) / 4
It can obtain | require by each formula of.
[0030]
FIG. 7 is a diagram showing a modification of the embodiment shown in FIG.
In the example shown in FIG. 7, among the two sets of charge sensitive amplifier groups arranged on both sides of the panel, the output cable of one charge sensitive amplifier group Aa1... Aa7 is connected to the other charge sensitive amplifier group Ab1. The two amplifier groups Aa1,... Aa7 and Ab1,... Ab7 are selectively connected to a common signal processing circuit via the switching circuit 4.
[0031]
As shown in FIG. 7, in this example, the gate signal is sent to the pixels on the panel center line at the time of to, and after t1, t1, t1 ', t2, t2',.・ ・ Sometimes a sequence is adopted in which gate signals are alternately output to the upper half and the lower half.
[0032]
Next, in the flat panel sensor of the present invention, an embodiment in which the gate line is divided will be described below with reference to FIG.
In the example of FIG. 8, the gate line group is divided between the fourth and fifth columns of the pixel array, and TFT elements D11,... D14,. .., D71... For D74, each gate terminal Dg is connected to the same gate line Ga1 ... Ga6 or Ga7 for each column arrangement, and is located in the fifth to seventh rows. .., D75... D77, each gate terminal Dg is connected to the same gate line Gb1... Gb6 or Gb7 for each column arrangement.
[0033]
Then, among the gate lines divided as described above, TFT elements D11,..., D71,..., D71,. .. Ga7 is connected to the gate control circuit 3a arranged on the left side of the panel 1 in the drawing, and TFT elements D15,..., D75,. Are connected to a gate control circuit 3b arranged on the right side of the panel 1 in the drawing.
[0034]
When the gate lines are divided in this way, the distance from the gate control circuits 3a and 3b to the farthest TFT element is substantially half that of the conventional (structure of FIG. 1), and the gates sent from the gate control circuits 3a and 3b. As a result of the reduction in delay and waveform distortion until the signal reaches the TFT element, the quality of the pixel signal is improved.
[0035]
FIG. 9 is a combination of the above-described configurations of FIG. 3 and FIG. 8, and includes data lines arranged for each pixel column or row and gate lines arranged for each pixel row or column, respectively. The panel is divided into two on the panel. Correspondingly, charge sensitive amplifiers Aa1,... Aa7 and Ab1,... Ab7 are arranged on both sides of panel 1, and gate control circuits 3a and 3b are arranged on both sides of panel 1. The charge-sensitive amplifiers Aa1,... Aa7 and Ab1,.
[0036]
Here, in the embodiment shown in FIG. 3, FIG. 8, and FIG. 9, the unevenness of the division boundary is a pattern that repeats in units of one pixel. However, the present invention is not limited to this, for example, as shown in FIG. In addition, the divisional unevenness may be a pattern extending over 2 pixels (4 pixels in the figure).
[0037]
In addition to the direct conversion type and indirect conversion type flat panel X sensors, panel type optical sensors such as image scanners, etc., the present invention is a close contact type for document reading, which has recently been studied for consumer use. It can also be used effectively for sensors.
[0038]
【The invention's effect】
As described above, according to the flat panel sensor of the present invention, the data line arranged for each column or row of pixels is divided into two on the panel, and the charge sensitive amplifier is sandwiched between the panels corresponding to this. Since they are arranged on both sides, the number of pixel rows (or the number of columns) handled by one data line can be substantially halved compared to a conventional panel. As a result, the line capacity of each data is halved, so that noise can be reduced.
[0039]
Further, according to the flat panel type sensor of the present invention, the gate line arranged for each pixel row or column is divided into two on the panel, and the gate control circuits are arranged on both sides of the panel correspondingly. As a result, the distance from the gate control circuit to the farthest TFT element can be made approximately half that of the conventional panel. As a result, the delay until the gate signal sent from the gate control circuit reaches the pixel TFT element and the waveform distortion are reduced, so that the quality of the pixel signal is improved.
[0040]
In addition, according to the present invention, the panel has a single panel, and the data lines and gate lines are divided on the panel to achieve the above-described effects. That is, problems such as an increase in the panel manufacturing process, machining accuracy of the fitting portion, and artifacts do not occur.
[0041]
Here, in the flat panel type sensor of the present invention, when the data line is divided, the pixel signals from the two sets of charge sensitive amplifier groups arranged on both sides of the panel are processed by the same signal processing circuit. If the configuration of selectively connecting the connection of one amplifier group to the signal processing circuit and the connection of the other amplifier group to the signal processing circuit is adopted, the processing amount of the signal processing circuit is Compared to, the cost is half, and the cost can be reduced accordingly.
[Brief description of the drawings]
FIG. 1 is a view showing an example of a conventional flat panel sensor. FIG. 2 is a view showing an embodiment of the first invention. FIG. 3 is a view showing another embodiment of the first invention. 4 is a diagram showing a transmission sequence of a gate signal in the embodiment of FIG. 3. FIG. 5 is an explanatory diagram of a data calibration method used in the embodiment of FIG. 3. FIG. FIG. 8 is a diagram showing still another embodiment of the first invention. FIG. 8 is a diagram showing an embodiment of the second invention. FIG. 9 is a diagram showing an embodiment of the third invention. Figure showing an example of dividing the shape into irregularities 【Explanation of symbols】
DESCRIPTION OF SYMBOLS 1 Flat panel type sensor 2a, 2b Signal processing circuit 3a, 3b Gate control circuit 4 Switching circuit P11 ... P17, ... P71, ... P77, ... Pixel D11 ... D17, ... D71,... D77,... TFT element Dd Drain terminal Dg Gate terminals Aa1,... Aa7, Ab1, .. Ab7 Charge sensitive amplifiers Sa1 ... Sa7, Sb1 ... Sb7 Data lines Ga1 ... Ga7, Gb1 ... Gb7 gate line

Claims (4)

A plurality of sensors are arranged in a matrix on an insulating substrate to form a two-dimensional pixel array, and data lines and gate lines for reading out pixel signals of the sensors are arranged in a matrix on the substrate on which the sensors are arranged. In a flat panel type sensor in which a charge sensitive amplifier and a gate control circuit are connected to the data line and the gate line, respectively,
The data lines arranged for each column or row of pixels are divided into two on the panel. Correspondingly, charge sensitive amplifiers are arranged on both sides of the panel, and the division boundaries of the data lines are uneven. Flat panel type sensor characterized by A plurality of sensors are arranged in a matrix on an insulating substrate to form a two-dimensional pixel array, and data lines and gate lines for reading out pixel signals of the sensors are arranged in a matrix on the substrate on which the sensors are arranged. In a flat panel type sensor in which a charge sensitive amplifier and a gate control circuit are connected to the data line and the gate line, respectively,
The gate lines arranged for each row or column of pixels are divided into two on the panel, and the gate control circuits are arranged on both sides across the panel, and the dividing boundary of the gate lines is uneven. A flat panel type sensor characterized by A plurality of sensors are arranged in a matrix on an insulating substrate to form a two-dimensional pixel array, and data lines and gate lines for reading out pixel signals of the sensors are arranged in a matrix on the substrate on which the sensors are arranged. In a flat panel type sensor in which a charge sensitive amplifier and a gate control circuit are connected to the data line and the gate line, respectively,
A data line arranged for each pixel column or row and a gate line arranged for each pixel row or column are each divided into two on the panel, and the charge sensitive amplifiers correspondingly sandwich both sides of the panel. The gate control circuit is arranged on both sides of the panel so as to be orthogonal to the arrangement of the amplifiers, and the division boundary between the data line and the gate line is uneven. Flat panel type sensor.   2. The flat panel sensor according to claim 1, wherein pixel signals from two sets of charge sensitive amplifiers arranged on both sides of the panel are processed by a common signal processing circuit. A flat panel sensor comprising means for selectively switching the connection of the one amplifier group to the signal processing circuit and the connection of the other amplifier group to the signal processing circuit.

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