JP5219481B2 - Imaging device - Google Patents

Description

  The present invention relates to an imaging apparatus and a control method for the imaging apparatus.

In an imaging system such as a digital camera, a CMOS sensor type imaging device may be used to image a subject.
JP 2003-51989

  A CMOS sensor type imaging device may use the circuit configuration shown in FIG.

  The imaging apparatus 1 illustrated in FIG. 8 includes a pixel array PA, a vertical scanning circuit block 121, a plurality of vertical output lines V0 to V2, and a reading unit 30.

  In the pixel array PA, a plurality of 100 (0, 0) to 100 (2, 3) are arranged in the row direction and the column direction. FIG. 8 illustrates a case where the pixels included in the pixel array PA are 3 columns × 4 rows.

  The vertical scanning circuit block 121 selects one row in the pixel array PA by supplying active pixel selection pulses φPSEL0 to φPSEL3 via the pixel selection lines PSEL0 to PSEL3. Further, the vertical scanning circuit block 121 supplies active pixel reset pulses φPRES0 to φPRES3 to the respective pixels via the pixel reset lines PRES0 to PRES3. The vertical scanning circuit block 121 supplies active pixel signal transfer pulses φPTX0 to φPTX3 to the respective pixels via the pixel signal transfer lines PTX0 to PTX3.

  The plurality of vertical output lines V0 to V2 are connected to the pixels in each column of the pixel array PA, respectively. Each vertical output line V0 to V2 extends along each column of the pixel array PA.

  The readout unit 30 reads out signals from the pixels in the row selected by the vertical scanning circuit block 121 in the pixel array PA at one ends V01 to V21 of the plurality of vertical output lines V0 to V2. The reading unit 30 generates an image signal according to the read signal and outputs it to the subsequent stage.

  Next, the configuration of each pixel 100 (0, 0) to 100 (2, 3) in the pixel array PA will be described. Hereinafter, the configuration of the pixel 100 (0, 0) will be described, but the configuration of the other pixels is the same as the configuration of the pixel 100 (0, 0).

  The pixel 100 (0, 0) includes a photodiode PD, a transfer MOS transistor M1, a floating diffusion (hereinafter referred to as FD) 101, and an amplification MOS transistor M3. The pixel 100 (0, 0) includes a reset MOS transistor M2, an amplification MOS transistor M3, and a selection MOS transistor M4.

  The photodiode PD generates an electric charge according to the received light. FIG. 8 illustrates a configuration in which the anode side is grounded. The cathode side of the photodiode PD is connected to the transfer MOS transistor M1.

  The transfer MOS transistor M1 transfers the charge accumulated in the photodiode PD to the FD 101 when an active transfer signal is supplied to the gate via the pixel signal transfer line PTX0.

  The FD 101 converts the transferred charge into a voltage, and inputs a signal (optical signal) corresponding to the potential to the gate of the amplification MOS transistor M3.

  When an active reset signal is supplied to the gate via the pixel reset line PRES0, the reset MOS transistor M2 resets the FD 101 connected to the source according to the potential of the reset power supplied to the drain. .

  In the amplification MOS transistor M3, a signal corresponding to the potential of the FD 101 is input to the gate. The amplification MOS transistor M3 performs a source follower operation together with the constant current source I connected via the vertical output line V0 when the selection MOS transistor M4 is turned on, amplifies the signal input to the gate, and selects the MOS transistor Output to the vertical output line V0 via M4. The selection MOS transistor M4 is turned on when an active pixel selection pulse is supplied to the gate via the pixel selection line PSEL0.

  Next, the configuration of the reading unit 30 will be described.

  The reading unit 30 includes a clamp capacitor C0, an operational amplifier 111, a noise signal transfer switch M11, an optical signal transfer switch M12, a noise signal holding capacitor CTN, and an optical signal holding capacitor CTS. The readout unit 30 includes a horizontal scanning circuit block 122, horizontal transfer switches M21 and M22, and a differential circuit block 112.

  The clamp capacitor C0 stores a noise signal or an optical signal transmitted to the vertical output lines V0 to V2. The clamp capacitor C0 performs a clamp operation together with the operational amplifier 111 at a predetermined timing, and clamps the accumulated noise signal or optical signal.

  In the operational amplifier 111, the clamp capacitor C0 is connected to the inverting input terminal, and the signal accumulated in the clamp capacitor C0 is transmitted. In the operational amplifier 111, the clamp voltage VC0R is supplied to the non-inverting input terminal. The operational amplifier 111 outputs a noise signal or an optical signal from its output terminal.

  The noise signal transfer switch M11 is turned on when an active noise signal transfer pulse φPTN is supplied to the gate via the noise signal transfer line PTN, and the noise signal output from the operational amplifier 111 is converted into a noise signal holding capacitor CTN. Forward to.

  The optical signal transfer switch M12 is turned on when an active optical signal transfer pulse φPTS is supplied to the gate via the optical signal transfer line PTS, and the optical signal output from the operational amplifier 111 is supplied to the optical signal holding capacitor CTS. Forward to.

  The noise signal holding capacitor CTN temporarily holds the transferred noise signal. In the noise signal holding capacitor CTN, an electrode opposite to an electrode to which a noise signal is transferred is grounded.

  The optical signal holding capacitor CTS temporarily holds the transferred optical signal. In the optical signal holding capacitor CTS, an electrode opposite to the electrode to which the optical signal is transferred is grounded.

  The horizontal scanning circuit block 122 sequentially activates horizontal scanning signals H0 to H2 supplied to the horizontal transfer switches M21 and M22 of each column.

  The horizontal transfer switches M21 and M22 are turned on when the active horizontal scanning signals H0 to H2 are supplied from the horizontal scanning circuit block 122 to the gates. As a result, the noise signal held in the noise signal holding capacitor CTN and the optical signal held in the optical signal holding capacitor CTS are supplied to the differential circuit block 112.

  The differential circuit block 112 calculates the difference between the noise signal and the optical signal to generate an image signal. Then, the differential circuit block 112 outputs the generated image signal to the subsequent stage.

  Next, a reading operation in the imaging apparatus 1 will be described with reference to FIG. FIG. 9 is a timing chart showing the operation of the imaging apparatus 1.

  The vertical scanning circuit block 121 sequentially selects the 0th row, the 1st row, the 2nd row, and the 3rd row of the pixel array PA by sequentially activating the pixel selection pulses φPSEL0, φPSEL1, φPSEL2, and φPSEL3. . That is, the vertical scanning circuit block 121 sequentially selects rows from the row farthest from one end V01 to V21 to the row closest to one end V01 to V21 in the pixel array PA.

  The readout unit 30 reads out signals from the pixels in the row selected by the vertical scanning circuit block 121 in the pixel array PA at one ends V01 to V21 of the plurality of vertical output lines V0 to V2. The reading unit 30 sequentially reads signals from the 0th row, the 1st row, the 2nd row, and the 3rd row of the pixel array PA. The reading unit 30 sequentially outputs the read signals for each column in the horizontal scanning period in which the horizontal scanning signals H0 to H2 are sequentially activated.

  At timing T1, the vertical scanning circuit block 121 activates the pixel selection pulse φPSEL0 (high level). As a result, the selection MOS transistor M4 of the pixel in the 0th row of the pixel array PA is turned on, and the 0th row of the pixel array PA is selected.

  At timing T2, the vertical scanning circuit block 121 activates the pixel reset pulse φPRES0 (high level). As a result, the reset MOS transistor M2 is turned on and the FD 101 is reset in the pixels in the 0th row of the pixel array PA. A signal (noise signal) based on the reset potential of the FD 101 is input to the gate of the amplification MOS transistor M3, and the noise signal of the pixel in the 0th row is input to the amplification MOS transistor M3 and one ends V01 to V21 of the vertical output lines V0 to V2. Read by the reading unit 30.

  At timing T3, the vertical scanning circuit block 121 makes the pixel reset pulse φPRES0 inactive (low level). Thereby, the reset of the FD 101 is completed.

  In a period CP1 between timings T3 and T4, an effective wiring capacity (capacitance indicated by a broken line) of the vertical output lines V0 to V2 and a clamp capacity C0 are generated by a voltage corresponding to the noise signal output from the pixel in the 0th row. Charge is charged (accumulated) in the clamp capacitor C0 according to the capacitance ratio. Then, the voltages of the vertical output lines V0 to V2 are sufficiently stabilized.

  At timing T4, the vertical scanning circuit block 121 changes the potential of the clamp voltage VC0R from the low level to the high level. As a result, the clamping operation by the operational amplifier 111 and the clamping capacitor C0 is started, and the noise signal starts to be clamped.

  At timing T5, the vertical scanning circuit block 121 changes the potential of the clamp voltage VC0R from the high level to the low level. Thereby, the clamping operation by the operational amplifier 111 and the clamping capacitor C0 is completed, and the noise signal is clamped.

  At timing T6, the vertical scanning circuit block 121 activates the noise signal transfer pulse φPTN (high level). As a result, the noise signal transfer switch M11 is turned on, and the noise signal accumulated in the clamp capacitor C0 is amplified by the operational amplifier 111 and then transferred to the noise signal holding capacitor CTN.

  At timing T7, the vertical scanning circuit block 121 makes the noise signal transfer pulse φPTN inactive (low level). As a result, the noise signal is held in the noise signal holding capacitor CTN.

  At timing T8, the vertical scanning circuit block 121 sets the pixel signal transfer pulse φPTX0 to the high level. Thereby, in the pixel in the 0th row of the pixel array PA, the transfer MOS transistor M1 is turned on, and the charge accumulated in the photodiode PD is transferred to the FD101. A signal (optical signal) based on the potential of the FD 101 is input to the gate of the amplification MOS transistor M3, and the optical signal of the pixel in the 0th row is read by the readout unit 30 at one end of the amplification MOS transistor M3 and the vertical output lines V0 to V2. Read out.

  At timing T9, the vertical scanning circuit block 121 makes the pixel signal transfer pulse φPTX0 inactive (low level). As a result, the transfer MOS transistor M1 is turned off in the pixels in the 0th row of the pixel array PA.

  In a period CP2 between timings T9 and T10, an effective wiring capacity (capacitance indicated by a broken line) of the vertical output lines V0 to V2 and a clamp capacity C0 are generated by a voltage corresponding to the optical signal output from the pixel in the 0th row. Charge is charged (accumulated) in the clamp capacitor C0 according to the capacitance ratio. Then, the voltages of the vertical output lines V0 to V2 are sufficiently stabilized.

  At timing T10, the vertical scanning circuit block 121 activates the optical signal transfer pulse φPTS (high level). As a result, the optical signal transfer switch M12 is turned on, and the optical signal accumulated in the clamp capacitor C0 is amplified by the operational amplifier 111 and then transferred to the optical signal holding capacitor CTS.

  At timing T11, the vertical scanning circuit block 121 makes the optical signal transfer pulse φPTS inactive (low level). As a result, the optical signal is held in the optical signal holding capacitor CTS.

  At timing T12, the vertical scanning circuit block 121 makes the pixel selection pulse φPSEL0 inactive (low level). As a result, the selection MOS transistor M4 is turned off in the pixels in the 0th row of the pixel array PA. The 0th row of the pixel array PA is not selected.

  In a period (horizontal scanning period) of timings T13 to T14, the horizontal scanning circuit block 122 sequentially activates the horizontal scanning signals H0 to H2. The horizontal transfer switches M21 and M22 corresponding to each column of the pixel array PA are sequentially turned on. Thereby, the noise signal and the optical signal of the pixel in each column of the 0th row are sequentially supplied from the noise signal holding capacitor CTN and the optical signal holding capacitor CTS to the differential circuit block 112 for each column. The differential circuit block 112 calculates the difference between the noise signal and the optical signal to generate an image signal, and outputs the image signal to the subsequent stage.

  As described above, in the read operation of the 0th row of the pixel array PA, the pixel signals of the pixels in each column of the 0th row of the pixel array PA are read, and image signals corresponding to the pixel signals are sequentially transmitted. Output to the subsequent stage. The readout operation for the first to third rows of the pixel array PA is similarly repeated. As a result, the reading operation for one frame is completed.

  Here, in the periods CP1, CP3, CP5, and CP7 shown in FIG. 9, the clamp capacitance C0 is generated according to the capacitance ratio between the wiring capacitance WC1 of the vertical output lines V0 to V2 and the clamp capacitance C0 by the noise signal output from the pixel. It is necessary to have a sufficient period for the electric charge to be charged. Similarly, in periods CP2, CP4, CP6, and CP8, the clamp capacitor C0 is charged with an optical signal output from the pixel according to the capacitance ratio between the wiring capacitance WC1 and the clamp capacitance C0 of the vertical output lines V0 to V2. It needs to be long enough to be played. If the clamp capacitor C0 is constant, the longer the wiring capacitor WC1 of the vertical output line, the longer it takes to charge the clamp capacitor C0. Therefore, the length of the periods CP1 to CP8 must be increased. There is a possibility of disappearing.

  In particular, when the imaging device 1 is a digital single-lens reflex camera or the like, the imaging sensor used tends to be large. When the imaging sensor is large, the wiring length of the vertical output line is long, so that the wiring capacity may be increased. In addition, since the vertical output lines tend to be miniaturized corresponding to the miniaturization of each pixel included in the pixel array PA of the imaging device 1, the inter-wiring capacitance is reduced by reducing the distance between adjacent wirings. May grow. As a result, the effective wiring capacity of the vertical output line may increase. As described above, when the wiring capacitance WC1 of the vertical output line is increased, there is a possibility that the lengths of the periods CP1 to CP8 must be increased as described above. Time can be long.

  An object of the present invention is to provide an imaging apparatus capable of reducing the time required for the reading operation for one frame.

An imaging apparatus according to a first aspect of the present invention includes a pixel array in which a plurality of pixels are arrayed in a row direction and a column direction, selection means for selecting at least one row in the pixel array, and each column of the pixel array. A plurality of output lines for outputting the respective signals of the pixels in each column in the column direction, and signals from the pixels in the row selected by the selection unit in the pixel array via the plurality of output lines. Read means for reading, and a plurality of separating means for electrically separating the rows of the pixel array between the rows in each of the plurality of output lines, and the selecting means includes the pixel array The plurality of output lines are sequentially selected from a row farthest from the output end of the plurality of output lines to a row closest to the output end, and the detaching means includes a row of pixels from which signals are read out in the pixel array. Between rows of the row of pixels that are not Desa see, characterized in that separating the plurality of output lines electrically.

  According to the present invention, the time required for the reading operation for one frame can be shortened.

  The present invention relates to an imaging system using a CMOS sensor type imaging device, and more particularly to speeding up signal readout of the imaging device.

  An imaging system 20a according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a configuration diagram of an imaging system 20a according to the first embodiment of the present invention.

  The imaging system 20a is, for example, a digital camera or a digital video camera. The imaging system 20a includes an imaging optical system 19, a mechanical shutter 2, an imaging device 1a, a timing signal generation circuit 5, a drive circuit 6, a signal processing circuit 7, and an image memory 8. The imaging system 20 a includes a recording circuit 10, a display circuit 12, an image display device 11, a system control unit 13, a nonvolatile memory (hereinafter referred to as ROM) 14, and a volatile memory (hereinafter referred to as RAM) 15. The imaging system 20a includes a plurality of switches 16 to 18 (power supply SW16, first SW17, and second SW18).

  The imaging optical system 19 receives the incident light and forms an image of the subject on the imaging surface of the imaging device 1a. The photographing optical system 19 includes a lens and a diaphragm.

  The mechanical shutter 2 is provided between the photographing optical system 19 and the imaging device 1a on the optical path, and controls exposure.

  The imaging device 1a converts the image of the subject formed on the imaging surface into an image signal. The imaging device 1a reads the image signal from the pixel array PA and outputs it.

  The timing signal generation circuit 5 generates a reference clock signal that serves as a reference for drive signals for driving the photographing optical system 1, the mechanical shutter 2, and the imaging device 3 in accordance with a command from the system control unit 13. The timing signal generation circuit 5 supplies a reference clock signal to the drive circuit 6.

  The drive circuit 6 receives the reference clock signal and generates drive signals for driving the imaging optical system 19, the mechanical shutter 2, and the imaging device 3. The drive circuit 6 supplies each drive signal to the imaging optical system 19, the mechanical shutter 2, and the imaging device 1a.

  The signal processing circuit 7 receives the image signal from the imaging device 1a, performs A / D conversion on the image signal, and performs arithmetic processing (signal processing) such as various corrections to generate image data. This image data is supplied to the image memory 8, the recording circuit 10, the system control unit 13, and the like.

  The image memory 8 receives the signal processed image data from the signal processing circuit 7 and stores it.

  A recording medium 9 is detachably connected to the recording circuit 10. The recording circuit 10 receives the signal-processed image data from the signal processing circuit 7 and records the image data on the connected recording medium 9.

  The display circuit 12 receives the signal-processed image data from the signal processing circuit 7 and converts the image data into a display signal.

  The image display device 11 receives a display signal from the display circuit 12 and displays an image corresponding to the image data.

  The system control unit 13 controls the entire imaging system 20a.

  The ROM 14 stores a program describing a control method executed by the system control unit 13, control data such as parameters and tables used when executing the program, and correction data such as defective pixel information. The system control unit 13 refers to these pieces of information as necessary when performing a predetermined control operation.

  The RAM 15 is used as a temporary storage area (work area) when the system control unit 13 performs a predetermined control operation.

  The plurality of switches 16 to 18 are connected to the system control unit 13 and execute processing corresponding to each state. Each switch 16-18 performs the following processes, for example.

  The power SW 16 executes a process for starting the imaging system 20a in response to a state where a power button (not shown) is pressed.

  In response to the shutter button (not shown) being in the first state (for example, half-pressed state), the first SW 17 generates a signal instructing a photographing preparation operation such as photometry processing and distance measurement processing. These signals are supplied to the system control unit 13. Thereby, the system control unit 13 performs control operations for photographing preparation operations such as photometry processing and distance measurement processing.

  The second SW 18 generates a signal instructing the start of the imaging operation in response to a shutter button (not shown) being in the second state (for example, fully pressed state), and the signal is sent to the system control unit 13. To supply. Thereby, the system control unit 13 starts a control operation for the imaging operation. That is, the mirror (not shown), the mechanical shutter 2, and the electronic shutter of the imaging device 3 are driven, and the image signal read from the imaging device 3 is transferred to the recording medium 9 via the signal processing circuit 7 and the recording circuit 10. A series of imaging operations to be written is performed.

  Next, the imaging device 1a according to the first embodiment of the present invention will be described with reference to FIG. FIG. 2 is a configuration diagram of the imaging apparatus 1a according to the first embodiment of the present invention. The circuit elements constituting the imaging device 1a are not particularly limited by the manufacturing technology of the semiconductor integrated circuit, but are formed on a single semiconductor substrate such as single crystal silicon.

  The imaging apparatus 1a includes a pixel array PA, a vertical scanning circuit block (selection unit) 121a, a plurality of vertical output lines V0a to V2a, a plurality of separation units (a plurality of separation units) MVOFF00a to MVOFF22a, and a reading unit (reading unit) 30. Prepare.

  In the pixel array PA, a plurality of pixels 100 (0, 0) to 100 (2, 3) are arrayed in the row direction and the column direction. FIG. 2 illustrates a case where the pixels included in the pixel array PA are 3 columns × 4 rows.

  The vertical scanning circuit block 121a selects one row in the pixel array PA by supplying active pixel selection pulses φPSEL0 to φPSEL3 via the pixel selection lines PSEL0 to PSEL3. Further, the vertical scanning circuit block 121a supplies active pixel reset pulses φPRES0 to φPRES3 to the respective pixels via the pixel reset lines PRES0 to PRES3. The vertical scanning circuit block 121a supplies active pixel signal transfer pulses φPTX0 to φPTX3 to the respective pixels via the pixel signal transfer lines PTX0 to PTX3. The vertical scanning circuit block 121a supplies active separation pulses φPVOFF0a to φPVOFF2a to the plurality of separation units MVOFF00a to MVOFF22a via the separation lines PVOFF0a to PVOFF2a.

  The plurality of vertical output lines V0a to V2a are respectively connected to the pixels in each column of the pixel array PA. Each vertical output line V0a to V2a extends along each column of the pixel array PA. Here, the wiring capacity of the vertical output lines V0a to V2a in the initial state is WC1.

  The plurality of separation portions MVOFF00a to MVOFF22a are provided in all of the plurality of portions between the rows of the pixel array PA in each of the plurality of vertical output lines V0a to V2a. Accordingly, the plurality of separation units MVOFF00a to MVOFF22a electrically separate all of the plurality of portions between the rows of the pixel array PA in each of the plurality of vertical output lines V0a to V2a. For example, the plurality of separation units MVOFF00a to MVOFF22a electrically separate the pixels in the row from which the signal is read in the pixel array PA and the readout unit 30.

  The readout unit 30 reads out signals from the pixels in the row selected by the vertical scanning circuit block 121a in the pixel array PA at one ends V0a1 to V2a1 of the plurality of vertical output lines V0a to V2a. The reading unit 30 generates an image signal according to the read signal and outputs it to the subsequent stage.

  Next, the configuration of each pixel 100 (0, 0) to 100 (2, 3) in the pixel array PA will be described. Hereinafter, the configuration of the pixel 100 (0, 0) will be described, but the configuration of the other pixels is the same as the configuration of the pixel 100 (0, 0).

  The pixel 100 (0, 0) includes a photodiode PD, a transfer MOS transistor M1, a floating diffusion (hereinafter referred to as FD) 101, and an amplification MOS transistor M3. The pixel 100 (0, 0) includes a reset MOS transistor M2, an amplification MOS transistor M3, and a selection MOS transistor M4.

  The photodiode PD generates an electric charge according to the received light. FIG. 2 illustrates a configuration in which the anode side is grounded. The cathode side of the photodiode PD is connected to the transfer MOS transistor M1.

  The transfer MOS transistor M1 transfers the charge accumulated in the photodiode PD to the FD 101 when an active transfer signal is supplied to the gate via the pixel signal transfer line PTX0.

  The FD 101 converts the transferred charge into a voltage, and inputs a signal (optical signal) corresponding to the potential to the gate of the amplification MOS transistor M3.

  When an active reset signal is supplied to the gate via the pixel reset line PRES0, the reset MOS transistor M2 resets the FD 101 connected to the source according to the potential of the reset power supplied to the drain. .

  In the amplification MOS transistor M3, a signal corresponding to the potential of the FD 101 is input to the gate. The amplification MOS transistor M3 performs a source follower operation together with the constant current source I connected via the vertical output line V0 when the selection MOS transistor M4 is turned on, amplifies the signal input to the gate, and selects the MOS transistor Output to the vertical output line V0 via M4. The selection MOS transistor M4 is turned on when an active pixel selection pulse is supplied to the gate via the pixel selection line PSEL0.

  Next, the configuration of the plurality of separation units MVOFF00a to MVOFF22a will be described. In the following, description will be made centering on the disconnecting portions MVOFF00a to MVOFF02a connected to the vertical output line V0a of the 0th column. The disconnecting portions MVOFF10a to MVOFF22a connected to the other vertical output lines V1a and V2a are the same as the disconnecting portions MVOFF00a to MVOFF02a.

  The separation unit MVOFF00a is provided between the 0th and 1st rows of the pixel array PA on the vertical output line V0a. The separation unit MVOFF00a is, for example, a MOS transistor. In this case, in the separation unit MVOFF00a, the drain is connected to the pixel 100 (0, 0) in the 0th row, the source is the pixels 100 (0, 1) to 100 (0, 3) and the readout in the first row and thereafter. Connected to the unit 30. The separation unit MVOFF00a is turned on when the active separation pulse φPVOFF0a is supplied to the gate, and electrically connects the pixel 100 (0, 0) in the 0th row and the readout unit 30. In this state, the effective length of the vertical output line V0a is L1a.

  The separation unit MVOFF00a is turned off when the non-active separation pulse φPVOFF0a is supplied to the gate, and electrically separates the pixel 100 (0, 0) in the 0th row from the readout unit 30. In this state, the effective length of the vertical output line V0a is L2a (<L1a). As a result, the wiring capacity WC2 of the vertical output line V0a is smaller than the wiring capacity WC1 when the effective length of the vertical output line V0a is L1a.

  The separation unit MVOFF01a is provided between the first row and the second row of the pixel array PA on the vertical output line V0a. The separation unit MVOFF01a is, for example, a MOS transistor. In this case, the separation unit MVOFF01a has its drain connected to the pixels 100 (0,0) and 100 (0,1) in the 0th and 1st rows, and its source as the pixels 100 (0,0) in the second and subsequent rows. 2), 100 (0, 3) and the reading unit 30. The separation unit MVOFF01a is turned on when the active separation pulse φPVOFF1a is supplied to the gate, and the pixels 100 (0, 0) and 100 (0, 1) in the 0th and 1st rows and the readout unit 30 Are electrically connected. The separation unit MVOFF01a is turned off when the non-active separation pulse φPVOFF1a is supplied to the gate, and the pixels 100 (0, 0) and 100 (0, 1) in the 0th and 1st rows and the readout unit 30 are turned off. Is electrically disconnected. In this state, the effective length of the vertical output line V0a is L3a (<L2a). As a result, the wiring capacity WC3 of the vertical output line V0a is smaller than the wiring capacity WC2 when the effective length of the vertical output line V0a is L2a.

  The separation unit MVOFF02a is provided between the second and third rows of the pixel array PA on the vertical output line V0a. The separation unit MVOFF02a is, for example, a MOS transistor. In this case, in the separation unit MVOFF02a, the drain is connected to the pixels 100 (0, 0) to 100 (0, 2) in the 0th row to the 2nd row, and the source is the pixel 100 (0, 0) in the 3rd row and thereafter. 3) and the reading unit 30. The separation unit MVOFF02a is turned on when the active separation pulse φPVOFF2a is supplied to the gate, and the pixels 100 (0, 0) to 100 (0, 2) in the 0th to 2nd rows and the readout unit 30 Are electrically connected. The separation unit MVOFF02a is turned off when the non-active separation pulse φPVOFF2a is supplied to the gate, and the pixels 100 (0, 0) to 100 (0, 2) in the 0th to 2nd rows and the readout unit 30 are turned off. Is electrically disconnected. In this state, the effective length of the vertical output line V0a is L4a (<L3a). As a result, the wiring capacity WC4 of the vertical output line V0a is smaller than the wiring capacity WC3 when the effective length of the vertical output line V0a is L3a.

  Next, the configuration of the reading unit 30 will be described.

  The reading unit 30 includes a clamp capacitor C0, an operational amplifier 111, a noise signal transfer switch M11, an optical signal transfer switch M12, a noise signal holding capacitor CTN, and an optical signal holding capacitor CTS. The readout unit 30 includes a horizontal scanning circuit block 122, horizontal transfer switches M21 and M22, and a differential circuit block 112.

  The clamp capacitor C0 stores a noise signal or an optical signal transmitted to the vertical output lines V0a to V2a. The clamp capacitor C0 performs a clamp operation together with the operational amplifier 111 at a predetermined timing, and clamps the accumulated noise signal or optical signal.

  In the operational amplifier 111, the clamp capacitor C0 is connected to the inverting input terminal, and the signal accumulated in the clamp capacitor C0 is transmitted. In the operational amplifier 111, the clamp voltage VC0R is supplied to the non-inverting input terminal. The operational amplifier 111 outputs a noise signal or an optical signal from its output terminal.

  The noise signal transfer switch M11 is turned on when an active noise signal transfer pulse φPTN is supplied to the gate via the noise signal transfer line PTN, and the noise signal output from the operational amplifier 111 is converted into a noise signal holding capacitor CTN. Forward to.

  The optical signal transfer switch M12 is turned on when an active optical signal transfer pulse φPTS is supplied to the gate via the optical signal transfer line PTS, and the optical signal output from the operational amplifier 111 is supplied to the optical signal holding capacitor CTS. Forward to.

  The noise signal holding capacitor CTN temporarily holds the transferred noise signal. In the noise signal holding capacitor CTN, an electrode opposite to an electrode to which a noise signal is transferred is grounded.

  The optical signal holding capacitor CTS temporarily holds the transferred optical signal. In the optical signal holding capacitor CTS, an electrode opposite to the electrode to which the optical signal is transferred is grounded.

  The horizontal scanning circuit block 122 sequentially activates horizontal scanning signals H0 to H2 supplied to the horizontal transfer switches M21 and M22 of each column.

  The horizontal transfer switches M21 and M22 are turned on when the active horizontal scanning signals H0 to H2 are supplied from the horizontal scanning circuit block 122 to the gates. As a result, the noise signal held in the noise signal holding capacitor CTN and the optical signal held in the optical signal holding capacitor CTS are supplied to the differential circuit block 112.

  The differential circuit block 112 calculates the difference between the noise signal and the optical signal to generate an image signal. Then, the differential circuit block 112 outputs the generated image signal to the subsequent stage.

  Next, a reading operation in the imaging apparatus 1a will be described with reference to FIG. FIG. 3 is a timing chart showing the operation of the imaging apparatus 1a.

  The vertical scanning circuit block 121a sequentially selects the 0th row, the 1st row, the 2nd row, and the 3rd row of the pixel array PA by sequentially activating the pixel selection pulses φPSEL0, φPSEL1, φPSEL2, and φPSEL3. . That is, the vertical scanning circuit block 121a sequentially selects rows from the row farthest from one end V0a1 to V2a1 to the row closest to the one end V0a1 to V2a1 in the pixel array PA.

  The readout unit 30 reads out signals from the pixels in the row selected by the vertical scanning circuit block 121a in the pixel array PA at one ends V0a1 to V2a1 of the plurality of vertical output lines V0a to V2a. The reading unit 30 sequentially reads signals from the 0th row, the 1st row, the 2nd row, and the 3rd row of the pixel array PA. The reading unit 30 sequentially outputs the read signals for each column in the horizontal scanning period in which the horizontal scanning signals H0 to H2 are sequentially activated.

  At timing T0a, the vertical scanning circuit block 121a activates the separation pulses φPVOFF0a to PVOFF2a. As a result, the plurality of separation portions MVOFF00a to MVOFF22a are turned on, and the effective lengths of the plurality of vertical output lines V0a to V2a are all L1a.

  At timing T1, the vertical scanning circuit block 121a activates the pixel selection pulse φPSEL0 (high level). As a result, the selection MOS transistor M4 of the pixel in the 0th row of the pixel array PA is turned on, and the 0th row of the pixel array PA is selected. Further, the vertical scanning circuit block 121a activates the separation pulses φPVOFF0a to PVOFF2a. As a result, the plurality of separation portions MVOFF00a to MVOFF22a are turned on, and the effective lengths of the plurality of vertical output lines V0a to V2a are all L1a.

  At timing T2, the vertical scanning circuit block 121a activates the pixel reset pulse φPRES0 (high level). As a result, the reset MOS transistor M2 is turned on and the FD 101 is reset in the pixels in the 0th row of the pixel array PA. Then, a signal (noise signal) based on the reset potential of the FD 101 is input to the gate of the amplification MOS transistor M3. The noise signal of the pixel in the 0th row is read by the reading unit 30 through the amplification MOS transistor M3 and one ends V0a1 to V2a1 of the vertical output lines V0a to V2a.

  At timing T3, the vertical scanning circuit block 121a makes the pixel reset pulse φPRES0 non-active (low level). Thereby, the reset of the FD 101 is completed.

  In a period CP1 between timings T3 and T4, the effective wiring capacitances (capacities indicated by broken lines) WC1 and clamp capacitances C0 of the vertical output lines V0a to V2a are generated by a voltage corresponding to the noise signal output from the pixel in the 0th row. The charge is charged (accumulated) in the clamp capacitor C0 according to the capacitance ratio. Then, the voltages of the vertical output lines V0a to V2a are sufficiently stabilized.

  At timing T4, the vertical scanning circuit block 121a changes the potential of the clamp voltage VC0R from the low level to the high level. As a result, the clamping operation by the operational amplifier 111 and the clamping capacitor C0 is started, and the noise signal starts to be clamped.

  At timing T5, the vertical scanning circuit block 121a changes the potential of the clamp voltage VC0R from the high level to the low level. Thereby, the clamping operation by the operational amplifier 111 and the clamping capacitor C0 is completed, and the noise signal is clamped.

  At timing T6, the vertical scanning circuit block 121a activates the noise signal transfer pulse φPTN (high level). As a result, the noise signal transfer switch M11 is turned on, and the noise signal accumulated in the clamp capacitor C0 is amplified by the operational amplifier 111 and then transferred to the noise signal holding capacitor CTN.

  At timing T7, the vertical scanning circuit block 121a makes the noise signal transfer pulse φPTN inactive (low level). As a result, the noise signal is held in the noise signal holding capacitor CTN.

  At timing T8, the vertical scanning circuit block 121a sets the pixel signal transfer pulse φPTX0 to a high level. Thereby, in the pixel in the 0th row of the pixel array PA, the transfer MOS transistor M1 is turned on, and the charge accumulated in the photodiode PD is transferred to the FD101. Then, a signal (optical signal) based on the potential of the FD 101 is input to the gate of the amplification MOS transistor M3, and the optical signal of the pixel in the 0th row is read by the amplification MOS transistor M3 and one ends V0a1 to V2a1 of the vertical output lines V0a to V2a. Read by the unit 30.

  At timing T9, the vertical scanning circuit block 121a makes the pixel signal transfer pulse φPTX0 inactive (low level). As a result, the transfer MOS transistor M1 is turned off in the pixels in the 0th row of the pixel array PA.

  In a period CP2 between timings T9 and T10, the effective wiring capacitances (capacities indicated by broken lines) WC1 and clamp capacitances C0 of the vertical output lines V0a to V2a are determined by the voltage corresponding to the optical signal output from the pixel in the 0th row. The charge is charged (accumulated) in the clamp capacitor C0 according to the capacitance ratio. Then, the voltages of the vertical output lines V0a to V2a are sufficiently stabilized.

  At timing T10, the vertical scanning circuit block 121a activates the optical signal transfer pulse φPTS (high level). As a result, the optical signal transfer switch M12 is turned on, and the optical signal accumulated in the clamp capacitor C0 is amplified by the operational amplifier 111 and then transferred to the optical signal holding capacitor CTS.

  At timing T11, the vertical scanning circuit block 121a makes the optical signal transfer pulse φPTS inactive (low level). As a result, the optical signal is held in the optical signal holding capacitor CTS.

  At timing T12a, the vertical scanning circuit block 121a makes the pixel selection pulse φPSEL0 inactive (low level). As a result, the selection MOS transistor M4 is turned off in the pixels in the 0th row of the pixel array PA. The 0th row of the pixel array PA is not selected. Further, the vertical scanning circuit block 121a makes the separation pulse φPVOFF0a non-active. As a result, the separation portions MVOFF00a, MVOFF10a, and MVOFF20a provided between the 0th and 1st rows of the pixel array PA are turned off, and the effective lengths of the plurality of vertical output lines V0a to V2a are all. L2a (<L1a). Accordingly, the effective wiring capacity of the plurality of vertical output lines V0a to V2a is WC2 (<WC1).

  In a period (horizontal scanning period) of timings T13 to T14, the horizontal scanning circuit block 122 sequentially activates the horizontal scanning signals H0 to H2. The horizontal transfer switches M21 and M22 corresponding to each column of the pixel array PA are sequentially turned on. Thereby, the noise signal and the optical signal of the pixel in each column of the 0th row are sequentially supplied from the noise signal holding capacitor CTN and the optical signal holding capacitor CTS to the differential circuit block 112 for each column. The differential circuit block 112 calculates the difference between the noise signal and the optical signal to generate an image signal, and outputs the image signal to the subsequent stage.

  In this manner, in the readout operation of the 0th row of the pixel array PA, the pixel signals of the pixels in each column of the 0th row of the pixel array PA are read out, and the image signals corresponding to the pixel signals are sequentially output in the subsequent stage. Is output. The readout operation of the first to third rows of the pixel array PA is basically repeated in the same manner, but the operation different from the zeroth row is performed in the following points.

  In a period CP3a between timings T15a to T16a, the voltage corresponding to the noise signal output from the pixel in the first row is used in accordance with the capacitance ratio between the effective wiring capacitance WC2 and the clamp capacitance C0 of the vertical output lines V0a to V2a. The clamp capacitor C0 is charged.

  In a period CP4a of timing T17a to T18a, the voltage according to the optical signal output from the pixel in the first row is used according to the capacitance ratio between the effective wiring capacitance WC2 and the clamp capacitance C0 of the vertical output lines V0a to V2a. The clamp capacitor C0 is charged.

  At timing T19a, the vertical scanning circuit block 121a deactivates the separation pulse φPVOFF1a. Thereby, the separation portions MVOFF01a, MVOFF11a, and MVOFF21a provided between the first and second rows of the pixel array PA are turned off, and the effective lengths of the plurality of vertical output lines V0a to V2a are all. L3a (<L2a). Accordingly, the effective wiring capacity of the plurality of vertical output lines V0a to V2a is WC3 (<WC2).

  In a period CP5a between timings T20a to T21a, a voltage corresponding to a noise signal output from the pixels in the second row is used in accordance with a capacitance ratio between the effective wiring capacitance WC3 and the clamp capacitance C0 of the vertical output lines V0a to V2a. The clamp capacitor C0 is charged.

  In a period CP6a of timing T22a to T23a, the voltage corresponding to the optical signal output from the pixel in the second row is used according to the capacitance ratio between the effective wiring capacitance WC3 and the clamp capacitance C0 of the vertical output lines V0a to V2a. The clamp capacitor C0 is charged.

  At timing T24a, the vertical scanning circuit block 121a deactivates the separation pulse φPVOFF2a. As a result, the separation portions MVOFF02a, MVOFF12a, and MVOFF22a provided between the second and third rows of the pixel array PA are turned off, and the effective lengths of the plurality of vertical output lines V0a to V2a are all. L4a (<L3a). Accordingly, the effective wiring capacity of the plurality of vertical output lines V0a to V2a is WC4 (<WC3).

  In a period CP7a between timings T25a to T26a, the voltage corresponding to the noise signal output from the pixel in the third row is used in accordance with the capacitance ratio between the effective wiring capacitance WC4 and the clamp capacitance C0 of the vertical output lines V0a to V2a. The clamp capacitor C0 is charged.

  In a period CP8a of timing T27a to T28a, depending on the voltage according to the optical signal output from the pixel in the third row, according to the capacitance ratio between the effective wiring capacitance WC4 and the clamp capacitance C0 of the vertical output lines V0a to V2a. The clamp capacitor C0 is charged.

  As described above, the readout operation for one frame is completed as a result of the readout operation of the 0th to 3rd rows.

  Here, the vertical output lines V0a to V2a have an effective length L2a in the first row read operation shorter than an effective length L1a in the zeroth row read operation. As a result, the vertical output lines V0a to V2a have a smaller wiring capacitance WC2 in the first row read operation than the wiring capacitance WC1 in the zeroth row read operation. As a result, compared to the periods CP1 and CP2 for charging the clamp capacitor C0 in the read operation of the 0th row, the periods CP3a and CP4a for charging the clamp capacitor C0 in the read operation of the first row are compared. Can be shortened.

  The vertical output lines V0a to V2a are shorter in effective length L3a in the second row read operation than in the effective length L2a in the first row read operation. Thereby, the vertical output lines V0a to V2a have a wiring capacitance WC3 in the read operation in the second row smaller than the wiring capacitance WC2 in the read operation in the first row. As a result, compared with the periods CP3a and CP4a for charging the clamp capacitor C0 in the first row read operation, the periods CP5a and CP6a for charging the clamp capacitor C0 in the second row read operation are compared. Can be shortened.

  The vertical output lines V0a to V2a are shorter in effective length L4a in the third row read operation than in the effective length L3a in the second row read operation. As a result, the vertical output lines V0a to V2a have a smaller wiring capacitance WC4 in the third row read operation than the wiring capacitance WC3 in the second row read operation. As a result, compared to the periods CP5a and CP6a for charging the clamp capacitor C0 in the second row read operation, the periods CP7a and CP8a for charging the clamp capacitor C0 in the third row read operation are set. Can be shortened.

  As described above, a signal can be read from the pixel array PA while reducing the effective wiring capacity of the vertical output line during the reading operation for one frame. As a result, the time for charging the clamp capacitor C0 during the reading operation for one frame can be shortened, so that the time required for the reading operation for one frame can be shortened as a whole.

  The present invention is more effective as the imaging device has a larger area of the pixel array PA and longer vertical output lines V0a to V2a. For example, it is effective in a large-sized imaging device used for a digital single-lens reflex camera, a large format digital camera, or the like.

  Next, an imaging system 20b according to a second embodiment of the present invention will be described using FIG. FIG. 4 is a configuration diagram of the imaging device 1b in the imaging system 20b according to the second embodiment of the present invention.

The imaging system 20b is different from the first embodiment in that the imaging system 20b includes the imaging device 1b. The imaging device 1b includes a vertical scanning circuit block 121b and a plurality of vertical output lines V0b to V2b. The imaging device 1b does not include a plurality of separation units MVOFF00a, MVOFF10a, MVOFF20a, MVOFF02a, MVOFF12a, and MVOFF22a. That is, a plurality of separation portions MVOFF01a, MVOFF11a, and MVOFF21a are provided between the rows of the pixel array PA in each of the plurality of vertical output lines V0b to V2b. Specifically, a plurality of cut-off portion MVOFF01a, MVOFF11a, MVOFF21a is provided between the second and third rows of the pixel array PA. In other words, the plurality of separation portions MVOFF01a, MVOFF11a, and MVOFF21a electrically separate one of the plurality of portions between the rows of the pixel array PA in each of the plurality of vertical output lines V0b to V2b.

  Next, as shown in FIG. 5, the reading operation in the imaging apparatus 1b differs from the first embodiment in the following points. FIG. 5 is a timing chart showing the operation of the imaging apparatus 1b.

  At timing T0b, the vertical scanning circuit block 121b activates the separation pulse φPVOFF1a. As a result, the plurality of separation portions MVOFF01a, MVOFF11a, and MVOFF21a are turned on, and the effective lengths of the plurality of vertical output lines V0b to V2b are all L1a.

  At timing T12b, the effective lengths of the plurality of vertical output lines V0b to V2b remain L1a, and the effective wiring capacitances of the plurality of vertical output lines V0b to V2b remain WC1.

  In the period CP3b from timing T15b to T16b, the voltage corresponding to the noise signal output from the pixels in the first row is used to correspond to the effective wiring capacitance WC1 and clamp capacitance C0 of the vertical output lines V0b to V2b. The clamp capacitor C0 is charged.

  In a period CP4b between timings T17b and T18b, the voltage according to the optical signal output from the pixel in the first row is used according to the capacitance ratio between the effective wiring capacitance WC1 and the clamp capacitance C0 of the vertical output lines V0b to V2b. The clamp capacitor C0 is charged.

  At timing T19b, the vertical scanning circuit block 121b deactivates the separation pulse φPVOFF1a. As a result, the separation portions MVOFF01a, MVOFF11a, and MVOFF21a provided between the first and second rows of the pixel array PA are turned off, and the effective lengths of the plurality of vertical output lines V0b to V2b are all. L3a (<L1a). Accordingly, the effective wiring capacity of the plurality of vertical output lines V0b to V2b is WC3 (<WC1).

  In a period CP5b between timings T20b to T21b, the voltage according to the noise signal output from the pixels in the second row is used according to the capacitance ratio between the effective wiring capacitance WC3 and the clamp capacitance C0 of the vertical output lines V0b to V2b. The clamp capacitor C0 is charged.

  In a period CP6b of timing T22b to T23b, depending on a voltage according to the optical signal output from the pixel in the second row, according to the capacitance ratio between the effective wiring capacitance WC3 and the clamp capacitance C0 of the vertical output lines V0b to V2b. The clamp capacitor C0 is charged.

  In a period CP7b of timing T25b to T26b, depending on the voltage according to the noise signal output from the pixel in the third row, according to the capacitance ratio between the effective wiring capacitance WC3 and the clamp capacitance C0 of the vertical output lines V0b to V2b. The clamp capacitor C0 is charged.

  In a period CP8b of timing T27b to T28b, depending on the voltage according to the optical signal output from the pixel in the third row, according to the capacitance ratio between the effective wiring capacitance WC3 and the clamp capacitance C0 of the vertical output lines V0b to V2b. The clamp capacitor C0 is charged.

  Here, the vertical output lines V0b to V2b have shorter effective lengths L3a in the read operations in the second and third rows than in the effective lengths L1a in the read operations in the zeroth and first rows. As a result, the vertical output lines V0b to V2b have a smaller wiring capacitance WC3 in the second row and third row read operations than in the second row and third row read operations WC1. As a result, compared to the period CP1 for charging the clamp capacitor C0 in the read operation of the 0th and 1st rows, the clamp capacitor C0 is charged in the 2nd and 3rd row read operations. The period CP5b and the like for this can be shortened.

  As described above, a signal can be read from the pixel array PA while reducing the effective wiring capacity of the vertical output line during the reading operation for one frame. As a result, the time for charging the clamp capacitor C0 during the reading operation for one frame can be shortened, so that the time required for the reading operation for one frame can be shortened as a whole.

  Note that the plurality of separation portions may be provided in a plurality of vertical output lines V0b to V2b other than between the first row and the second row as long as they are between the rows of the pixel array PA. The plurality of separation portions may be provided in two or more portions among the plurality of portions between the rows of the pixel array PA in each of the plurality of vertical output lines V0b to V2b.

  Next, an imaging system 20c according to a third embodiment of the present invention will be described using FIG. FIG. 6 is a configuration diagram of the imaging device 1c in the imaging system 20c according to the third embodiment of the present invention. Below, it demonstrates centering on a different part from 1st Embodiment and 2nd Embodiment, and abbreviate | omits description of the same part.

  The imaging system 20c is different from the first embodiment and the second embodiment in that an imaging apparatus 1c is provided. The imaging device 1c includes a vertical scanning circuit block 121c, a plurality of vertical output lines V0c to V2c, a plurality of separation units MVOFF0Nc, MVOFF1Nc, MVOFF2Nc, and a reading unit 30c. The imaging system 20c has a normal operation mode and a partial readout operation mode.

  The imaging device 1c performs different operations in the normal operation mode and the partial readout operation mode. The imaging device 1c performs the same operation as in the second embodiment in the normal operation mode. On the other hand, the imaging device 1c performs an operation different from the first embodiment and the second embodiment in the partial readout operation mode.

  That is, the readout unit 30c does not read out signals from the non-readout regions NR1c and NR2c of the pixel array PA in the partial readout operation mode. In the partial readout operation mode, the readout unit 30c reads out signals from the pixels in the readout region RR1c of the pixel array PA at one ends V0c1 to V2c1 of the plurality of vertical output lines V0c to V2c. The readout region RR1c is a region extending in the row direction in the pixel array PA, and is arranged side by side with the non-readout regions NR1c and NR2c. The plurality of separation portions MVOFF0Nc to MVOFF2Nc are provided between the non-read region NR1c adjacent to the read region RR1c on the side far from the one end V0c1 to V2c1 and the read region RR1c in each of the plurality of vertical output lines V0c to V2c. Yes. Accordingly, the plurality of separation units MVOFF0Nc, MVOFF1Nc, and MVOFF2Nc electrically separate the non-read region NR1c and the read unit 30c.

  Specifically, in the partial reading operation mode, the vertical scanning circuit block 121c supplies an active separation pulse φPVOFFNc to the plurality of separation units MVOFF0Nc, MVOFF1Nc, and MVOFF2Nc via the separation line PVOFFNc. As a result, the plurality of separation portions MVOFF0Nc, MVOFF1Nc, and MVOFF2Nc are turned on, and the effective lengths of the plurality of vertical output lines V0c to V2c are all L1a.

  Then, the vertical scanning circuit block 121c only counts up the row number for the non-readout region NR1c of the pixel array PA, and does not activate the pixel selection pulse corresponding thereto. Thereby, the signal is not read out by the reading unit 30c in each row of the non-reading area NR1c. That is, each row of the non-read region NR1c is skipped by the read unit 30c.

  The vertical scanning circuit block 121c makes the separation pulse φPVOFFNc non-active in response to counting up the row number up to the row closest to the reading unit 30c in the non-reading region NR1c, that is, the Nth row. As a result, the plurality of separation portions MVOFF0Nc, MVOFF1Nc, and MVOFF2Nc are turned off, and the effective lengths of the plurality of vertical output lines V0c to V2c are all LNd (<L1a). Accordingly, the effective wiring capacity of the plurality of vertical output lines V0c to V2c is WCN (<WC1).

  The vertical scanning circuit block 121c sequentially selects rows from the row farthest from one end V0c1 to V2c1 to the row closest to one end V0c1 to V2c1 in the readout region RR1c of the pixel array PA. Accordingly, the readout unit 30c reads out signals from the pixels in the readout region RR1c, which is a part of the pixel array PA, at one ends V0c1 to V2c1 of the plurality of vertical output lines V0c to V2c.

  Further, the vertical scanning circuit block 121c only counts up the row number for the non-readout region NR2c of the pixel array PA, and does not activate the pixel selection pulse for the row number. Thereby, the signal is not read out by the reading unit 30c in each row of the non-reading area NR2c. That is, each row of the non-read region NR2c is skipped by the read unit 30c.

  Here, the vertical output lines V0c to V2c are shorter in effective length LNd in the read operation of the read region RR1c in the partial read operation mode than in the effective length L1a in the read operation of the 0th row in the normal operation mode. . Thereby, the vertical output lines V0c to V2c have a smaller wiring capacitance WCN in the reading operation of the reading region RR1c in the partial reading operation mode than the wiring capacitance WC1 in the reading operation of the 0th row in the normal operation mode. As a result, in order to charge the clamp capacitor C0 in the read operation of the read region RR1c in the partial read operation mode, compared to the period for charging the clamp capacitor C0 in the read operation of the 0th row in the normal operation mode. Can be shortened.

  As described above, according to the partial operation mode, it is possible to read a signal from the pixel array PA in a state where the effective wiring capacity of the vertical output line is reduced. As a result, the time required to charge the clamp capacitor C0 can be shortened in accordance with the operation mode, so that the time required for the read operation for one frame can be shortened as a whole.

  The vertical scanning circuit block 121c may deactivate the separation pulse φPVOFFNc before counting up the row number up to the row closest to the reading unit 30c in the non-reading region NR1c, that is, the Nth row.

  Next, an imaging system 20d according to a fourth embodiment of the present invention will be described using FIG. FIG. 7 is a configuration diagram of the imaging apparatus 1d in the imaging system 20d according to the fourth embodiment of the present invention. Below, it demonstrates centering on a different part from 1st Embodiment-3rd Embodiment, and abbreviate | omits description of the same part.

  The imaging system 20d is different from the first to third embodiments in that it includes an imaging device 1d. The imaging device 1d includes a vertical scanning circuit block 121d and a plurality of vertical output lines V0d to V2d. The imaging device 1d includes a plurality of separation units MVOFF0Jd, MVOFF1Jd, MVOFF2Jd, MVOFF0Md, MVOFF1Md, MVOFF2Md, and a reading unit 30d. The plurality of separation portions MVOFF0Jd to MVOFF2Jd and MVOFF0Md to MVOFF2Md are provided for each of the plurality of vertical output lines V0d to V2d between two adjacent reading regions of the plurality of reading regions RR1d to RR3d. The imaging system 20d has a normal operation mode and a thinning operation mode.

  The imaging device 1d performs different operations in the normal operation mode and the thinning-out operation mode. The imaging device 1d performs the same operation as in the second embodiment in the normal operation mode. On the other hand, the imaging device 1d performs an operation different from that in the first to third embodiments in the thinning-out operation mode.

  That is, the readout unit 30d does not read out signals from the non-readout regions NR1d and NR2d of the pixel array PA in the thinning-out operation mode. In the thinning-out operation mode, the readout unit 30d reads out signals from the pixels in the readout regions RR1d to RR3d of the pixel array PA at one end V0d1 to V2d1 of the plurality of vertical output lines V0d to V2d. The readout regions RR1d to RR3d are regions extending in the row direction of the pixel array PA, and are arranged side by side in the column direction.

  The plurality of separation portions MVOFF0Jd to MVOFF2Md are provided in all of the plurality (one or more) of the plurality of read regions RR1d to RR3d in each of the plurality of vertical output lines V0d to V2d. Further, the plurality of separation portions MVOFF0Jd to MVOFF2Md are provided between the non-read regions NR1d and NR2d adjacent to one read region RR2d and RR3d on the side far from one end V0d1 to V2d1 and the one read region RR2d and RR3d. It has been. As a result, the plurality of separation units MVOFF0Jd to MVOFF2Md electrically separate the pixels in the readout regions RR1d and RR2d from which signals are read from the readout unit 30d, and electrically connect the non-readout regions NR1d and NR2d to the readout unit 30d. Separate.

  Specifically, in the thinning-out operation mode, the vertical scanning circuit block 121d supplies an active separation pulse φPVOFFJd to the plurality of separation units MVOFF0Jd to MVOFF2Jd via the separation line PVOFFJd. The vertical scanning circuit block 121d supplies an active separation pulse φPVOFFMd to the plurality of separation units MVOFF0Md to MVOFF2Md via the separation line PVOFFMd. As a result, the plurality of separation portions MVOFF0Jd to MVOFF2Md are turned on, and the effective lengths of the plurality of vertical output lines V0d to V2d are all L1a.

  The vertical scanning circuit block 121d sequentially selects rows from the row farthest from one end V0d1 to V2d1 to the row closest to the one end V0d1 to V2d1 in the readout region RR1d of the pixel array PA. As a result, the readout unit 30d reads out signals from the pixels in the readout region RR1d, which is a part of the pixel array PA, at one ends V0d1 to V2d1 of the plurality of vertical output lines V0d to V2d.

  Then, the vertical scanning circuit block 121d only counts up the row number for the non-readout region NR1d of the pixel array PA, and does not activate the pixel selection pulse corresponding thereto. Thereby, the signal is not read out by the readout unit 30d in each row of the non-readout region NR1d. That is, each row of the non-read region NR1d is skipped by the read unit 30d.

  The vertical scanning circuit block 121d deactivates the separation pulse φPVOFFJd in response to counting up the row number up to the row closest to the reading unit 30d in the non-readout region NR1d, that is, the Jth row. As a result, the plurality of separation portions MVOFF0Jd, MVOFF1Jd, and MVOFF2Jd are turned off, and the effective lengths of the plurality of vertical output lines V0d to V2d are all LJd (<L1a). Accordingly, the effective wiring capacity of the plurality of vertical output lines V0d to V2d is WCJ (<WC1).

  Further, the vertical scanning circuit block 121d only counts up the row number for the non-readout region NR2d of the pixel array PA, and does not activate the pixel selection pulse for the row number. Thereby, the signal is not read out by the readout unit 30d in each row of the non-readout region NR2d. That is, each row of the non-read region NR2d is skipped by the read unit 30d.

  The vertical scanning circuit block 121d deactivates the separation pulse φPVOFFMd in response to counting up the row number up to the row closest to the reading unit 30d in the non-reading region NR2d, that is, the Mth row. As a result, the plurality of separation portions MVOFF0Md, MVOFF1Md, and MVOFF2Md are turned off, and the effective lengths of the plurality of vertical output lines V0d to V2d are all LMd (<LJd). Accordingly, the effective wiring capacity of the plurality of vertical output lines V0d to V2d is WCM (<WCJ).

  Here, the vertical output lines V0d to V2d have an effective length LJd in the read operation of the read region RR2d in the thinning operation mode shorter than an effective length L1a in the read operation of the 0th row in the normal operation mode. Thereby, the vertical output lines V0d to V2d have a smaller wiring capacitance WCJ in the reading operation of the reading region RR1d in the partial reading operation mode than the wiring capacitance WC1 in the reading operation of the 0th row in the normal operation mode. As a result, the clamp capacitor C0 is charged in the read operation of the read region RR2d in the partial read operation mode as compared with the period for charging the clamp capacitor C0 in the read operation of the 0th row in the normal operation mode. Can be shortened.

  In the vertical output lines V0d to V2d, the effective length LMd in the read operation of the read region RR3d in the thinning operation mode is shorter than the effective length LJd in the read operation of the read region RR2d in the thinning operation mode. Thereby, the vertical output lines V0d to V2d have a smaller wiring capacitance WCM in the reading operation of the reading region RR3d in the thinning-out operation mode than the wiring capacitance WCJ in the reading operation of the reading region RR2d in the thinning-out operation mode. As a result, the period for charging the clamp capacitor C0 in the read operation of the read region RR3d in the thinning operation mode is shorter than the period for charging the clamp capacitor C0 in the read region RR2d in the thinning operation mode. it can.

  As described above, in accordance with the thinning mode, a signal can be read from the pixel array PA in a state where the effective wiring capacity of the vertical output line is reduced. As a result, the time required to charge the clamp capacitor C0 can be shortened in accordance with the operation mode, so that the time required for the read operation for one frame can be shortened as a whole.

  In addition, a signal can be read from the pixel array PA while reducing the effective wiring capacity of the vertical output line during the reading operation for one frame. As a result, the time for charging the clamp capacitor C0 during the reading operation for one frame can be shortened, so that the time required for the reading operation for one frame can be shortened as a whole.

1 is a configuration diagram of an imaging system 20a according to a first embodiment of the present invention. The block diagram of the imaging device 1a in 1st Embodiment of this invention. 6 is a timing chart showing the operation of the imaging apparatus 1a. The block diagram of the imaging device 1b in the imaging system 20b which concerns on 2nd Embodiment of this invention. 6 is a timing chart showing the operation of the imaging apparatus 1b. The block diagram of the imaging device 1c in the imaging system 20c which concerns on 3rd Embodiment of this invention. The block diagram of the imaging device 1d in the imaging system 20d which concerns on 4th Embodiment of this invention. The figure for demonstrating the subject of this invention. The figure for demonstrating the subject of this invention.

Explanation of symbols

1, 1a, 1b, 1c, 1d Imaging devices 20a, 20b, 20c, 20d

Claims (5)

A pixel array in which a plurality of pixels are arranged in a row direction and a column direction;
Selecting means for selecting at least one row in the pixel array;
A plurality of output lines provided in each column of the pixel array for outputting respective signals of pixels in each column in the column direction;
Reading means for reading out signals from the pixels in the row selected by the selection means in the pixel array via the plurality of output lines;
Each of the plurality of output lines includes a plurality of separation means for electrically separating between the rows of the pixel array between the rows,
The selecting means sequentially selects rows from the row farthest from the output ends of the plurality of output lines to the row closest to the output ends in the pixel array;
The image pickup apparatus characterized in that the separation means electrically separates the plurality of output lines between a row of pixels from which signals are read in the pixel array and a row of pixels that are not read out. A pixel array in which a plurality of pixels are arranged in a row direction and a column direction;
Selecting means for selecting at least one row in the pixel array;
A plurality of output lines provided in each column of the pixel array for outputting respective signals of pixels in each column in the column direction;
Reading means for reading out signals from the pixels in the row selected by the selection means in the pixel array via the plurality of output lines;
Each of the plurality of output lines comprises a plurality of separation means for electrically separating between the rows of the pixel array between at least one row,
The separating unit is configured to detect the plurality of rows in response to the signals being read from the pixels in all rows located farther from the output ends of the plurality of output lines than between the rows that are electrically separated by the separating unit. An imaging device characterized in that an output line is electrically disconnected. A pixel array in which a plurality of pixels are arranged in a row direction and a column direction;
Selecting means for selecting at least one row in the pixel array;
A plurality of output lines provided in each column of the pixel array for outputting respective signals of pixels in each column in the column direction;
Reading means for reading out signals from the pixels in the row selected by the selection means in the pixel array via the plurality of output lines;
Each of the plurality of output lines comprises a plurality of separation means for electrically separating between the rows of the pixel array between at least one row ,
Before SL plurality of disconnecting means, in the partial reading operation mode, electrically disconnecting the plurality of output lines, said selection means, the output end of said plurality of output lines than rows which are electrically disconnected by the disconnecting means An image pickup apparatus characterized by not selecting a row on the side far from. A pixel array in which a plurality of pixels are arranged in a row direction and a column direction;
Selecting means for selecting at least one row in the pixel array;
A plurality of output lines provided in each column of the pixel array for outputting respective signals of pixels in each column in the column direction;
Reading means for reading out signals from the pixels in the row selected by the selection means in the pixel array via the plurality of output lines;
An imaging apparatus comprising: a plurality of separation means for electrically separating a row of the pixel array from each other in each of the plurality of output lines for each of a plurality of rows. The imaging device has a thinning operation mode,
In the thinning-out operation mode, the selection unit sequentially selects rows from the rows far from the output ends of the plurality of output lines, every other row.
5. The imaging according to claim 4, wherein the plurality of output lines are electrically disconnected by the separation unit located on a side farther from an output end of the plurality of output lines in the row selected by the selection unit. apparatus.

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