JP3574672B2 - Sense circuit - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a sense circuit used in a semiconductor integrated circuit or the like.
[0002]
[Prior art]
For example, the EP-ROM is provided with a dummy cell having the same circuit configuration as that of the main body ROM, and a sense circuit for reading out the memory including a sense amplifier for detecting a reference level by the dummy cell and an output from the main body ROM. 2-49519 (G11C 17/18)).
[0003]
In the conventional sense circuit, one reference level is set to a substantially intermediate value between the “0” level and the “1” level in the bit line data.
[0004]
[Problems to be solved by the invention]
By the way, in order to shorten the sensing time in the sensing circuit, for example, by bringing the reference level closer to the level of "1" in the bit line data, the sensing time when the bit line data changes from "1" to "0" Can be shortened, but this increases the sensing time when the bit line data changes from “0” to “1”. Conversely, when the reference level is made closer to the level of “0” in the bit line data, the sense time when the bit line data changes from “0” to “1” becomes shorter, but the bit line data becomes “0”. The sense time when changing from "1" to "0" becomes long.
[0005]
The present invention has been made in view of the above circumstances, and has been made in consideration of the above-described circumstances. It is intended to provide a circuit.
[0006]
In order to solve the above problem, the sense circuit of the present invention sets a reference level between the level of data “0” and the level of data “1” in a bit line and performs reading of a memory device. In the sense circuit, the first sense amplifier inverts the output at a first reference level near the level of data "0" and the output is inverted at the second reference level near the level of data "1". a second sense amplifier, and an output switching unit for selecting the sense amplifier output towards which inverts earlier, of the two sense amplifier based on the output data of the two sense amplifiers in the previous sense operation, the output switching The device is disposed between the first sense amplifier and the output buffer, and a latch unit for latching the output of the sense amplifier during the previous sensing operation. 1 transfer gate, and a second transfer gate arranged between a second sense amplifier and an output buffer, wherein the latch is determined based on output data of the two sense amplifiers before a sensing operation. The transfer gate connected to the sense amplifier that operates faster by the output of the unit is turned on.
[0008]
The front Kide force selector, the next sensing operation for selecting a sense amplifier of the inverted side when the amplitude of the bit lines is not inverted only one of said two sense amplifiers in sense operation in order not sufficient but it may also be configured to.
[0009]
In addition, the first and second sense amplifiers are of a current mirror type, and the bit line side component is one, and the reference side component is two circuits for generating the first and second reference levels, respectively. It may be constituted by parts.
[0010]
[Action]
According to the first configuration, when the bit line changes from “1” to “0”, the second sense amplifier of which the second reference level closer to the level of the data “1” is set is set. When the bit line changes from “0” to “1”, the first reference level closer to the level of data “0” is set. The first sense amplifier operates faster than the second sense amplifier, and the faster one of the two sense amplifiers is selected and its output is used as a sense output. regardless ing that can be shortened sense time not. Since the output of the sense amplifier is previously connected to the output buffer through the transfer gate, the time required for output switching can be saved.
[0012]
According to the second configuration, even if only one of the sense amplifiers is inverted and then returns to its previous state again because the amplitude of the bit line is not sufficient, the sense in the state where only one of the sense amplifiers is inverted is obtained. Since the output is performed and the switching of the sense amplifier is not performed, the sensing operation when returning to the previous state is performed accurately and quickly.
[0013]
According to the third configuration, since the bit line side components of the current mirror type sense amplifier are shared, an increase in power consumption when two sense amplifiers are configured as a full set is avoided. Become.
[0014]
【Example】
Hereinafter, the present invention will be described with reference to the drawings showing the embodiments.
[0015]
FIG. 1 is a block diagram showing a schematic configuration of a sense circuit 1 of the present invention. The sense circuit 1 sets a reference level between "0" level and "1" level in bit line data and reads data from a memory device. The first sense amplifier 2 and the second sense amplifier 2 It comprises a sense amplifier 3 and an output switch 4.
[0016]
The first sense amplifier 2 is configured to invert at a first reference level (hereinafter abbreviated as ref1) near the “0” level in the bit line data. Further, the second sense amplifier 3 is configured to invert at a second reference level (hereinafter abbreviated as ref2) near the “1” level in the bit line data.
[0017]
The output switch 4 receives the output (OUT1) of the first sense amplifier 2 and the output (OUT2) of the second sense amplifier 3 and outputs both signals based on the output data of the two sense amplifiers 2 and 3 before the sensing operation. Of the sense amplifiers 2 and 3, the one that operates earlier is selected to be the sense output.
[0018]
FIG. 2 is a block diagram showing the configuration of the output switch 4 described above. The first transfer gate 5 (hereinafter abbreviated as TG5) is at the output of the first sense amplifier 2, and the second transfer gate 6 (hereinafter abbreviated as TG6) is at the output of the second sense amplifier 3. And the other end is connected to an output buffer (not shown). Further, one of these TG5 and TG6 is turned on by the output of the latch unit 7 and the inverted output by the inverter 8. Has become. Specifically, when the output (OUT) of the latch unit 7 is "0", TG5 is ON and TG6 is OFF, and when "1", TG6 is ON and TG5 is OFF. As described above, since the output of the sense amplifier is previously connected to the output buffer through the TGs 5 and 6, the time required for output switching can be saved.
[0019]
FIG. 3 is a circuit diagram showing a configuration of the latch unit 7 described above. The latch unit 7 includes a first C-MOS gate (hereinafter abbreviated as CI1) having an input unit (IN) connected to TGs 5 and 6, a first latch unit 10 connected to an output unit of CI1, and A third C-MOS gate (hereinafter abbreviated as CI3) connected to the output section of the first latch section 10, and a second latch section 11 connected to the output section of the CI3. The output (OUT) of the second latch section 11 is used as a selection signal in the TGs 2 and 3.
[0020]
The first latch unit 10 includes an inverter 10a, two NOR gates 10b and 10c, and a second C-MOS gate (hereinafter, abbreviated as CI2). The second latch section 11 includes an inverter 11a and a fourth C-MOS gate (hereinafter, abbreviated as CI4).
[0021]
Among the above CI1 to CI4, CI1 and CI4 are turned on when α is “1” and turned off when α is “0” (that is, separated from the circuit). On the other hand, CI2 and CI3 are turned on when α is “0” and turned off (that is, disconnected from the circuit) when α is “1”. The above α is the exclusive OR of OUT1 (shown as A in the figure) and OUT2 (shown as B in the figure). The circuit for generating the above α and its inverted value α ⁻¹ is not shown.
[0022]
In the two NOR gates 10b and 10c, the output of the inverter 10a is input to one input terminal of the NOR gate 10b, and the AND output (AB) of OUT1 and OUT2 is input to the other input terminal. Is done. The output of the NOR gate 10b is input to one input terminal of the NOR gate 10c, and the AND output (A ⁻¹ · B ⁻¹ ) of each inverted value of OUT1 and OUT2 is input to the other input terminal. It has become so. The circuit for generating the AND output (A · B) and the AND output (A ⁻¹ · B ⁻¹ ) of each inverted value is also not shown.
[0023]
Next, the operation of the latch unit 7 configured as described above will be described with reference to FIG.
[0024]
4A shows a change in the data level of the bit line, FIG. 4B shows a time chart of the output OUT1 of the first sense amplifier 2, and FIG. 3 shows a time chart of OUT2 which is an output of the amplifier 3, (d) shows values of α, α ⁻¹ , (A · B), and (A ⁻¹ · B ⁻¹ ), and (e) shows CI1. To the ON / OFF state of CI4, (f) shows an output state at a main point of the latch unit 7, and (g) shows which output of the sense output OUT3 is OUT1 or OUT2. That is, it indicates A or B, and (h) shows the output state of the sense output OUT3.
[0025]
(State 1)
This is a state where the bit line data is about to change from “0” level to “1” level, and both OUT1 and OUT2 are in “0” state. At this time, CI1 is OFF and disconnected from the circuit, and CI2 is ON, so that the output at point N2 is "0" and the output at point N1 is "1". Then, since CI3 is ON, N3 becomes a value “1” obtained by inverting N2, and because CI4 is turned OFF and inverted by the inverter 11a, OUT as a selection signal becomes “0”. Therefore, TG5 is selected, and the output OUT1 of the first sense amplifier 2 becomes the sense output OUT3.
[0026]
Then, when proceeding to the next state 2, OUT1 is first inverted to "1" out of OUT1 and OUT2, but as described above, the output of OUT1 is the sense output OUT3. , The sensing operation for proceeding to the next state 2 is performed earlier.
[0027]
(State 2)
When the bit line data reaches ref1, OUT1 becomes "1", and the sense output of "1" is made earlier as described above. Since the bit line data has not reached ref2, OUT2 remains "0". At this time, since CI1 is ON and CI2 is OFF, the value of IN (here, the value of OUT1) is inverted and N1 becomes “0” and N2 becomes “0”, but CI3 is turned off and CI4 is turned off. Since it is ON, the output of OUT in the previous state is maintained, and the selection signal OUT remains “0”. Therefore, TG5 remains selected, and OUT1, which is the output of the first sense amplifier 2, is continuously output as the sense output (OUT3).
[0028]
(State 3)
When the bit line data reaches ref2, OUT remains "1" and OUT2 also becomes "1". At this time, since CI1 is OFF and CI2 is ON, the output at point N2 is "1" and the output at point N1 is "0". Then, since CI3 is ON, N3 becomes a value “0” obtained by inverting N2, and because CI4 is turned OFF and inverted by the inverter 11a, the selection signal OUT becomes “1”. Therefore, TG6 is selected. At this time, since the output OUT2 of TG6 is also "1", there is no change in the sense output OUT3.
[0029]
Then, as described above, TG6 is selected and OUT2 is set as the sense output OUT3, so that the sensing operation when proceeding to the next state 4 is performed earlier.
[0030]
(State 4)
In the state 4, it is assumed that the amplitude of the bit line data is insufficient. When the bit line data reaches ref2 from the level "1", OUT2 becomes "0" and the sense output of "0" is made earlier as described above. Since the bit line data has not reached ref1, OUT1 remains “1”. At this time, since CI1 is ON and CI2 is OFF, the value of IN (here, the value of OUT2) is inverted so that N1 becomes "1" and N2 becomes "0", but CI3 is turned off and CI4 is turned off. Since it is ON, the output of OUT in the previous state is maintained, and the selection signal OUT remains "1" and TG6 remains selected. Although the selection state of TG6 does not change, the output OUT2 of TG6 is "0", so that the sense output OUT3 is "0".
[0031]
Then, as described above, since TG6 is selected and OUT2 is set as the sense output OUT3, the sensing operation when proceeding to the next state 5 is performed earlier. Further, even when the bit line level temporarily enters the middle between ref1 and ref2 due to noise or the like and returns to the original level again, the two NOR circuits 10b and 10c connected in series by the first latch unit 10 operate. Since the polarity of OUT is determined, the polarity of OUT is maintained correctly.
[0032]
(State 5)
When the bit line data reaches ref2 without reaching ref1, OUT1 is "1" and OUT2 is also "1", which is the same as the above-mentioned state 3. In this state, subsequent to State 4, OUT is "1" and TG6 is selected. Although the selection state of TG6 does not change, the output OUT2 of TG6 is "1", so that the sense output OUT3 is "1".
[0033]
Then, as described above, since TG6 is selected and OUT2 is set as the sense output OUT3, the sensing operation when proceeding to the next state 6 is performed earlier.
[0034]
(State 6)
When the bit line data reaches ref2 from the level "1", OUT2 becomes "0" and the sense output is made earlier. Since the bit line data has not reached ref1, OUT1 remains “1”. At this time, the OUT output in the previous state is maintained, OUT remains "1", and TG6 remains selected. Although the selection state of TG6 does not change, the output OUT2 of TG6 becomes "0", and the sense output OUT3 becomes "0".
[0035]
(State 7)
In state 7, the same state as state 1 described above, that is, both OUT1 and OUT2 are "0", and TG5 is selected. Although the selected state of TG is different from that of state 6, the output OUT1 of TG5 is "0", so that the sense output OUT3 remains "0".
[0036]
Then, as described above, when TG5 is selected and OUT1 is set as the sense output OUT3, the sensing operation when proceeding to the next state 8 is performed earlier.
[0037]
(State 8)
In state 8, it is assumed that the amplitude of the bit line data is insufficient when the direction changes in the direction opposite to that of the state 4 and the amplitude of the bit line data is insufficient. When the bit line data reaches ref1 from the level "0" side, OUT1 becomes "1" and the sense output of "1" is performed earlier. Since the bit line data has not reached ref2, OUT2 remains "0". Therefore, the OUT output in the previous state is maintained, and OUT remains "0" and TG5 remains selected. Although the selection state of TG5 does not change, the output OUT1 of TG5 is "1", so that the sense output OUT3 is "1".
[0038]
As described above, since TG5 is selected and OUT1 is set as the sense output OUT3, the sensing operation when proceeding to the next state 9 is performed earlier.
[0039]
(State 9)
When the bit line data reaches ref1 without reaching ref2, OUT1 is "0" and OUT2 is also "0", which is the same as the above-mentioned state 7. In this state, subsequent to State 8, OUT is "0" and TG5 is selected. Although the selection state of TG5 does not change, the output OUT1 of TG5 is "0", so that the sense output OUT3 is "0".
[0040]
As described above, since TG5 is selected and OUT1 is set as the sense output OUT3, the sensing operation when proceeding to the next state is performed quickly.
[0041]
As is apparent from the operations in the states 1 to 9 described above, when the bit line changes from "1" to "0", the second sense amplifier to which the ref2 closer to the "1" level is set. 3 operates faster than the first sense amplifier 2, and conversely, when the bit line changes from “0” to “1”, the first ref1 near the “0” level is set. Of the sense amplifier 2 operates faster than the second sense amplifier 3, and the one of the two sense amplifiers 2 and 3 that operates earlier is selected and its output is used as a sense output. The sensing time can be reduced regardless of the direction.
[0042]
Further, when the amplitude of the bit line data is insufficient, that is, when only one of the two sense amplifiers 2 and 3 is inverted as shown in the state 4 or the state 8, the sense output is performed. However, since the output is not switched, the sensing operation can be performed quickly even at the next sense inversion.
[0043]
Further, in the above embodiment, two sense amplifiers 2 and 3 having a full set configuration are used. However, as shown in FIG. 5, the sense amplifier is configured as a current mirror type current mirror type and its bit line The number of the side components 20 is one, and the reference side component is configured by a circuit portion 21 that generates a first reference level (ref1) and a circuit portion 22 that generates a second reference level (ref2). It may be. In other words, another reference-side component (22) may be added to the normal current mirror type sense amplifier configuration (20, 21).
[0044]
With this configuration, the bit line side component 20 of the current mirror type sense amplifier is shared, so that the current i of the bit line side load can be halved and the two sense amplifiers can be fully set. An increase in power consumption in a configuration is avoided.
[0045]
When the sense amplifier is configured as a voltage sensing type current mirror type, the same effect can be obtained by directly connecting the bit line and the dummy line to the gate input (indicated by point X in FIG. 5). Is obtained.
[0046]
【The invention's effect】
As described above, according to the present invention, it is possible to shorten the sensing time both when the bit line data changes from “1” to “0” and when the bit line data changes from “0” to “1”. . Also, the time required for the output switching can be saved. Further, even when the amplitude of the bit line data becomes insufficient, the reduction of the sensing time can be ensured. Further, it is possible to avoid a problem such as an increase in power consumption when a full set of sense amplifiers is provided to set two types of reference levels.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a sense circuit of the present invention.
FIG. 2 is a block diagram showing an output switch of FIG. 1;
FIG. 3 is a circuit diagram illustrating a latch unit of FIG. 2;
FIG. 4 is an explanatory diagram for explaining an operation and the like of a latch unit in FIG. 3;
FIG. 5 is a circuit diagram showing a power saving type sense amplifier that can be used in the sense circuit of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Sense circuit 2 1st sense amplifier 3 2nd sense amplifier 4 Output switcher 5 1st transfer gate 6 2nd transfer gate 7 Latch section 10 1st latch section 11 2nd latch section 20 Bit line side constituent part 21 A circuit part for generating a first reference level 22 A circuit part for generating a second reference level

Claims (3)

In a sense circuit in which a reference level is set between the level of data “0” and the level of data “1” in a bit line to perform reading of a memory device, a first level closer to the level of data “0” is provided. A first sense amplifier for inverting an output at a reference level, a second sense amplifier for inverting an output at a second reference level closer to the level of data "1", and the two senses at the time of a previous sensing operation An output switch for selecting a sense amplifier output of the two sense amplifiers that inverts earlier based on output data of the amplifier , wherein the output switcher latches a sense amplifier output at the time of a previous sensing operation. Unit, a first transfer gate disposed between the first sense amplifier and the output buffer, and a second sense amplifier. And a second transfer gate disposed between the input and output buffers, and a sense amplifier which operates faster with an output of the latch unit determined based on output data of the two sense amplifiers before a sensing operation. Characterized in that it is configured to turn on a transfer gate connected to the sensing circuit. Before Kide force selector, as the next sensing operation for selecting a sense amplifier of the inverted side when the amplitude of the bit lines is not inverted only one of said two sense amplifiers in sense operation in order not sufficient The sense circuit according to claim 1, wherein the sense circuit is configured. The first and second sense amplifiers are of the current mirror type, and the bit line side component is one, and the reference side component is two circuit portions for generating the first and second reference levels, respectively. The sense circuit according to claim 1 , wherein the sense circuit is configured.

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