JP4384792B2 - I / O circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an input / output circuit for connecting an external circuit in an integrated circuit of a microcontroller.
[0002]
[Prior art]
In general, an input / output circuit used in a microcontroller such as a microcomputer can use one external connection interface as a digital signal input or output circuit by rewriting a function setting register by a program. It can be done. In addition, there are also input / output circuits that can be used as output circuits for address signals and data signals for external buses and input circuits with pull-up as secondary functions.
[0003]
FIG. 2 is a block diagram showing an example of a conventional input / output circuit.
This input / output circuit is incorporated in an integrated circuit of a microcomputer, and includes an input / output control register 12, a secondary function control register 13, an output data register 14, a pull-up control register 15 and the like connected to the internal bus 11. It has a function setting register.
[0004]
The input / output control register 12 holds an input mode or output mode control command given via the internal bus 11 and switches input / output operations. The output data register 14 holds output data given via the internal bus 11 in the output mode. The secondary function control register 13 holds control information for switching whether to output data in the output data register 14 or to output an address signal or the like given as a secondary function in the output mode. The pull-up control register 15 holds control information indicating whether or not to pull up the input terminal in the input mode.
[0005]
The output side of the output data register 14 is connected to the first input side of the selector 16, and a secondary function output signal such as an address signal is given to the second input side of the selector 16. Yes. The selector 16 selects and outputs a signal on the first or second input side based on the control information given from the secondary function control register 13. The output side of the selector 16 is connected to an input / output terminal 18 for connecting an external circuit via an output buffer 17. The output buffer 17 amplifies the output signal of the selector 16 and drives an external circuit connected to the input / output terminal 18 when the output mode signal OUT applied from the input / output control register 12 becomes level “H”. Is. When the output mode signal OUT is at the level “L”, the output side of the output buffer 17 is in a high impedance state and is disconnected from the input / output terminal 18.
[0006]
An input side of the input buffer 19 is connected to the input / output terminal 18. The input buffer 19 outputs an input signal supplied from an external circuit to the input / output terminal 18 to the internal bus 11 when the input mode signal IN supplied from the input / output control register 12 becomes “H”. When the input mode signal IN is “L”, the output side of the input buffer 19 is in a high impedance state and is disconnected from the internal bus 11.
[0007]
The input mode signal IN output from the input / output control register 12 and the output signal of the pull-up control register 15 are supplied to the input side of a two-input negative AND gate (hereinafter referred to as “NAND”) 20. ing. The output side of the NAND 20 is connected to the gate of a P-channel MOS transistor (hereinafter referred to as “PMOS”) 21. The source of the PMOS 21 is connected to the power supply potential VDD, and the drain is connected to the input / output terminal 18.
[0008]
In such an input / output circuit, an input mode or an output circuit can be selected by setting an input mode or an output mode in the input / output control register 12 via the internal bus 11.
When the input mode is set, by further setting a control signal in the pull-up control register 15, the PMOS 21 becomes conductive and the input / output terminal 18 can be pulled up. An input signal input from the external circuit to the input / output terminal 18 is applied to the internal bus 11 via the input buffer 19.
[0009]
On the other hand, when the output mode is set, the selector 16 selects either the data stored in the output data register 14 or the secondary function output signal by further setting a control signal in the secondary function control register 13. Can be output. The output signal selected by the selector 16 is amplified by the output buffer 17 and output to the input / output terminal 18, and the external circuit connected to the input / output terminal 18 is driven.
[0010]
[Problems to be solved by the invention]
However, the conventional input / output circuit has the following problems.
FIG. 3 is a signal waveform diagram showing signal timing at the time of data writing in a static random access memory (hereinafter referred to as “SRAM”).
[0011]
As shown in FIG. 3, in the SRAM, an address signal is first given, and a strobe signal is given (set to "L") when a predetermined address sense time has elapsed and the state of the decoder in the SRAM is determined. There is a need. Further, after giving a data signal to be written, a strobe signal must be set to “H” after a predetermined data setup time has elapsed. Further, even after the strobe signal becomes “H”, the address signal must not be changed for a predetermined address hold time. In addition, the data signal should not be changed during the predetermined data hold time. If these timing conditions are not satisfied, data cannot be normally written to the SRAM.
[0012]
In the output mode of the input / output circuit of FIG. 2, if there is a mismatch in timing between the output signal and the input-side external circuit due to the external circuit connected to the input / output terminal 18 and the connection method, the external circuit can be used. It may disappear. For example, when an SRAM is connected as an external circuit, there is a problem that access is difficult unless appropriate timing conditions are established among the address signal, data signal, and strobe signal that are output signals from the input / output terminal 18. It was. Furthermore, if the capabilities of the input buffer 19 and the output buffer 17 are not consistent with the input / output conditions of the external circuit connected to the input / output terminal 18, the input / output waveform may deteriorate, leading to data errors and a decrease in data speed. There was a problem of waking up.
[0013]
The present invention solves the problems of the prior art and provides an input / output circuit capable of adjusting the timing of input / output signals and selecting input / output conditions.
[0014]
[Means for Solving the Problems]
  In order to solve the above problem,The invention according to claim 1 of the present invention is an input / output for inputting / outputting data or signals to / from an external circuit incorporated in an integrated circuit of a microcontroller and connected via an input / output terminal of the integrated circuit. The output circuit includes delay means for delaying the data or the signal output to the input / output terminal, the delay means having a plurality of delay elements connected in series, of the plurality of delay elements A plurality of delay signals delayed by a plurality of delay times using outputs of any of the plurality of delay elements, and based on control information, any one of the generated plurality of delay signals, or A signal obtained by combining any of the plurality of delay signals is output to the input / output terminal as an output signal.
[0015]
  According to a second aspect of the present invention, there is provided the input / output circuit according to the first aspect, further comprising a plurality of output buffers having different driving capacities, and the data is selected via the output buffer preselected from the output buffers. Alternatively, output means for outputting the signal to the input / output terminal is provided.
[0016]
  The invention according to claim 3 is the input / output circuit according to claim 1 or 2, further comprising a plurality of input buffers having different input characteristics, wherein the data or the signal given to the input / output terminal is input to the input / output circuit. Input means for inputting through the input buffer preselected from the buffers is provided.
[0017]
  According to a fourth aspect of the present invention, in the input / output circuit according to the third aspect, in the input mode, it is possible to selectively control whether or not the input / output terminal has a predetermined potential. .
[0018]
  The invention according to claim 5 is the delay means in the input / output circuit according to any one of claims 1 to 4, wherein the control information includes first information and second information, Based on the first information, a selection output stage that selectively outputs some of the plurality of delay signals, and a combined signal based on the signal that is selectively output from the selection output stage are generated. And a signal generation stage that outputs the output signal based on the second information, any one of the plurality of delay signals, or any combination of the plurality of delay signals. To do.
[0019]
  According to a sixth aspect of the present invention, in the input / output circuit according to the fifth aspect, the signal generation stage generates and outputs the combined signal based on the selectively output signals. And a second signal generation circuit configured to generate and output the output signal from the output of the first signal generation circuit based on the second information.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a configuration diagram of an input / output circuit showing an embodiment of the present invention. Elements common to those in FIG. 2 are denoted by common reference numerals.
This input / output circuit is incorporated in an integrated circuit such as a microcomputer. This input / output circuit includes functions of an output switching register 22 and an input switching register 23 in addition to the input / output control register 12, the secondary function control register 13, the output data register 14, and the pull-up control register 15 similar to those in FIG. Has a setting register. These registers are connected to the internal bus 11.
[0021]
The input / output control register 12 holds a control command for designating an input mode or an output mode given via the internal bus 11 and switches input / output operations. When the input mode is set in the input / output control register 12, an “H” input mode signal IN is output, and when the output mode is set, an “H” output mode signal OUT is output. Yes.
[0022]
The output data register 14 holds output data given via the internal bus 11 in the output mode. The secondary function control register 13 holds control information for switching whether to output data in the output data register 14 or to output an address signal or the like given as a secondary function in the output mode. The pull-up control register 15 holds control information indicating whether or not the input / output terminal 18 is pulled up in the input mode.
[0023]
On the other hand, the output switching register 22 holds a control signal for switching the driving capability of the output buffer. For example, when an output buffer with a high driving capability is selected, an “H” control signal is held in the output switching register 22, and when an output buffer with a low driving capability is selected, an “L” control signal is held. It has become. The input switching register 23 holds a control signal for switching the input level of the input buffer. For example, when a TTL level input buffer is selected, an “H” control signal is held in the input switching register, and when a CMOS level input buffer is selected, an “L” control signal is held. .
[0024]
The output side of the output data register 14 is connected to the first input side of the selector 16, and a secondary function output signal such as an address signal is given to the second input side of the selector 16. Yes. The selector 16 selects and outputs a signal on the first or second input side based on the control information given from the secondary function control register 13. The output side of the selector 16 is connected to the input side of the delay means (for example, delay circuit) 30.
[0025]
The delay circuit 30 delays the output signal of the selector 16 based on a control signal supplied from the internal bus 11, and the output side of the delay circuit 30 is connected to the input side of the output buffers 17a and 17b having different driving capabilities. It is connected. The output sides of the output buffers 17a and 17b are connected to an input / output terminal 18 for connecting an external circuit. The output buffers 17a and 17b both drive the external circuit connected to the input / output terminal 18 by amplifying the output signal of the delay circuit 30 when the control signal applied to the control terminal is "H". Further, when the control signal applied to the control terminals of the output buffers 17a and 17b is "L", the output side is in a high impedance state and is disconnected from the input / output terminal 18. The output buffer 17a is set to have a greater driving capability than the output buffer 17b.
[0026]
A decoder 24 is connected to the output side of the output switching register 22. The decoder 24 includes, for example, 2-input AND gates (hereinafter referred to as “AND”) 24a and 24b and an inverter 24c. When the output mode signal OUT output from the input / output control register 12 is “H”, the decoder 24 corresponds to “H” and “L” of the output signal of the output switching register 22 from the ANDs 24a and 24b, respectively. H "signal is output. The output sides of the ANDs 24a and 24b are connected to the control terminals of the output buffers 17a and 17b, respectively.
[0027]
The input side of the input buffers 19a and 19b is connected to the input / output terminal 18. The input buffers 19a and 19b output an input signal applied from an external circuit to the input / output terminal 18 to the internal bus 11 when the control signal applied to the control terminal becomes "H". When the control signal is “L”, the output side of the input buffers 19 a and 19 b is in a high impedance state and is disconnected from the internal bus 11. The input buffer 19a is a TTL level buffer, and the input buffer 19b is a CMOS level buffer.
[0028]
A decoder 25 is connected to the output side of the input switching register 23. For example, the decoder 25 includes 2-input ANDs 25a and 25b and an inverter 25c. When the input mode signal IN output from the input / output control register 12 is “H”, the decoder 25 corresponds to “H” and “L” of the output signal of the input switching register 23 to “AND” from the ANDs 25a and 25b, respectively. H "signal is output. The output sides of the ANDs 25a and 25b are connected to control terminals of the input buffers 19a and 19b, respectively.
[0029]
  The input mode signal IN output from the input / output control register 12 and the output signal of the pull-up control register 15 are supplied to the input side of the two-input NAND 20. The output side of the NAND 20 is connected to the gate of the PMOS 21. The source of the PMOS 21 is connected to the power supply potential VDD, and the drain is connected to the input / output terminal 18.The input / output control register 12, the pull-up control register 15, the NAND 20, and the PMOS 21 can be configured to selectively control whether the input / output terminal 18 is set to a predetermined potential (pull-up) in the input mode. It has become.
[0030]
  FIG. 4 is a circuit diagram showing an example of the delay circuit 30 in FIG.
  The delay circuit 30 includes a delay element 31 a to which the output signal of the selector 16 is given, a delay element 31 b connected to the subsequent stage, and a register 32 to which a control signal is set from the internal bus 11.The register 32 has output terminals A, B, and C that output first information of the control information, and an output terminal D that outputs second information of the control information.The input side and output side of the delay element 31a, and the output side of the delay element 31a are AND inputs 33a, 33b, and 33c, respectively.Selective output stage consisting ofIs connected to the first input side. The second input sides of the ANDs 33a to 33c are connected to the output terminals A, B, and C of the register 32, respectively.
[0031]
  The output side of the ANDs 33a to 33c is a three-input OR gate (hereinafter referred to as “OR”) 34, and an AND 35.First signal generation circuit comprisingIs connected to the input side. The output sides of the OR 34 and the AND 35 are connected to the first input sides of the two-input ANDs 36 and 37, respectively. The second input side of the AND 36 is connected to the output terminal D of the register 32, and the second input side of the AND 37 is connected to the output terminal D of the register 32 via the inverter 38. Further, the output sides of the ANDs 36 and 37 are connected to the input side of the two-input OR 39, and the output side of the OR 39 is connected to the input sides of the output buffers 17a and 17b.A second signal generation circuit is configured by the ANDs 36 and 37 and the OR 39, and a signal generation stage is configured by the second signal generation circuit and the first signal generation circuit.
[0032]
FIG. 5 is a signal waveform diagram for explaining the function of the delay circuit 30 of FIG.
In FIG. 4, an input signal S16 is delayed by delay elements 31a and 31b to become signals S31a and S31b, respectively. These signals S16, S31a, and S31b are transferred to bits 0 (A), 1 (B), and 2 (C) of the 4-bit control signals output from the output terminals A, B, C, and D of the register 32, respectively. It corresponds. A signal in which the corresponding bit of the control signal is set to the logical value “1” is selected by ANDs 33a to 33c, and signals S34 and S35 are output from the OR 34 and AND 35, respectively. The signals S34 and S35 are input to a selector including ANDs 36 and 37, an inverter 38, and an OR 39, and one of them is selected and output as a signal S39 according to a control signal output from the output terminal D of the register 32. .
[0033]
As shown in FIG. 5, for example, when the signal S16 rises at time t1, the signal S16 is delayed by the delay element 31a, and the signal S31a rises at time t2. Further, the signal S31a is delayed by the delay element 31b, and the signal S31b rises at time t3.
When the signal S16 falls at time t4, the signal S16 is delayed by the delay element 31a, and the signal S31a falls at time t5. Further, the signal S31a is delayed by the delay element 31b, and the signal S31b falls at time t6.
[0034]
If the set value of the register 32 is “0001”, a signal having the same timing as the signal S16 is output as the signal S39. If the setting value of the register 32 is “0010”, a signal having the same timing as the signal S31a is output as the signal S39. If the setting value of the register 32 is “0100”, the signal having the same timing as the signal S31b is output. Is output as a signal S39.
[0035]
In addition, by setting two of the bits 0 to 2 of the register 32 to “1”, a signal having a timing obtained by combining the signal S16 and the signals S31a and 31b can be output as the signal S39. For example, when the setting value of the register 32 is “0011”, a signal S39 having a width from time t1 to time t5 is obtained. If the setting value of the register 32 is “0101”, a signal S39 having a width from time t1 to t6 is obtained. If this setting value is “0110”, a signal S39 having a width from time t2 to t6 is obtained. Is obtained.
[0036]
Further, by setting bit 3 of register 32 to “1”, inverted signals of signals S16, S31a, S31b, and S39 designated by bits 0 to 2 can be obtained.
[0037]
Next, the operation of FIG. 1 will be described separately for (I) input mode and (II) output mode.
(I) Input mode
When the input mode is set in the input / output control register 12 via the internal bus 11, the input mode signal IN output from the input / output control register 12 becomes "H". On the other hand, the output mode signal OUT output from the input / output control register 12 becomes “L”, the output signals of the decoder 24 both become “L”, and the output side of the output buffers 17a and 17b enters the high impedance state. The input / output terminal 18 is disconnected.
[0038]
Further, “1” or “0” is set in the input switching register 23 based on whether the output condition of the external circuit connected to the input / output terminal 18 is TTL level or CMOS level. Here, when “1” is set in the input switching register 23, the output signal of the AND 25a of the decoder 25 becomes “H”, and the input / output terminal 18 is connected to the internal bus 11 via the TTL level input buffer 19a. On the other hand, when “0” is set in the input switching register 23, the output signal of the AND 25b of the decoder 25 becomes “H”, and the input / output terminal 18 is connected to the internal bus 11 via the CMOS level input buffer 19b.
[0039]
Further, when pulling up the input / output terminal 18, “1” is set in the pull-up control register 15. As a result, the output signal of the NAND 20 becomes “L”, the PMOS 21 is turned on, and the input / output terminal 18 is pulled up. On the other hand, when “0” is set in the pull-up control register 15, the output signal of the NAND 20 becomes “H”, the PMOS 21 is turned off, and no pull-up is performed.
[0040]
In this way, by setting the input level by the input switching register 23 and selecting one of the input buffers 19a and 19b, and setting the necessity of pull-up by the pull-up control register 15, this input / output circuit is The input circuit is set to meet the interface conditions of the external circuit. An input signal input to the input / output terminal 18 is output to the internal bus 11 via the input buffer 19a or 19b.
[0041]
(II) Output mode
When the output mode is set in the input / output control register 12 via the internal bus 11, the output mode signal OUT output from the input / output control register 12 becomes "H". On the other hand, the input mode signal IN output from the input / output control register 12 is “L”, the output signals of the decoder 25 are both “L”, and the output side of the input buffers 19a and 19b is in a high impedance state. And disconnected from the internal bus 11. Further, the output signal of the NAND 20 becomes “H”, and the PMOS 21 is turned off.
[0042]
Further, “1” or “0” is set in the output switching register 22 based on the magnitude of the load of the external circuit connected to the input / output terminal 18. Here, when “1” is set in the output switching register 22, the output signal of the AND 24 a of the decoder 24 becomes “H”, and the output side of the delay circuit 30 is connected to the input / output terminal 18 via the output buffer 17 a having high driving capability. Connected to. On the other hand, when “0” is set in the output switching register 22, the output signal of the AND 24b of the decoder 24 becomes “H”, and the output side of the delay circuit 30 is connected to the input / output terminal 18 via the output buffer 17b having a small driving capability. Connected.
[0043]
Further, a delay time is set from the internal bus 11 to the delay circuit 30, and a control signal indicating whether to output the data stored in the output data register 14 or the secondary function output signal is used as the secondary function control register. Set to 13.
As a result, the output signal selected by the selector 16 is delayed by a predetermined time by the delay circuit 30, amplified to a predetermined power by the output buffer 17 a or 17 b, and output to the input / output terminal 18. The external circuit connected to is driven.
[0044]
As described above, the input / output circuit of this embodiment has the following advantages (1) to (3).
(1) It has a delay circuit 30 capable of delaying the output timing of secondary function output signals such as address signals and output data by an arbitrary time or increasing / decreasing the time of signals to be output in the output mode. . As a result, when this input / output circuit is used as an external bus function, it becomes possible to change the output timing of the address signal, data signal, strobe signal, etc. output as the secondary function and connected to the input / output terminal 18. The timing conditions of an external circuit such as SRAM can be matched. In addition, when used as an output circuit of a clock synchronous serial port, it is possible to change the timing of a transmission clock signal and transmission data, so that transmission data setup can be performed according to the peripheral device of the external circuit that is the communication partner Time and transmission data hold time can be adjusted. Thereby, the types of external circuits that can be connected can be increased.
[0045]
(2) It has output buffers 17a and 17b having different driving capabilities, and an output switching register 22 and a decoder 24 for switching these output buffers 17a and 17b. As a result, when the output capacity of the output buffer 17b with a small capacity is insufficient due to an increase in the load capacity of the external circuit, the delay due to the dullness of the output signal can be eliminated by switching to the output buffer 17a with a large capacity. it can. The drive capability can also be changed when using the external bus function, which is a secondary function, and the synchronous serial port, so the output signal setup time can be increased by increasing or decreasing the rise time of the output signal. It is possible to adjust the hold time.
[0046]
(3) It has input buffers 19a and 19b having different input levels, and has an input switching register 23 and a decoder 25 for switching these input buffers 19a and 19b. As a result, the output conditions of the external circuit can be matched, so that the types of external circuits that can be connected can be increased. Also, the input level can be changed when using the external bus function and synchronous serial port, so the input signal setup time and hold time can be adjusted by speeding up or slowing down the input signal capture. Is possible.
[0047]
In addition, this invention is not limited to the said embodiment, A various deformation | transformation is possible. Examples of such modifications include the following (a) to (f).
(A) The configuration of the delay circuit 30 is not limited to FIG. That is, the number of delay times that can be set by increasing the number of delay elements to three or more can be increased. Thereby, the time adjustment range is widened, and the types of external circuits that can be connected can be further increased. Further, by using a counter as the delay element, the delay time can be adjusted on a clock basis.
[0048]
(B) In the delay circuit 30, the delay time setting is programmable by the register 32, but a switch for delay time setting or an external terminal may be provided in place of the register 32. Such a setting switch or the like is effective in the case of an input / output circuit that requires normal operation before initial setting at the time of power-on.
[0049]
(C) The number of selectable input buffers and output buffers is not limited to two. For example, the type of the input buffer is not limited to the one that performs level conversion such as TTL or CMOS, and a Schmitt circuit having hysteresis characteristics can also be used. By increasing the number and types of input buffers and output buffers, the types of external circuits that can be connected can be further increased.
[0050]
(D) Since the pull-up control register 15 and the output switching register 22 are not used at the same time, they can be shared. Alternatively, the input switching register 23 and the output switching register 22 may be shared.
[0051]
(E) If the output level of the external circuit is determined to be, for example, CMOS, it is not necessary to provide two types of input buffers. In that case, the input switching register 23 and the decoder 25 are unnecessary.
[0052]
(F) If it is not necessary to switch the driving capability for the external circuit, it is not necessary to provide two types of output buffers. In that case, the output switching register 22 and the decoder 24 are unnecessary.
[0053]
【The invention's effect】
  As explained in detail above,According to the first invention (inventions according to claims 1, 5 and 6), the delay means for delaying the data or signal output to the input / output terminal is provided. This delay means is configured to generate a plurality of delay signals, generate a signal combining some of these delay signals, and output this as an output signal to the input / output terminal. The output signal can be delayed by an arbitrary time, or the time of the output signal can be increased or decreased.As a result, it becomes possible to match the timing conditions of the external circuit, and an efficient input / output operation is possible by adapting to various memories and peripheral circuits having different timing conditions.
[0054]
  Second invention(Inventions according to claims 2, 5 and 6)According to the present invention, there is provided output means for outputting data or signals via an output buffer having a preselected driving capability. As a result, an output buffer suitable for the load capacity of the external circuit can be used, and an efficient input / output operation becomes possible.
[0055]
  Third invention(Invention according to claims 3 to 6)According to the above, it has an input means for inputting data or signals through an input buffer having input characteristics selected in advance. As a result, it is possible to use an input buffer that matches the output conditions of the external circuit, and it is possible to deal with various external circuits.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an input / output circuit showing an embodiment of the present invention.
FIG. 2 is a configuration diagram illustrating an example of a conventional input / output circuit.
FIG. 3 is a signal waveform diagram showing signal timing at the time of data writing in SRAM;
4 is a circuit diagram showing an example of a delay circuit 30 in FIG. 1. FIG.
5 is a signal waveform diagram for explaining the function of the delay circuit 30 of FIG. 4; FIG.
[Explanation of symbols]
11 Internal bus
12 I / O control register
13 Secondary function control register
14 Output data register
15 Pull-up control register
16 selector
17a, 17b Output buffer
18 I / O terminals
19a, 19b Input buffer
20 NAND
21 PMOS
22 Output switching register
23 Input switching register
24,25 decoder

Claims (6)

Built into the microcontroller of the integrated circuit, the input-output circuit for inputting and outputting data or signals with an external circuit connected through the input and output terminals of the integrated circuit,
A delay means for delaying the data or the signals output to the output terminal,
The delay means includes a plurality of delay elements connected in series, and a plurality of delays delayed by a plurality of delay times using outputs of any one of the plurality of delay elements. A signal is generated, and based on the control information, any one of the generated plurality of delay signals or a combination of any of the plurality of delay signals is output to the input / output terminal as an output signal An input / output circuit characterized by that. The input / output circuit according to claim 1 further includes:
A plurality of output buffers having different driving capabilities, and characterized in that the data or the signals via the preselected said output buffer from the output buffer with an output means for outputting to said input terminal Input / output circuit. The input / output circuit according to claim 1 or 2,
A plurality of input buffers having different input characteristics, further comprising input means for inputting through a preselected the input buffer from among the input buffer the data or the signals given to the input terminal An input / output circuit characterized by 4. The input / output circuit according to claim 3, wherein in the input mode, the input / output terminal is configured to selectively control whether or not the input / output terminal is set to a predetermined potential. In the delay means,
The control information includes first information and second information, and
A selective output stage for selectively outputting some of the plurality of delayed signals based on the first information;
Generate a combined signal based on the signal selectively output from the selective output stage, and based on the second information, any one of the plurality of delayed signals or any of the plurality of delayed signals A signal generation stage for outputting the output signal in combination of several;
The input / output circuit according to claim 1, comprising: The signal generation stage includes:
A first signal generation circuit for generating and outputting the combined signal based on the selectively output signal;
A second signal generation circuit that generates and outputs the output signal from the output of the first signal generation circuit based on the second information;
6. The input / output circuit according to claim 5, further comprising:

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