JP2839667B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary of the Invention] A write pulse control circuit for a semiconductor memory device is provided. In a semiconductor memory device having a memory cell connected to a line and a sense / write amplifier, one of the bit lines is connected to one of the input terminals of the amplifier during writing, and a dummy bit line to which a dummy cell for flowing a read current is connected. The switching device connects a dummy bit line to the other of the input terminals, and a write control circuit that determines the end of writing based on the output of the amplifier and generates an output for returning from the write mode to the read mode.

[Industrial applications]

The present invention relates to a write pulse control circuit for a semiconductor memory device.

In an asynchronous RAM, writing is performed by inputting a write pulse from the outside. In an external synchronous RAM, a signal pulse (clock) is input from the outside, and the R / W signal is low at the rising edge.
If so, write is performed, and a write pulse is generated internally to start a write operation. The present invention relates to means for making the width of the write pulse appropriate.

[Conventional technology]

It is difficult to set the internal write pulse width in a memory such as an external synchronous RAM that generates a write pulse internally. In consideration of the variation in the required writing time of each memory cell, the pulse width must be set large. However, if the pulse width is too large, it may interfere with the next cycle and cause erroneous writing, and it is decisive to hinder high-speed access.

The write pulse width can be set to a desired value by using a plurality of gates as gate delay elements and an OR gate, but if a high-speed gate is used as the gate, many gates are required to obtain a sufficient pulse width. I do. Power consumption cannot be ignored. However, fine adjustment of the pulse width is possible. When a low-speed gate is used, the delay time per stage is large, so that a large number of gates are not necessary to obtain a sufficient pulse width. However, if the pulse width cannot be fine-tuned and the margin is not made large, No.

[Problems to be solved by the invention]

The method of obtaining a write pulse of a desired width by using a gate as a delay element has the above-mentioned problem due to the high / low speed of the gate, and in any case, it is extremely difficult to obtain an optimum width and a necessary and sufficient pulse width.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and has as its object to optimize the write width by detecting the end of writing and terminating the writing.

[Means for solving the problem]

As shown in FIG. 1, in the present invention, a pair of bit lines BL,
A dummy bit line DBL connected to a dummy cell DMC is provided in a semiconductor memory device including the memory cells MC _{1 to} MC _n connected to に and the sense / write amplifier SWA. A read (read) current of the memory cell is supplied to the dummy cell.

Also provided switchgear SW ₁ to SW _3, these switchgear, write (write) and sometimes a sense / write amplifier SWA
One of the bit line pairs, for example, BL, is connected to one of the input terminals of
The other of the input terminals is the other of the pair of bit lines.
From the dummy bit line DBL.

Further, a write control circuit WCNT is provided to determine the end of writing based on the output of the amplifier SWA whose connection has been switched as described above, and to output a signal WST indicating that.

Although a semiconductor memory device is provided with a number of bit line pairs and word lines, FIG. 1 shows only one bit line pair. OT
B is an output buffer for outputting read data to the outside. L ₃ and L ₄ are data output buses.

[Action]

The memory cell MC (subscripts 1,... N for distinguishing each other) is provided with a pair of transistors, one being on and the other being off, or vice versa. When a memory cell is selected, a current (read current) flows through the on-side transistor. This is shown in FIG.

Memory cell is constituted by nMOS transistors N ₃ to N ₆ and the resistor R _5, R ₆ as shown in example FIG. 3 (d), N N ₃ is on
_{When 4} is off or vice versa, data 1 and 0 are stored. Word lines WL transistor N ₅ and becomes H level, N ₆ is turned on when the memory cell MC is the bit line BL, ▲ is connected to ▼, as shown in Figure 3 if N ₄ is on (a) ▲ The lead I _R flows from ▼ to N ₄ .

Writing means inverting the on and off states of N ₃ and N _{4. As} shown in FIG. 3 (b), this means that the CMOS inverters P ₁ and N ₁ for driving the bit lines have H level, and An L level signal (write data) is applied to P ₂ and N ₂ . This pMOS transistor P ₁ turns off, nMOS transistor N ₁ is turned on, also pMOS transistor P ₂ is turned on, nMOS transistor N ₂ is (becomes never change in this example) turns off. P ₁ off, N ₁ on
BL becomes L level, N ₄ is turned off, N ₃ is turned on in this as is clear from FIG. 3 (d). This is shown in FIG. 3 (c).

Transistor N ₃ is turned on, the N ₄ is turned off, the bit line ▲
The read current I _R flowing in ▼ disappears. Since I _R voltage drop is not caused by the transistor P ₂ becomes zero bit line ▲ ▼ becomes H level. Bit line H in a state in which read current I _R is the voltage drop due to the transistor P ₂ flows
The level is represented here by H '. Of course, H> H '.

As described above, the read current I _R disappears at the end of the write, and the H ′ level of the bit line changes to the H level, so that the end of the write can be known from this. Write control circuit of FIG.
WCNT detects this and outputs a signal WST indicating the end of writing.

As described above, according to the present invention, the end of writing is detected and the mode is returned from the writing mode to the reading mode. Therefore, a necessary and sufficient writing period can be provided irrespective of variation in characteristics of memory cells and the like, and the writing performance of the memory is maximized. Limit can be increased.

The writing of the same data, Figure 3 on already N ₄ is on if example, to turn off the N ₃ is off (i.e. do nothing). In this case, the CMOS inverter shown in Fig. 3 (b)
An L level is applied to P ₁ and N ₁ and an H level is applied to P ₂ and N ₂ . with this
BL becomes H, ▲ ▼ becomes L, and I _R disappears immediately. Therefore, the write control circuit WCNT immediately generates the output WST. Thus, according to the present invention, substantially no writing is performed when the same data is written.

〔Example〕

FIG. 2 shows an embodiment of the present invention. Bit line BL, ▲
▼ CMOS inverter for driving pMOS transistor M ₃ and M _4, n
Is composed of MOS transistors M _5, M _6, the gate of these transistors are connected to the data input bus L _1, L _2. These are write amplifiers, and the sense amplifier is indicated by PSA (pre-sense amplifier). The switch SW 1 in FIG. ₁ is a pMOS
The switches SW ₂ and SW ₃ are composed of transistors M ₄ and M ₃ , respectively, with the transistors M ₁ and M ₇ , and M ₂ and M ₈ . The write control circuit WCNT is not shown in FIG.

When writing data, set L according to write data 1,0.
_One of L ₁ and L ₂ becomes H and the other becomes L. L ₁ in this example is L, L ₂
Is H. The read / write control line RWC is set to L. Therefore, the transistors M ₁ and M ₂ are turned on, and when L ₁ = L, M
₆ off, M ₄ ON, M ₇ on and M ₃ off L ₂ = H, M ₅ on, the M ₈ off. With this, the input terminal on the left side of the drawing of the sense amplifier PSA is connected to the dummy bit line DBL through M ₁ and M ₇ ,
The input terminal on the right side is disconnected from the bit line BL, and is disconnected from the DBL.

Since the dummy cell DMC flows the same current as the read current I _R , the left input terminal of the PSA goes to H ′ level. Memory cell M
When the transistor on the right side of C is on and a read current is flowing through the bit line ▲ ▼, the potential of ▲ ▼ is H ′ and PS
Both inputs of A are at the same level and the PSA produces no output (since the PSA is a current switch, both transistors carry the same current). Since BL becomes L at M ₅ on, on the memory cell MC, and the inversion of the off occurs, the left transistor is turned on, the right transistor is turned off. This changes ▲ to H and PSA produces an output (one transistor is on,
On the other hand, the transistor is turned off, a current flows to one of L ₃ and L ₄ ,
No current flows to the other). Write control circuit WC in FIG.
The NT detects this, and changes the signal WST, which has been at the L level, to the H level (and vice versa), thereby notifying the amplifier SWA of the end of writing.

Data input bus L ₁ is L, L ₂ is H, in the present example the left cell MC is turned on, corresponds to the right side off. Similarly, L ₁ =
H, L ₂ = L indicates that the right side of the cell MC is on and the left side is off. At the time of writing, the on-side bit line is connected to PSA.

FIG. 4 shows the configuration of the semiconductor memory device. Cell array MC
Row decoder RD and row address buffer R for A
There is an AB, which selects a word line of a cell array according to an address signal. Column address buffer CAB,
There is a column decoder CD, which selects a bit line of a cell array according to an address signal. The sense amplifier amplifies the read data of the cell array and outputs it to the outside via the output buffer OTB. The write amplifier performs H and L control of the bit line pair according to the write data.

FIG. 5 shows a configuration example of the write control circuit WCNT. As shown, this is a differential amplifier DAMP, comparators COMP _{1 to} COM
Consisting of P _3.

The outputs of the data output buses L ₃ and L ₄ are input to the differential amplifier DAMP, and this output is compared with the signals D _IN and ▲ ▼ from the data input by the comparators COMP ₁ and COMP ₂ . When they match, COMP ₁ and COMP ₂ output L level, and at the time of writing, the write enable WE is H, so that the output of the comparator COMP ₃ , that is, WST, which has been L level until now, becomes H level. . This WST = L indicates the end of writing. W when reading
E is L, so the output WST of COMP ₃ is H. Signal W
ST is in the write data output bus L _3, the signal D _IN from the output and the data input of L _4, only when the ▲ ▼ do not match,
It becomes L level.

〔The invention's effect〕

As described above, according to the present invention, the write width can be optimized in the external synchronous RAM, and the high-speed write can be performed as much as possible. Unlike the method of determining the write pulse width by using the gate as a delay element, there is no need to worry about gate selection or the like.

[Brief description of the drawings]

1 is a principle diagram of the present invention, FIG. 2 is a main part circuit diagram showing an embodiment of the present invention, FIG. 3 is an operation explanatory diagram, and FIG. 4 is a block diagram showing a configuration of a memory. FIG. 5 is a circuit diagram showing a configuration example of a write control circuit. BL in Figure 1, ▲ ▼ a pair of bit lines, MC is a memory cell, SWA sense amplifier and the write amplifier, DBL dummy bit line, SW ₁ to SW ₃ are switchgear, WCNT is a write control circuit.

Claims (1)

(57) [Claims] 1. A semiconductor memory device comprising a memory cell connected to a pair of bit lines (BL, ▲ ▼) and a sense / write amplifier (SWA), a dummy bit line connected to a dummy cell for passing a read current, write to, connect one of the bit lines to one input terminal of the amplifier, switchgear for connecting dummy bit lines to the other of the input and (SW ₁ ~SW _3), the write end by the output of said amplifier A semiconductor memory device comprising: a write control circuit (WCNT) for generating an output for determining and returning from the write mode to the read mode.