JP3562715B2 - Clock recovery circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a clock recovery circuit for extracting a clock from a serial data signal, and more particularly to a clock recovery circuit for realizing an optical receiver whose pull-in range, jitter characteristics and the like do not depend on a data pattern of an input signal.
[0002]
[Prior art]
FIG. 8 is a diagram showing an example of a conventional clock recovery circuit (reference: CRHogge, JR., “A Self Correcting Clock Recovery Circuit”, Journal of Lightwave Tech., Vol. LT-3, No. 6 1985). , p1323).
[0003]
The conventional clock recovery circuit includes a phase comparator 2, a loop filter 3, a voltage controlled oscillator (hereinafter abbreviated as VCO) 4, and an adder 19. The phase comparator 2 has a function of outputting a signal including a DC voltage component proportional to the phase difference. Although many configurations have been proposed for the phase comparator, the configuration in FIG. 8 is the most widely known.
[0004]
The input data Din is input to a D-type flip-flop (hereinafter abbreviated as D-FF) 9 via the data input terminal 1. The output signal of the VCO 4 triggers the D-FF 9 via the buffer 6. As a result, a signal in which the input data Din is retimed by the clock CLK appears at the output of the D-FF 9. Din and the retimed signal are connected to the input of an exclusive OR gate (hereinafter abbreviated as EXOR) 13. The EXOR 13 has a signal (phase comparison signal 15) V having a pulse width proportional to the phase difference between Din and CLK._PWill be output. Note that the EXOR 13 outputs a pulse only when an edge (transition from high level to low level or transition from low level to high level) occurs in the input signal._PHas a DC component proportional to not only the phase difference but also the edge density.
[0005]
The phase difference between Din and CLK when the rising edge of CLK coincides with the edge of Din as a reference (zero) is φ (radian), the edge density coefficient of input signal Din (the number of edges of input data Din / clock) If the number of edges of CLK is DF, the phase comparison signal V_PDC component of the high-level and low-level difference voltage as a unit voltage,
V_P= Φ · DF (1)
Is represented as Here, 0 <φ <2π and 0 <DF <0.5.
[0006]
On the other hand, the signal retimed by the D-FF 9 is also input to the D-FF 10 and re-timed again by the inverted CLK output of the buffer 6. The output of D-FF 9 and the output of D-FF 10 are connected to the input of EXOR 14. Since the two signals input to the EXOR 14 are both retimed by the output of the VCO 4, the output (edge density signal 16) of the EXOR 14_EIs constant (half the clock cycle if the duty of CLK is exactly 50%) regardless of the phase difference between Din and CLK.
[0007]
Since the EXOR 14 outputs a pulse only when an edge occurs in the input signal, similarly to the EXOR 13, the EXOR 14 outputs a pulse._EHas a DC component proportional to the edge density. If the duty of CLK is exactly 50%, the edge density signal V_EThe DC component of
V_E= Π · DF (2)
Is represented as The adder 19 outputs the phase comparison signal V_PAnd edge density signal V_EAnd outputs the difference voltage. From the equations (1) and (2), the output V of the adder 19 is obtained._PEThe DC component of
V_PE= (Φ-π) · DF (3)
Is represented as Output V of adder 19_PEIs transmitted to the VCO 4 after the band is limited by passing through the loop filter 3. The output of the VCO 4 is connected to the clock output terminal 5 and returned to the phase comparator 2 at the same time, whereby the phase synchronization is established between Din and CLK.
[0008]
In the locked state, the VCO 4 oscillates at a substantially constant frequency, so that the output V_PEIs substantially constant (Equation (3)). When the edge density coefficient DF changes under these conditions, V_PEIs changed so that is kept constant, and the locked state is maintained. That is, φ is modulated by the DF. The only case where φ is not affected by DF is when φ = π. When the lock state is realized when φ = π, φ does not change its value even if DF changes.
[0009]
When retimed data is required, the output of the D-FF 9 or the output of the D-FF 10 may be used. In FIG. 8, the output of the D-FF 10 is set to Dout, connected to the data output terminal 34, and transmitted to the outside.
[0010]
FIG. 9 is a waveform diagram showing the operation of the conventional clock recovery circuit. The Din signal shown in (a) given to the input terminal 1 is retimed by the D-FF 9 by the CLK signal shown in (b) to obtain a signal 11 shown in (c), and the Din signal shown in (a) is retimed. The EXOR 13 uses the phase comparison signal 15 (= V) shown in FIG._P) Is obtained. Further, the signal 11 shown in (c), which has been retimed, is further retimed by the D-FF 10 by the inverted CLK signal shown in (d) to obtain a signal 12 shown in (e). The edge density signal 16 (= V) shown in FIG._E) Is obtained. The difference between the phase comparison signal shown in (f) and the edge density signal shown in (g) (= V_P-V_E) Is the output 17 (= V) shown in (h) of the adder 19._PE).
[0011]
FIG. 9I shows the operation when the phase of the CLK signal is ahead of the Din signal (0 <φ <π), and the pulse width of the phase comparison signal (f) is the pulse of the edge density signal (g). Shorter than the width, the output V of the adder 19_PEIs negative. FIG. 9 (III) shows the operation when the phase of the CLK signal lags behind the Din signal (π <φ <2π), and the pulse width of the phase comparison signal (f) is the pulse of the edge density signal (g). Longer than the width, the output V of the adder 19_PEIs positive. FIG. 9 (II) shows the operation when the phase relationship between the CLK signal and the Din signal is optimal (φ = π).
[0012]
The optimal phase relationship is a phase relationship in which the D-FF 9 punches out the center of the Din signal at the rising edge of the CLK signal, and has the largest phase margin for the D-FF 9. In this case, the pulse width of the phase comparison signal (f) matches the pulse width of the edge density signal (g), and the DC component of the output of the adder 19 becomes zero. This is consistent with the result of φ = π in equation (3).
[0013]
FIG. 10 shows the phase comparison characteristic of the phase comparator 2 (the phase difference φ of Din-CLK and the output V of the adder 19)._PERelationship with the average voltage). The case where the edge density coefficient DF of the input data Din is 0.5 and 0.25 is shown. The maximum value of DF is DF = 0.5 when Din is a 0/1 alternating signal, and DF <0.5 in the case of a PN (pseudo noise) signal or normal data transmission.
[0014]
As described above, the output V of the adder 19 during the operation of the clock recovery circuit (when locked)._PEIs kept substantially constant, so that if the value of DF changes during operation, the phase difference φ of Din-CLK is affected and changes. At this time, the degree of the influence depends on the value of the phase difference φ of Din-CLK itself. As shown in (II), when φ is close to π, φ is hardly affected by a change in the value of DF, and is not affected when φ is π. On the other hand, if φ greatly deviates from π, it will be greatly affected. That is, the optimum point (II) of the phase relationship of Din-CLK is optimal in the sense that the phase margin of Din punching by CLK in the D-FF 9 is the largest, and in addition, φ is the only point that is not affected by DF. It can also be said that the phase relationship is optimal. The output V of the adder 19_PEIs not affected by the DF only at the optimum point (II).
[0015]
FIG. 11 shows the free running frequency of the VCO 4 and the output V of the adder 19._PEFIG. 4 is a diagram showing a relationship with an average voltage. The slope in the locked state is negative, but this is because the output V of the adder 19 becomes higher when the free-running frequency shifts to a higher direction for the same bit rate._PEMean that the locked state is maintained. As described above, the output V of the adder 19 which is not affected by the DF_PESince the average voltage of the VCO 4 exists only at the point (optimum point (II)), the free-running frequency of the VCO 4 not affected by the DF also exists only at the point (the center of the lock range).
[0016]
[Problems to be solved by the invention]
As described above, in the conventional clock recovery circuit shown in FIG. 8, the free-running frequency of the VCO 4 whose phase comparison characteristic is not affected by the DF exists only at points. Consider a case where the free-running frequency of the VCO 4 becomes higher (I) than the optimum point (II) (FIG. 11). Then, the output V of the adder 19_PEThe average voltage is maintained in synchronization by lowering its value. As a result, as shown as (I) in FIG. 10, the phase difference φ of Din-CLK greatly changes depending on the value of DF. This means that the punch timing of the D-FF 9 and D-FF 10 is greatly modulated by the DF.
[0017]
As a result, in addition to the phase of the reproduced clock Cout being modulated by the DF, the phase of the retimed reproduced data Dout is similarly modulated by the DF. When the DF modulates the phase of Cout or the phase of Dout in this way, it causes problems such as new generation of jitter and reduction in tolerance to jitter contained in the input data Din. Further, since the lock range and the pull-in range shift due to the difference in the DF, a sufficient pull-in range can be obtained only for a specific range of the DF.
[0018]
In order to avoid the above problem, it is necessary to adjust the free-running frequency of the VCO 4 to an optimum point, and the free-running frequency of the VCO 4 changes over time and changes in the environment (temperature change, power supply voltage change, input data amplitude, etc.). Etc.) must be provided with compensation means. However, individual adjustment at the time of shipment of the VCO requires enormous operation, and it is practically difficult to compensate for aging of the free-running frequency of the VCO 4.
[0019]
Further, even when the free-running frequency of the VCO 4 is adjusted to the optimum point, the fact that the phase comparison characteristic has the DF dependence as shown in FIG. Means having Since the loop gain greatly affects jitter characteristics such as jitter transmission, it is necessary to design the loop gain to an optimum value to satisfy system requirements. If the loop gain optimization design is performed for a specific DF, the loop gain for another DF value will deviate from the optimal value, and if data with a DF outside the specific range is input, the jitter characteristics will be reduced. There is a possibility that the system requirements cannot be satisfied.
[0020]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a clock recovery circuit in which a phase comparison characteristic is not affected by an input data pattern and performance degradation due to a change in an edge density coefficient can be suppressed.
[0021]
[Means for Solving the Problems]
Delete
[0022]
Delete
[0023]
For this reason1The invention relates to a voltage controlled oscillator whose oscillation frequency is controlled by a voltage, and a phase comparison including a DC voltage component proportional to the phase difference by detecting a phase difference between an output signal of the voltage controlled oscillator and an input signal from an input terminal. Signal V_PAnd an edge density signal V including a DC voltage component proportional to the edge density._EAnd an edge density signal V output when an input signal having an edge density serving as a reference for the phase comparator is input._EReference edge density signal V having the same DC component as_E0, And α is an arbitrary constant, and the phase comparison signal V_PAnd the edge density signal V_EAnd the reference edge density signal V_E0And α (V_P-V_E) (V_E0/ V_E), And a loop filter that extracts a component below a predetermined band from the output signal of the arithmetic circuit and applies it as a control voltage to the voltage-controlled oscillator. Was obtained.
[0024]
No.2The invention of the1In the invention, the arithmetic circuit includes: a resistor group for determining the α;_P-V_E) (V_E0/ V_E), And a differential amplifier and a multiplier for performing the operation of (1).
[0025]
Delete
[0026]
Delete
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
The most important feature of the clock recovery circuit according to the present invention is that an adder that performs subtraction in a conventional clock recovery circuit is replaced with an arithmetic circuit including division. In the conventional clock recovery circuit, the phase comparison signal V_PAnd edge density signal V_E, The output V of the adder 19 is calculated._PEIn the clock recovery circuit of the present invention, the phase comparison signal V_PAnd edge density signal V_EThe difference is that the edge density information is completely canceled at the output of the arithmetic circuit and only the phase comparison information is extracted.
[0028]
In the conventional clock recovery circuit, the edge density information can be completely canceled only when the phase difference φ of Din-CLK is π, whereas when φ deviates from π, the output V of the adder 19 becomes smaller._PEThe edge density coefficient DF leaks. Such a leak of the edge density coefficient DF causes a change in the lock range and the pull-in range due to a change in the edge density coefficient DF (a change in the data pattern), generation of jitter, and deterioration of jitter tolerance. The present invention has been made in order to suppress the performance degradation due to such a change in the edge density coefficient DF. The edge density coefficient does not leak to the output of the circuit.
[0029]
[First reference example]
FIG. 1 shows the present invention.First reference example3 is a diagram showing a clock recovery circuit of FIG. BookReference exampleIs composed of a phase comparator 2, a loop filter 3, a VCO 4, and an arithmetic circuit 20a. The phase comparator 2 has a function of outputting a signal including a DC voltage component proportional to the phase difference. The input data Din is input to the D-FF 9 via the data input terminal 1. The output signal of the VCO 4 triggers the D-FF 9 via the buffer 6.
[0030]
As a result, a signal in which the input data Din is retimed by the clock CLK appears at the output of the D-FF 9. Din and the retimed signal are connected to the EXOR 13 input. The EXOR 13 has a signal (phase comparison signal 15) V having a pulse width proportional to the phase difference between Din and CLK._PWill be output. As described above, the phase difference between Din and CLK is φ (radian) when the phase relationship where the rising edge of CLK coincides with the edge of Din is defined as a reference (zero), and the edge density coefficient of the input signal (input data Din DF is the number of edges of the clock CLK / the number of edges of the clock CLK)._PIs represented by the aforementioned equation (1).
[0031]
On the other hand, the signal retimed by the D-FF 9 is also input to the D-FF 10 and re-timed again by the inverted CLK output of the buffer 6. The output of D-FF 9 and the output of D-FF 10 are connected to the input of EXOR 14. Since the two signals input to the EXOR 14 are both retimed by the output of the VCO 4, the output (edge density signal 16) of the EXOR 14_EIs constant (half the clock cycle if the duty of CLK is exactly 50%) regardless of the phase difference between Din and CLK.
[0032]
Since the EXOR 14 outputs a pulse only when an edge occurs in the input signal, similarly to the EXOR 13, the EXOR 14 outputs a pulse._EHas a DC component proportional to the edge density. If the duty of CLK is exactly 50%, the edge density signal V_EIs represented by the above-mentioned equation (2).
[0033]
The arithmetic circuit 20a calculates the phase comparison signal V of the phase comparator 2._PAnd edge density signal V_EAnd enter
V_PE= Α (V_P-V_E) / V_E                                (4)
A signal V having a DC component represented by_PEIs output. Here, α is an arbitrary constant. Phase comparison signal V_PIs given by the above equation (1), and the edge density signal V_EIs represented by the above equation (2), and when these are substituted, equation (4) becomes
V_PE= (Α / π) (φ-π) (5)
Is represented by
[0034]
As described above, in the conventional clock recovery circuit, the output V of the adder 19 is_PEContains the edge density coefficient DF (Equation (3)), so that when the phase difference φ deviates from π, the phase comparison characteristic is affected by the DF. Such a leak of the edge density information causes a change in the lock range and the pull-in range due to a change in the edge density coefficient DF (a change in the data pattern), generation of jitter, and deterioration of jitter tolerance.
[0035]
In contrast, the bookReference exampleOutput V of the arithmetic circuit 20a_PEDoes not include the DF (Equation (5)), so that the phase comparison characteristic is not affected by the DF even when the phase difference φ takes any value from 0 to 2π. Therefore, the output V of the arithmetic circuit 20a_PESince there is no leak of edge density information, changes in the lock range and the pull-in range due to changes in the edge density coefficient DF (changes in the data pattern) are suppressed, and it is possible to prevent jitter generation and jitter tolerance deterioration.
[0036]
FIG. 2 shows the phase comparison characteristic of the phase comparator 2 (the phase difference φ of Din-CLK and the output V of the arithmetic circuit 20a)._PERelationship with the average voltage). The case where the edge density coefficient (DF) of the input data Din is 0.5 and 0.25 is shown. During the operation of the clock recovery circuit (at the time of locking), the average voltage of the output of the arithmetic circuit 20a is kept substantially constant. When it changes, the phase difference φ of Din-CLK is affected and changes its value. The larger φ deviated from π, the greater the influence. On the other hand, in the clock recovery circuit of the present embodiment, even when the value of DF changes during operation, the phase difference φ of Din-CLK is constant without being affected, and φ greatly deviates from π. Even if the clock recovery circuit keeps the synchronization state, there is no influence.
[0037]
That is, in the conventional clock recovery circuit, it is necessary to precisely adjust the free-running frequency of the VCO 4 so that φ takes a value close to π, and suppress a temperature change, a secular change, and a power supply voltage fluctuation that causes the free-running frequency to drift. I needed a bookReference exampleClock recovery circuit does not cause performance degradation even if φ deviates from π, so it is not necessary to adjust the free-running frequency of VCO4 precisely. Even so, it is possible to relax the allowable range.
[0038]
FIG.First reference exampleOf the arithmetic circuit 20a in FIG. The arithmetic circuit 20b in FIG. 3 includes a differential amplifier 51, a multiplier 52, resistors 53 and 54 having a resistance value R1, and resistors 55 and 56 having a resistance value R2. Hereinafter, the input / output relationship of the arithmetic circuit 20b, that is, the phase comparison signal V_P, Edge density signal V_E, The output V of the arithmetic circuit 20b_PEThe relationship will be described.
[0039]
Assuming that the proportional coefficient is K (arbitrary constant), the output V of the multiplier 52_MIs
V_M= KV_PE・ V_E                                       (6)
Is represented by On the other hand, the voltage V of the positive input terminal (+) of the differential amplifier 5l_INPIs obtained by voltage division of the resistor 54 and the resistor 56.
V_INP= (V_E−0) (R2 / (R1 + R2)) + 0 (7)
Given by Further, the voltage V of the negative input terminal (-) of the differential amplifier 5l_INMIs obtained by voltage division of the resistor 53 and the resistor 55.
V_INM= (V_P-V_M) (R2 / (R1 + R2)) + V_M               (8)
Given by Assuming that the gain of the differential amplifier 51 is sufficiently large, the nature of a virtual short appears between the inputs of the closed-loop differential amplifier,
V_INP= V_INM                                             (9)
It becomes. Therefore, according to equations (7), (8), and (9), the output V_MIs
V_M=-(R2 / R1) (V_P-V_E) (10)
Is represented by Equations (6) and (10) represent the voltage at the same node and therefore need to match. From this condition, the output V of the arithmetic circuit 20b_PEIs
V_PE=-(R2 / R1) (1 / K) (V_P-V_E) / V_E             (11)
Given by
[0040]
Output V of arithmetic circuit 20b given by equation (11)_PEIs equivalent to equation (4) if α = − (R2 / R1) (1 / K) is defined. That is, the arithmetic circuit 20b shown in FIG.First reference exampleIs one of the implementation examples of the arithmetic circuit 20a. Here, although the sign of α is negative in the above example, it changes depending on the polarity of the connection of the multiplier 52 and the differential amplifier 51, the modulation polarity of the VCO 4, and the like. What is necessary is just to select the polarity which establishes phase synchronization.
[0041]
Note that the configuration of the phase comparator 2 is not limited to the configuration of FIG. That is, the D-FF 10 can be realized by a delay circuit (refer to CRHogge, JR., "A Self Correcting Clock Recovery Circuit", Journal of Lightwave Tech., Vol. LT-3, no. 6, 1985, p1323), and Din may be directly input to the delay circuit instead of the output of the D-FF 9. Further, the EXOR 13 and the EXOR 14 are changed to AND gates 35 and 36 (reference: JP-A-2000-68991), and the phase comparator 40 (FIG. 12) in which the buffer 39 is added can be used as the phase comparator of the present invention. Similar effects can be obtained. That is, the clock recovery circuit using the phase comparator 40 shown in FIG. 12 also has a problem that the free-running frequency of the VCO 4 whose phase comparison characteristic is not affected by the DF exists only at a point. ToFirst reference exampleBy applying the phase comparator 2 as the phase comparator 2, it is possible to realize a phase comparison characteristic that is not affected by the DF.
[0042]
[No.1Embodiment]
FIG. 4 shows a second embodiment of the present invention.1FIG. 3 is a diagram illustrating a clock recovery circuit according to the embodiment. This embodiment includes a phase comparator 2, a loop filter 3, a VCO 4, an arithmetic circuit 21a, and a reference voltage generator 57a.First reference exampleThe difference between this is that a reference voltage generator 57a is newly provided and the output V_E0Is input to the arithmetic circuit 21a.
[0043]
The arithmetic circuit 21a calculates the phase comparison signal V of the phase comparator 2_PAnd edge density signal V_EAnd enter
V_PE= Α (V_P-V_E) (V_E0/ V_E) (12)
A signal V having a DC component represented by_PEIs output. Here, α is an arbitrary constant. Also, V_E0Is an output of the reference voltage generator 57a, and when an edge density coefficient DF (for example, DF = 0.5) as a reference, the edge density signal V_EIs a signal having the same DC component as the DC component included in. That is, the reference edge density coefficient is DF = DF₀Then, the output of the reference voltage generator 57a is obtained from the above equation (2).
V_EO= ΠDF₀                                        (13)
Is represented by Phase comparison signal V_PIs expressed by the above equation (1), and the edge density signal V_EIs given by the above equation (2), and using these and equation (13), equation (12) gives the phase difference φ and the reference edge density coefficient DF.₀As a function of
V_PE= (Α ・ DF₀) (φ-π) (14)
Is represented by
[0044]
As described above, the output V of the arithmetic circuit 21a of the present embodiment is_PEDoes not include the DF (Equation (14)), so that the phase comparison characteristic is not affected by the DF even when the phase difference φ takes any value from 0 to 2π. The present invention1The phase comparison characteristic of the embodimentFirst reference exampleOf the same shape as the phase comparison characteristic (FIG. 2). Therefore, the output V of the arithmetic circuit 21a_PESince there is no leak of edge density information, changes in the lock range and the pull-in range due to changes in the edge density coefficient DF (changes in the data pattern) are suppressed, and it is possible to prevent jitter generation and jitter tolerance deterioration.
[0045]
FIG. 5 shows a second embodiment of the present invention.1This provides an arithmetic circuit 21b and a reference voltage generator 57b that embody the arithmetic circuit 21a and the reference voltage generator 57a in the embodiment. 5 includes a differential amplifier 58, a multiplier 64, resistors 60 and 61 having a resistance value R1, and resistors 62 and 63 having a resistance value R2. The arithmetic circuit 21b of the present embodiment has a firstReference exampleIs different from the arithmetic circuit 20b (FIG. 3) in that a multiplier 64 is added. When the addition of the multiplier 64 is reflected in the equation (11), the output V_PEIs
V_PE=-(R2 / Rl) (Kb / Ka) (V_P-V_E) (V_E0/ V_E) (15)
It can be seen that Here, the coefficient of the multiplier 59 is Ka, and the coefficient of the multiplier 64 is Kb. The output V of the arithmetic circuit 21b given by the equation (15)_PEIs equivalent to equation (12) if α = − (R2 / R1) (Kb / Ka) is defined. That is, the arithmetic circuit 21b shown in FIG.1This is one of the implementation examples of the arithmetic circuit 21a in the embodiment.
[0046]
The reference voltage generator 57b in FIG. 5 includes a frequency divider 70, a delay circuit 71, and an EXOR 72. Reference edge density coefficient DF₀Is described as an example. In this case, the frequency division ratio of the frequency divider 70 may be set to 1/2, and the delay time of the delay circuit 71 may be selected to be 1/2 of the clock cycle. In this case, the output signal of the frequency divider 70 becomes 0/1 alternating signal data (DF = 0.5), and the EXOR 72 outputs the edge density signal V output by the EXOR 14 when Din is the 0/1 alternating signal._EAnd outputs a signal equivalent to. Also, the reference edge density coefficient DF₀Is set to 0.25, the frequency division ratio of the frequency divider 70 may be set to 1/4, and the delay time of the delay circuit 71 may be selected to be 1/2 of the clock cycle. In this case, the output signal of the frequency divider 70 has a repeating pattern of 0011 (DF = 0.25).
[0047]
This second1In the clock recovery circuit according to the embodiment, the output V_PEHas the characteristic that each numerator denominator of the expression (15) is expressed symmetrically.First reference exampleOutput V of the arithmetic circuit 20b in the clock recovery circuit of FIG._PESince the numerator denominator is not symmetric in the expression (Equation (11)), if the circuit constant such as the coefficient K of the multiplier 52 is manufactured out of the designed value, a loop gain shift is caused. On the other hand1The clock recovery circuit according to the embodiment has an advantage that the requirement for the absolute accuracy of the circuit constant can be eased. This is effective in reducing the adjustment cost at the time of manufacturing and shipping and improving the yield.
[0048]
[Second reference example]
FIG.Second reference example3 is a diagram showing a clock recovery circuit of FIG. BookReference exampleIs composed of a phase comparator 2, a loop filter 3, a VCO 4, and an arithmetic circuit 22a. The operation circuit 22a calculates the phase comparison signal V of the phase comparator 2._PAnd edge density signal V_EAnd enter
V_PE= Α (V_P/ V_E) (16)
A signal V having a DC component represented by_PEIs output. Here, α is an arbitrary constant. Phase comparison signal V_PIs expressed by the above equation (1), and the edge density signal V_EIs represented by the above equation (2), and when these are substituted, equation (16) becomes
V_PE= Α (φ / π) (17)
Is represented by From the above, the bookReference exampleOutput V of the arithmetic circuit 22a_PEDoes not include the DF (Equation (17)), so that the phase comparison characteristic is not affected by the DF even when the phase difference φ takes any value from 0 to 2π.
[0049]
Of the present inventionSecond reference examplePhase comparison characteristics of the present inventionFirst reference exampleOf the same shape as the phase comparison characteristic (FIG. 2). Therefore, the output V of the arithmetic circuit 22a_PESince there is no leak of edge density information, changes in the lock range and the pull-in range due to changes in the edge density coefficient DF (changes in the data pattern) are suppressed, and it is possible to prevent jitter generation and jitter tolerance deterioration.
[0050]
FIG. 7 shows the present invention.Second reference exampleAnd an arithmetic circuit 22b that embodies the arithmetic circuit 22a in FIG. The arithmetic circuit 22b in FIG. 7 includes a differential amplifier 65, a multiplier 66, a resistor 67 having a resistance value R1, a resistor 69 having a resistance value R2, and a resistor 68 having a resistance value Rc. Assuming that the proportional coefficient is K (arbitrary constant), the output V of the multiplier 66_MIs
V_M= KV_PE・ V_E                                     (18)
Is represented by On the other hand, the voltage V of the positive input terminal (+) of the differential amplifier 65_INPBy selecting a value sufficiently smaller than the input impedance of the positive input terminal as the resistance value Rc of the resistor 68,
V_INP= 0 (19)
Given by Further, the voltage V of the negative input terminal (−) of the differential amplifier 65 is_INMIs obtained by voltage division of the resistor 67 and the resistor 69.
V_INM= (V_P-V_M) (R2 / (R1 + R2)) + V_M              (20)
Given by Assuming that the gain of the differential amplifier 65 is sufficiently large, the nature of a virtual short appears between the inputs of the closed-loop differential amplifier,
V_INP= V_INM                                           (21)
It becomes. Therefore, from the equations (19), (20), and (21), the output V of the_MIs
V_M=-(R2 / R1) V_P                               (22)
Is represented by Equations (18) and (22) represent the voltage at the same node and need to match. From this condition, the output V of the arithmetic circuit 22b is_PEIs
V_PE=-(R2 / R1) (1 / K) (V_P/ V_E) (23)
Given by Output V of arithmetic circuit 22b given by equation (23)_PEIs equivalent to equation (16) if α = − (R2 / R1) (1 / K) is defined. That is, the arithmetic circuit 22b shown in FIG.Second reference exampleIs one of the implementation examples of the arithmetic circuit 22a.
[0051]
Second reference exampleIs characterized in that the adder in the conventional clock recovery circuit is replaced with an arithmetic circuit 22b for performing division.First reference example,1It can be realized with a simpler circuit than the clock recovery circuit of the embodiment, and has a feature that the number of parts is small and the size can be reduced.
[0052]
【The invention's effect】
The clock recovery circuit of the present invention can completely cancel the edge density information at the output of the arithmetic circuit and extract only the phase comparison information. As a result, even when the phase difference φ takes any value from 0 to 2π, the phase comparison characteristic has an effect of being unaffected by edge density (type of data pattern, temporal fluctuation of edge density).
[Brief description of the drawings]
FIG. 1 of the present invention.First reference exampleFIG. 3 is a circuit diagram of a clock recovery circuit of FIG.
FIG. 2 is a phase comparison characteristic diagram of a phase comparator 2 of the clock recovery circuit of FIG.
FIG. 3 is a circuit diagram embodied as an arithmetic circuit 20a in the clock recovery circuit of FIG. 1 as 20b;
FIG. 4 of the present invention.1FIG. 3 is a circuit diagram of a clock recovery circuit according to the embodiment.
FIG. 5 is a circuit diagram in which an arithmetic circuit 21a and a reference voltage generator 57a in the clock recovery circuit of FIG. 4 are embodied as 21b and 57b.
FIG. 6 of the present invention.Second reference exampleFIG. 3 is a circuit diagram of a clock recovery circuit according to an embodiment.
FIG. 7 is a circuit diagram in which the arithmetic circuit 22a is embodied as 22b in the clock recovery circuit of FIG. 6;
FIG. 8 is a circuit diagram showing an example of a conventional clock recovery circuit.
FIG. 9 is a waveform chart showing an operation of the conventional clock recovery circuit of FIG.
10 is a phase comparison characteristic diagram of the phase comparator 2 of the conventional clock recovery circuit of FIG.
11 is a characteristic diagram showing the relationship between the free-running frequency of the VCO 4 and the average voltage of the output of the adder 19 in the conventional clock recovery circuit of FIG.
FIG. 12 is a circuit diagram showing a configuration example of another phase comparator portion of the conventional clock recovery circuit of FIG. 8;
[Explanation of symbols]
1: Input terminal for data Din
2: Phase comparator
3: Loop filter
4: VCO (voltage controlled oscillator)
5: Clock CLK output terminal
6: Buffer
7: Non-inverted output of buffer 6
8: inverted output of buffer 6
9, 10: D-FF (D-type flip-flop)
11: output of D-FF9
12: Output of D-FF10
13, 14: EXOR (exclusive OR gate)
I5: Output V of EXOR13_P
16: Output V of EXOR14_E
17: output V of the adder 19 and the arithmetic circuits 20a, 20b, 21a, 21b, 22a, 22b_PE
18: Output of loop filter 3
19: Adder
20a, 20b, 21a, 21b, 22a, 22b: arithmetic circuit
35, 36: AND gate
37: Output of AND gate 35
38: Output of AND gate 36
39: Buffer
40: Phase comparator
51: Differential amplifier 52: Multiplier
53-56: Resistor
57a, 57b: reference voltage generator
58: Differential amplifier
59: Multiplier
60-63: resistor
64: Multiplier
65: Differential amplifier
66: Multiplier
67-69: resistor
70: frequency divider
71: Delay circuit
72: EXOR

Claims (2)

A voltage-controlled oscillator whose oscillation frequency is controlled by voltage;
The edge density is detected and the phase comparison signal V _P, the edge density of the input signal containing a DC voltage component to detect a phase difference proportional to the phase difference between the output signal of said voltage controlled oscillator to the input signal from the input terminal a phase comparator for outputting an edge density signal V _E containing a DC voltage component which is proportional to,
A reference voltage generator for generating a reference edge density signal V _E0 having the same DC component and an edge density signal V _E to be output when the input signal of the edge density of the phase comparator is the reference is inputted,
The α and arbitrary constants, enter the said phase comparison signal _{V P} and the edge density signal _{V E} and the reference edge density signal _{V E0,} outputs α a _{(V P -V E) (V} E0 / V E) An arithmetic circuit;
A loop filter that extracts a component below a predetermined band from an output signal of the arithmetic circuit and applies the component as a control voltage to the voltage-controlled oscillator,
A clock recovery circuit for obtaining a recovery clock from an output signal of the voltage controlled oscillator. The arithmetic circuit includes a resistor group for determining the alpha, the _{(V P -V E) (V} E0 / V E) claims, characterized in that it is composed of a differential amplifier and a multiplier for performing an operation Item 2. The clock recovery circuit according to Item 1.

Images