JP2002280900A - Clock reproducing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent phase comparison characteristic from being affected by an edge density (kind of data pattern). SOLUTION: In a phase comparator 2, a phase compare signal VP containing a DC voltage component in proportion to the phase difference between output signal CLK of a VCO 4 and signals inputted to an input terminal 1 and an edge density signal VE containing a DC voltage component in proportion to the edge density of the input signal are outputted. In an arithmetic circuit 20a, with α as an arbitrary constant, α(VP-VE)/VE is derived. In a loop filter 3, a component of lower band than a prescribed band is extracted out of an output signal VPE of the arithmetic circuit 20a and applied to the VCO 4 as a control signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery circuit for extracting a clock from a serial data signal, and more particularly to a clock recovery circuit for realizing an optical receiver whose pull-in range and jitter characteristics do not depend on the data pattern of an input signal. It is related to the circuit.

[0002]

2. Description of the Related Art FIG. 8 is a diagram showing an example of a conventional clock recovery circuit (reference: CRHogge, JR., "A Self Cor
recting Clock Recovery Circuit ”, Journal of Lightw
ave Tech., vol. LT-3, No. 6 1985, p1323).

A conventional clock recovery circuit includes a phase comparator 2, a loop filter 3, and a voltage controlled oscillator (hereinafter referred to as a VCO).
4) and an adder 19. The phase comparator 2 has a function of outputting a signal including a DC voltage component proportional to the phase difference. Although many configurations have been proposed for the phase comparator, the configuration in FIG. 8 is the most widely known.

The input data Din is input to a D-type flip-flop (hereinafter abbreviated as D-FF) 9 via a data input terminal 1. The output signal of the VCO 4 triggers the D-FF 9 via the buffer 6. As a result, a signal in which the input data Din is retimed by the clock CLK appears at the output of the D-FF 9. Din and the retimed signal are exclusive OR gates (hereinafter, EXO)
R) (abbreviated as R). EXOR13
Will output a signal (phase comparison signal 15) V _P having a pulse width proportional to the phase difference between Din and CLK. The EXOR 13 outputs a pulse only when an edge (a transition from a high level to a low level or a transition from a low level to a high level) occurs in the input signal.
_P has a DC component proportional to not only the phase difference but also the edge density.

Din and CLK when the phase relationship where the rising edge of CLK coincides with the edge of Din are set as a reference (zero).
When the phase difference phi (radian), the edge density coefficients of the input signal Din (the number of edge edges number / clock CLK of the input data Din) and DF of the DC component of the phase comparison signal V _P has a high level low Using the level difference voltage as a unit voltage, V _P = φ · DF (1) Here, 0 <φ <2π, and 0 <
DF <0.5.

On the other hand, the signal retimed by the D-FF 9 is also input to the D-FF 10 and re-timed again by the inverted CLK output of the buffer 6. DF
The output of F9 and the output of D-FF10 are connected to the input of EXOR14. Since the two signals inputted to EXOR14 is retimed by the output of the VCO4 any, constant regardless of the pulse width of the output (edge density signal 16) _{V E} of EXOR14 to the phase difference between Din and CLK (C
If the duty of LK is exactly 50%, the clock cycle is half).

The EXOR 14 outputs a pulse only when an edge occurs in the input signal, similarly to the EXOR 13.
_VE has a DC component proportional to the edge density. If the duty of the CLK is exactly 50%, the DC component of the edge density signal _{V E} is expressed as _{V E = π · DF (2} ). The adder 19 receives the phase comparison signal _VP and the edge density signal _VE and outputs a voltage corresponding to the difference. From the equations (1) and (2), the DC component of the output _VPE of the adder 19 is expressed as follows: _VPE = (φ−π) · DF (3) After the output _VPE of the adder 19 is band-limited by passing through the loop filter 3,
Sent to CO4. The output of the VCO 4 is connected to the clock output terminal 5 and returned to the phase comparator 2 at the same time, whereby the phase synchronization is established between Din and CLK.

[0008] In the locked state, the DC component of the output _{V PE} of the adder 19 to oscillate at a substantially constant frequency VCO4
(Equation (3)) is almost constant. When the edge density coefficient DF changes under this condition, φ changes so as to keep _VPE constant, and the locked state is maintained. That is, φ
Will be modulated by the DF. Only φ is D
F is not affected when φ = π. When the lock state is realized when φ = π, φ does not change its value even if DF changes.

When the retimed data is required, the output of the D-FF 9 or the output of the D-FF 10 may be used. In FIG. 8, the output of the D-FF 10 is set to Dout, connected to the data output terminal 34, and transmitted to the outside.

FIG. 9 is a waveform diagram showing the operation of the conventional clock recovery circuit. Di shown in (a) given to input terminal 1
The n signal is retimed by the D-FF 9 by the CLK signal shown in (b) to obtain the signal 11 shown in (c), and the Din shown in (a)
EXOR from the signal shown in FIG.
Phase comparison signal 15 shown in (f) by 13 (= _{V P)} is obtained. Also, the signal 11 shown in FIG.
Is further retimed by the D-FF 10 using the inverted CLK signal shown in (d) to obtain the signal 12 shown in (e). The edge density shown in (g) by EXOR 14 from these signals (c) and (e) signal 16 (= _{V E)} is obtained. The difference between the phase comparison signal shown in (f) and the edge density signal shown in (g) (= V
_P− V _E ) is the output 17 (= V) shown in (h) of the adder 19.
_PE ).

FIG. 9I shows the operation when the phase of the CLK signal is ahead of the Din signal (0 <φ <π).
The pulse width of the phase comparison signal (f) is shorter than the pulse width of the edge density signal (g), and the DC component of the output _VPE of the adder 19 becomes negative. FIG. 9 (III) shows the operation when the phase of the CLK signal lags behind the Din signal (π <φ <2π), and the pulse width of the phase comparison signal (f) is the pulse of the edge density signal (g). It is longer than the width, and the DC component of the output _VPE of the adder 19 is positive. FIG. 9 (II) shows the operation when the phase relationship between the CLK signal and the Din signal is optimal (φ = π).

The optimal phase relationship is a phase relationship in which the D-FF 9 punches out the center of the Din signal at the rising edge of the CLK signal, and has the largest phase margin for the D-FF 9. In this case, the pulse width of the phase comparison signal (f) matches the pulse width of the edge density signal (g), and the DC component of the output of the adder 19 becomes zero. This agrees with the result of setting φ = π in equation (3).

FIG. 10 shows a phase comparison characteristic (D
(Relationship between phase difference φ of in-CLK and average voltage of output _VPE of adder 19). The case where the edge density coefficient DF of the input data Din is 0.5 and 0.25 is shown. The maximum value of DF is DF = 0.5 when Din is a 0/1 alternating signal, and DF <0.5 in the case of PN (pseudo noise) signal or normal data transmission.

As described above, the average voltage of the output _VPE of the adder 19 is kept substantially constant during the operation of the clock recovery circuit (at the time of locking). , Din-CLK is affected and changes its value. At this time, the degree of the influence depends on the value of the phase difference φ of Din-CLK itself. As shown in (II), when φ is close to π, φ is hardly affected by a change in the value of DF, and is not affected when φ is π. On the other hand, if φ deviates significantly from π, it will be greatly affected. That is, D
The optimum point (II) of the phase relationship of in-CLK is optimal in the sense that the phase margin of Din punching by CLK in the D-FF 9 is the maximum, and in addition, φ is the only phase relationship that is not affected by the DF. Can be said to be optimal in some sense. Also, the average voltage of the output V _PE of the adder 19 is also not affected by the DF is only optimal point (II).

FIG. 11 shows the free-running frequency of the VCO 4 and the adder 1
9 is a diagram illustrating a relationship between an output _{VPE and} an average voltage of the output _VPE . The slope in the locked state is negative, but this means that when the free-running frequency shifts to a higher direction for the same bit rate,
The lock state is maintained by reducing the average voltage of the output _VPE of the adder 19. Since the average voltage of the output V _PE of the adder 19 is not affected as described above DF exist only at the point (optimal point (II)), VCO 4 free running frequency also point which is not influenced by the DF (lock range Only in the center).

[0016]

As described above,
In the conventional clock recovery circuit shown in FIG. 8, the free-running frequency of the VCO 4 whose phase comparison characteristic is not affected by the DF exists only at points. Consider a case where the free-running frequency of the VCO 4 becomes higher (I) than the optimum point (II) (FIG. 11). Then the average voltage of the output V _PE of the adder 19 to maintain synchronization state by lowering its value. As a result, as shown as (I) in FIG.
Is greatly affected by the value of DF. This means that the punching timing of the D-FF 9 and D-FF 10 is greatly modulated by the DF.

As a result, in addition to the phase of the reproduced clock Cout being modulated by the DF, the phase of the retimed reproduced data Dout is similarly modulated by the DF. When the DF modulates the phase of Cout or the phase of Dout in this way, it causes problems such as new generation of jitter and reduction in tolerance to jitter included in the input data Din. Further, since the lock range and the pull-in range are shifted due to the difference in the DF, a sufficient pull-in range can be obtained only for the DF in a specific range.

In order to avoid the above problems, VCO4
It is necessary to adjust the free-running frequency of the VCO 4 to the optimum point, and to compensate for the free-running frequency of the VCO 4 not being affected by aging or environmental changes (temperature change, power supply voltage fluctuation, input data amplitude, etc.) It is necessary to provide. However, individual adjustment at the time of shipment of the VCO requires enormous operation, and it is practically difficult to compensate for the secular change of the free-running frequency of the VCO 4.

Further, even when the free-running frequency of the VCO 4 is adjusted to the optimum point, the fact that the phase comparison characteristic has the DF dependence as shown in FIG. It has DF dependency. Since the loop gain greatly affects jitter characteristics such as jitter transmission, it is necessary to design the loop gain to an optimum value so as to satisfy system requirements. If the loop gain optimization design is performed for a specific DF, the loop gain for another DF value will deviate from the optimum value, and if data having a DF outside the specific range is input, the jitter characteristic will be reduced. There is a possibility that the system requirements cannot be satisfied.

An object of the present invention is to provide a clock recovery circuit in which a phase comparison characteristic is not affected by an input data pattern, and performance degradation due to a change in an edge density coefficient can be suppressed. .

[0021]

According to a first aspect of the present invention, a voltage controlled oscillator whose oscillation frequency is controlled by a voltage and a phase difference between an output signal of the voltage controlled oscillator and an input signal from an input terminal are detected. detecting an edge density of the phase comparison signal V _P and the input signal containing a DC voltage component proportional to the phase difference of Sico phase comparator for outputting an edge density signal V _E containing a DC voltage component proportional to this edge density When the alpha and arbitrary constants, enter the said phase comparison signal _{V P} and the edge density signal _{V E, α (V P -V} E) / V E
And a loop filter that extracts a component below a predetermined band from the output signal of the arithmetic circuit and applies the component as a control voltage to the voltage-controlled oscillator, and generates a reproduction clock from the output signal of the voltage-controlled oscillator. It was configured to obtain.

In a second aspect based on the first aspect, the arithmetic circuit includes a resistor group for determining the α and the (V _P −
V _E ) / V _E , and a differential amplifier and a multiplier.

According to a third aspect of the present invention, the oscillation frequency is changed by a voltage.
Controlled voltage controlled oscillator and input signal from input terminal
The phase difference of the output signal of the voltage controlled oscillator with respect to
Phase comparison signal containing a DC voltage component proportional to the phase difference.
No. V_PAnd the edge density of the input signal
Edge density signal V including DC voltage component proportional to density _E
And a phase comparator that outputs
Output when an input signal with a different edge density is input.
Edge density signal V_EReference edge density with the same DC component as
Signal V_E0Reference voltage generator that generates
And the phase comparison signal V_PAnd the edge density signal V_E
And the reference edge density signal V_E0And α (V_P
-V_E) (V_E0/ V_E) And an arithmetic circuit for outputting
Extracts components below a specified band from the output signal of the arithmetic circuit
And a loop for applying a control voltage to the voltage-controlled oscillator.
A filter, wherein the output signal of the voltage-controlled oscillator is
It is configured to obtain a reproduction clock from the same.

[0024] A fourth aspect based on the third aspect, the arithmetic circuit includes a resistor group for determining the alpha, the (V _P -
V _E ) (V _E0 / V _E ) and a differential amplifier and a multiplier.

According to a fifth aspect of the present invention, the oscillation frequency is changed by a voltage.
Controlled voltage controlled oscillator and input signal from input terminal
The phase difference of the output signal of the voltage controlled oscillator with respect to
Phase comparison signal containing a DC voltage component proportional to the phase difference.
No. V_PAnd the edge density of the input signal
Edge density signal V including DC voltage component proportional to density _E
, And α is an arbitrary constant.
Phase comparison signal V_PAnd the edge density signal V_EAnd enter
α (V_P/ V_EAnd an arithmetic circuit for outputting the arithmetic circuit
Take out components below a predetermined band from the output signal of
Loop fill applied as control voltage to voltage controlled oscillator
A regeneration clock based on the output signal of the voltage controlled oscillator.
It was configured to get a lock.

[0026] A sixth aspect of the fifth invention, the arithmetic circuit includes a resistor group for determining the alpha, the (V _P /
V _E ), and a differential amplifier and a multiplier.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION A clock recovery circuit according to the present invention is most characterized in that an adder for performing subtraction in a conventional clock recovery circuit is replaced with an arithmetic circuit including division. By performing subtraction between the phase comparison signal V _P and edge density signal V _E by the conventional clock recovery circuit adder for taking out the phase comparison information at the output V _PE of the adder 19, the clock of the present invention by performing the division between the phase comparison signal V _P and edge density signal V _E by the arithmetic circuit recovery circuit including a division, be taken only completely offset phase comparison information edge density information different in the output of the arithmetic circuit .

In the conventional clock recovery circuit, Din-CL
In the case of the phase difference K phi is π only the edge density information to be able fully offset, the output V _PE to edge density factor DF of phi is the out of the π adder 19 leaks. Such a leak of the edge density coefficient DF is as follows.
Changes in the lock range and pull-in range due to a change in the edge density coefficient DF (changes in the data pattern), jitter generation, and jitter tolerance deterioration are caused. The present invention has been made in order to suppress the performance degradation due to such a change in the edge density coefficient DF. By applying an arithmetic circuit including division, even if the phase difference φ of Din-CLK deviates from π, the calculation is performed. The edge density coefficient does not leak to the output of the circuit.

[First Embodiment] FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a diagram illustrating a clock recovery circuit according to the embodiment. In the present embodiment, the phase comparator 2, the loop filter 3, the VCO
4. It is composed of an arithmetic circuit 20a. The phase comparator 2 has a function of outputting a signal including a DC voltage component proportional to the phase difference. The input data Din is input to the D-FF 9 via the data input terminal 1. The output signal of the VCO 4 triggers the D-FF 9 via the buffer 6.

As a result, the input data Din becomes the clock CL
The signal retimed by K appears at the output of D-FF9. Din and the retimed signal are EXOR1
Connected to 3 inputs. The EXOR 13 outputs a signal having a pulse width proportional to the phase difference between Din and CLK (the phase comparison signal 1).
5) will be output _{V P.} As already mentioned,
The phase difference between Din and CLK when the rising edge of CLK coincides with the edge of Din as a reference (zero) is φ (radian), the edge density coefficient of the input signal (the number of edges of input data Din / clock CLK Number of edges)
When the DC component of the phase comparison signal V _P is expressed by the above equation (1).

On the other hand, the signal retimed by the D-FF 9 is also input to the D-FF 10 and re-timed again by the inverted CLK output of the buffer 6. DF
The output of F9 and the output of D-FF10 are connected to the input of EXOR14. Since the two signals inputted to EXOR14 is retimed by the output of the VCO4 any, constant regardless of the pulse width of the output (edge density signal 16) _{V E} of EXOR14 to the phase difference between Din and CLK (C
If the duty of LK is exactly 50%, the clock cycle is half).

The EXOR 14 outputs a pulse only when an edge occurs in the input signal, similarly to the EXOR 13.
_VE has a DC component proportional to the edge density. If the duty of the CLK is exactly 50%, the DC component of the edge density signal V _E is expressed by the above equation (2).

[0033] DC operation circuit 20a, which inputs a phase comparison signal _{V P} and edge density signal _{V E} of the phase comparator 2 is represented by _{V PE = α (V P -V} E) / V E (4) A signal _VPE having a component is output. Here, α is an arbitrary constant. The phase comparator較信No. V _P is in the (1), since the edge density signal V _E is expressed by the equation (2), Substituting these (4) is _{V PE = (α / π)} ( φ-π) (5)

As described above, in the conventional clock recovery circuit, since the output density _VPE of the adder 19 includes the edge density coefficient DF (Equation (3)), the phase difference φ becomes π.
In the case where it deviates from the above, the phase comparison characteristic was affected by the DF. Such a leak of the edge density information causes a change in the lock range and the pull-in range due to a change in the edge density coefficient DF (a change in the data pattern), generation of jitter, and deterioration of jitter tolerance.

On the other hand, the arithmetic circuit 20 of the present embodiment
Since the output _VPE of a does not include DF (Equation (5)),
Even when the phase difference φ takes any value from 0 to 2π, the phase comparison characteristic is not affected by the DF. Accordingly, the output V _PE of the arithmetic circuit 20a because there is no leakage of the edge density information is suppressed change in the lock range and the pull-in range due to the change of the edge density factor DF (changes in data patterns) are jitter generation, jitter tolerance degradation Can be prevented.

FIG. 2 shows the phase comparison characteristic (Din
And the phase difference φ of -CLK, a relationship) between the average voltage at the output _{V PE} of the arithmetic circuit 20a. The case where the edge density coefficient (DF) of the input data Din is 0.5 and 0.25 is shown. While the clock recovery circuit is operating (at the time of locking), the arithmetic circuit 20
Since the average voltage of the output of a is kept substantially constant, the phase difference φ of Din-CLK has an effect on the phase comparison characteristic (FIG. 10) in the conventional clock recovery when the value of DF changes during operation. The value was changed. The larger the φ deviated from π, the greater the effect. On the other hand, in the clock recovery circuit of the present embodiment, the DF
, The phase difference φ of Din-CLK is not affected and is constant, and even if the clock recovery circuit keeps the synchronized state with φ largely deviating from π, I do not receive.

That is, in the conventional clock recovery circuit,
It is necessary to precisely adjust the free-running frequency of the VCO 4 so that φ takes a value close to π, and it is necessary to suppress a temperature change, a secular change, and a power supply voltage fluctuation that cause the free-running frequency to drift. Clock recovery circuit does not cause performance degradation even if φ deviates from π, so it is not necessary to adjust the free-running frequency of VCO4 with high accuracy. Even so, it is possible to relax the allowable range.

FIG. 3 shows one specific circuit 20b of the arithmetic circuit 20a according to the first embodiment of the present invention. The arithmetic circuit 20b in FIG. 3 includes a differential amplifier 51, a multiplier 52, resistors 53 and 54 having a resistance value R1, and resistors 55 and 56 having a resistance value R2. Thereafter, the input-output relationship of the arithmetic circuit 20b, that is, the phase comparison signal _{V P,} edge density signal _{V E,} the output V of the arithmetic circuit 20b
The relationship between _PEs will be described.

[0039] When the proportional coefficient a K (arbitrary constant), the output _{V M} of the multiplier 52 is expressed by _{V M = K · V PE ·} V E (6). On the other hand, the positive input terminal (+) of the differential amplifier 5l
The voltage _{V INP} the voltage division between the resistor 54 resistor 56 is given by _{V INP = (V E -0)} (R2 / (Rl + R2)) + 0 (7). The negative input terminal of the differential amplifier 5l (-) by the voltage division of the voltage _{V INM} resistor 53 and the resistor _{55, V INM = (V P} -V M) (R2 / (Rl + R2)) + V M ( 8) given by Assuming that the gain of the differential amplifier 51 is sufficiently large, the nature of virtual short-circuit (virtual short) appears between the inputs of the closed-loop differential amplifier, and V _INP = V _INM (9). Therefore, (7), (8) and (9), the output _{V M} of the multiplier 52, _V M = - represented by _{(R2 / R1) (V P} -V E) (10). Equations (6) and (10) represent the voltage at the same node and therefore need to match. From this condition, the output _{V PE} arithmetic circuit 20b, _V PE = - given by (R2 / R1) (1 / K) (V P -V E) / V E (11).

Operation circuit 2 given by equation (11)
Expression for the output _{V PE} = 0b is, α = - (R2 / R1 ) (1 /
Defining as K) matches equation (4). That is, FIG.
The operation circuit 20b shown in FIG. 7 is one of the examples of realization of the operation circuit 20a in the first embodiment of the present invention. Here, although the sign of α is negative in the above example, it changes depending on the polarity of the connection between the multiplier 52 and the differential amplifier 51, the modulation polarity of the VCO 4, and the like. What is necessary is just to select the polarity which establishes phase synchronization.

The configuration of the phase comparator 2 is not limited to the configuration shown in FIG. That is, the D-FF 10 can be realized by a delay circuit (see Reference: CRHogge, JR., "A Sel
f Correcting Clock Recovery Circuit ", Journal of Li
ghtwave Tech., vol. LT-3, no. 6, 1985, p1323), and Din may be directly input to the delay circuit instead of the output of the D-FF9. Also, EXOR13, EX
OR14 changed to AND gates 35 and 36 (references:
A similar effect can be obtained by using the phase comparator 40 (FIG. 12) to which the buffer 39 is added as the phase comparator of the present invention. That is, the clock recovery circuit using the phase comparator 40 shown in FIG. 12 also has a problem that the free-running frequency of the VCO 4 whose phase comparison characteristic is not affected by the DF exists only at a point. Is applied as the phase comparator 2 of the first embodiment, it is possible to realize a phase comparison characteristic that is not affected by the DF.

[Second Embodiment] FIG. 4 is a diagram showing a clock recovery circuit according to a second embodiment of the present invention. In the present embodiment, the phase comparator 2, the loop filter 3, the VCO 4,
The arithmetic circuit 21a includes a reference voltage generator 57a. The difference from the first embodiment is that the reference voltage generator 57
a is newly provided and this output _VE0 is input to the arithmetic circuit 21a.

The arithmetic circuit 21a receives the phase comparison signal _{V P} and edge density signal _{V E} of the phase comparator 2, in _{V PE = α (V P -V} E) (V E0 / V E) (12) A signal _VPE having the indicated DC component is output. Here, α is an arbitrary constant. _VE0 is the output of the reference voltage generator 57a, and the reference edge density coefficient DF
And a signal having the same DC component and the DC component contained in the edge density signal V _E in the case of (e.g., DF = 0.5). That is, the reference edge density coefficient is DF = DF
_If it is set to ₀ , the output of the reference voltage generator 57a is expressed by the following equation (2): V _EO = π · DF ₀ (13) The phase comparison signal _VP is expressed by the above equation (1), and the edge density signal _VE is expressed by the above equation (2). As a function of φ and the reference edge density coefficient DF ₀ , V _PE = (α · DF ₀ ) (φ−π) (14)

[0044] From the above, since the output V _PE of the arithmetic circuit 21a of the present embodiment does not include DF ((14) formula), even if the phase difference φ took any value from 0 to 2 [pi, The phase comparison characteristic is not affected by the DF. The phase comparison characteristic of the second embodiment of the present invention has the same shape as the phase comparison characteristic (FIG. 2) of the first embodiment of the present invention.
Accordingly, the output V _PE of the arithmetic circuit 21a because there is no leakage of the edge density information is suppressed change in the lock range and the pull-in range due to the change of the edge density factor DF (changes in data patterns) are jitter generation, jitter tolerance degradation Can be prevented.

FIG. 5 shows an arithmetic circuit 21b and a reference voltage generator 57b which embody the arithmetic circuit 21a and the reference voltage generator 57a according to the second embodiment of the present invention. The arithmetic circuit 21b in FIG.
8, a multiplier 64, resistors 60 and 61 having a resistance value of R1, and resistors 62 and 63 having a resistance value of R2. The arithmetic circuit 21b of the present embodiment is different from the arithmetic circuit 2 of the first embodiment.
0b (FIG. 3) in that a multiplier 64 is added. (11) and applied at an addition amount of the multiplier 64 in equation operation circuit 21b outputs _{V PE is, V PE = - (R2 /} Rl) (Kb / Ka) (V P -V E) (V E0 / V _E ) (15) Here, the coefficient of the multiplier 59 is Ka, and the coefficient of the multiplier 64 is Kb. (15) expression for the output _{V PE} arithmetic circuit 21b given by equation, α = - (R2 / R1 ) if (Kb / Ka) and definition (1
2) It matches the equation. That is, the arithmetic circuit 21 shown in FIG.
"b" is one of the implementation examples of the arithmetic circuit 21a in the second embodiment of the present invention.

The reference voltage generator 57b shown in FIG.
Is composed of a frequency divider 70, a delay circuit 71, and an EXOR 72. An example in which the reference edge density coefficient DF _{0 is set} to 0.5 will be described. In this case, the frequency division ratio of the frequency divider 70 may be set to 1/2, and the delay time of the delay circuit 71 may be selected to be 1/2 of the clock cycle. In this case, the frequency divider 70
The output signal is 0/1 alternating signal data (DF = 0.5)
The EXOR 72 sets E when the Din is a 0/1 alternating signal.
XOR14 outputs a signal equivalent to the edge density signal _{V E} to be output. Also, the reference edge density coefficient DF _{0 is set} to 0.25
In this case, the frequency division ratio of the frequency divider 70 may be set to 、, and the delay time of the delay circuit 71 may be selected to be の of the clock cycle. In this case, the output signal of the frequency divider 70 has a repeating pattern of 0011 (DF = 0.25).

The clock recovery circuit according to the second embodiment
Then, the output V of the arithmetic circuit 21b is _PEExpression of ((15)
Each of the numerator and denominator of the formula) has a feature of being expressed symmetrically.
Arithmetic circuit in clock recovery circuit according to first embodiment
Output V of 20b_PEIn the expression (Equation (11)), the numerator denominator is
Since it is not symmetrical, for example, the circuit
If the number is manufactured out of design, the loop gain
Invite you. On the other hand, the clock reset of the second embodiment
In a raw circuit, it is possible to relax the requirement for the absolute accuracy of circuit constants.
There is a point. This reduces adjustment costs during manufacturing and shipping, and
This is effective for improving the yield.

[Third Embodiment] FIG. 6 is a diagram showing a clock recovery circuit according to a third embodiment of the present invention. In the present embodiment, the phase comparator 2, the loop filter 3, the VCO 4,
It comprises an arithmetic circuit 22a. Operation circuit 22a includes a phase comparator of the phase comparator 2 signals _{V P} and edge density signal _{V E}
And outputs a signal _VPE having a DC component represented by _VPE = α ( _VP / _VE ) (16). Here, α is an arbitrary constant. The phase comparison signal _VP is expressed by the above equation (1), and the edge density signal _VE is expressed by the above equation (2).
When these are substituted, the expression (16) is expressed by the following expression: V _PE = α (φ / π) (17) From the above, because does not include DF in the output V _PE of the arithmetic circuit 22a of the present embodiment ((17)), even if the phase difference φ took any value from 0 to 2 [pi, the phase comparison characteristic Is not affected by DF.

Phase comparison characteristic of the third embodiment of the present invention
Is the phase comparison characteristic of the first embodiment of the present invention (FIG. 2)
It has the same shape characteristics as. Therefore, the output of the arithmetic circuit 22a is
Force V _PEEdges do not leak edge density information.
Due to the change in the density coefficient DF (change in the data pattern)
Changes in the lock range and pull-in range are suppressed,
Data generation and deterioration of jitter tolerance can be prevented.

FIG. 7 shows an arithmetic circuit 22b which embodies the arithmetic circuit 22a according to the third embodiment of the present invention. The arithmetic circuit 22b in FIG.
5, a multiplier 66, a resistor 67 having a resistance value Rl, a resistance value R2
And a resistor 68 having a resistance value Rc. Assuming that the proportional coefficient is K (arbitrary constant), the multiplier 66
The output _{V M} of is expressed by _{V M = K · V PE ·} V E (18). On the other hand, the positive input terminal (+) of the differential amplifier 65
The voltage V _INP is given by V _INP = 0 (19) by selecting a value sufficiently smaller than the input impedance of the positive input terminal as the resistance value Rc of the resistor 68. The voltage V _INM of the negative input terminal (−) of the differential amplifier 65 is V _INM = (V _P −V _M ) (R2 / (R1 + R2)) + V _M (by the voltage division of the resistor 67 and the resistor 69). 20) given by Assuming that the gain of the differential amplifier 65 is sufficiently large, the nature of a virtual short circuit (virtual short) appears between the inputs of the closed loop differential amplifier, and V _INP = V _INM (21) Therefore, (19), (20) and (21), the output _{V M} of the multiplier 66, _V M = - represented by _{(R2 / R1) · V P} (22). Equations (18) and (22) represent the voltage at the same node and therefore need to match. From this condition, the output _{V PE} arithmetic circuit 22b, _{V PE} = - given by (R2 / R1) (1 / K) (V P / V E) (23). (23) expression for the output _{V PE} arithmetic circuit 22b given by equation α = - (R2 / R1) (1 /
Defining as K) matches equation (16). That is, the arithmetic circuit 22b shown in FIG. 7 is one of the implementation examples of the arithmetic circuit 22a in the third embodiment of the present invention.

The clock recovery circuit according to the third embodiment comprises:
It is characterized in that an adder in a conventional clock recovery circuit is replaced by an arithmetic circuit 22b for performing division, and can be realized by a simpler circuit than the clock recovery circuits of the first and second embodiments. The feature is that the number of points is small and miniaturization can be achieved.

[0052]

The clock recovery circuit of the present invention can completely cancel the edge density information at the output of the arithmetic circuit and extract only the phase comparison information. As a result, even when the phase difference φ takes any value from 0 to 2π, the phase comparison characteristic has an effect of being unaffected by edge density (type of data pattern, temporal fluctuation of edge density).

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a clock recovery circuit according to a first embodiment of the present invention.

FIG. 2 is a phase comparison characteristic diagram of a phase comparator 2 of the clock recovery circuit of FIG.

FIG. 3 shows an arithmetic circuit 2 in the clock recovery circuit of FIG.
FIG. 9 is a circuit diagram embodied by setting 0a to 20b.

FIG. 4 is a circuit diagram of a clock recovery circuit according to a second embodiment of the present invention.

5 is an arithmetic circuit 2 in the clock recovery circuit of FIG.
FIG. 2 is a circuit diagram in which 1a and a reference voltage generator 57a are embodied as 21b and 57b.

FIG. 6 is a circuit diagram of a clock recovery circuit according to a third embodiment of the present invention.

7 is an arithmetic circuit 2 in the clock recovery circuit of FIG.
FIG. 2 is a circuit diagram in which 2a is embodied as 22b.

FIG. 8 is a circuit diagram showing an example of a conventional clock recovery circuit.

FIG. 9 is a waveform chart showing an operation of the conventional clock recovery circuit of FIG.

10 is a phase comparison characteristic diagram of the phase comparator 2 of the conventional clock recovery circuit of FIG.

11 shows a VCO4 of the conventional clock recovery circuit of FIG.
FIG. 4 is a characteristic diagram showing a relationship between a free-running frequency and an average voltage of an output of an adder 19.

FIG. 12 is a circuit diagram showing a configuration example of another phase comparator portion of the conventional clock recovery circuit of FIG.

[Explanation of symbols]

1: input terminal of data Din 2: phase comparator 3: loop filter 4: VCO (voltage controlled oscillator) 5: output terminal of clock CLK 6: buffer 7: non-inverted output of buffer 6 8: inverted output of buffer 6 9 , 10: D-FF (D type flip-flop) ll: D-FF9 output of 12: D-FF10 output 13, 14: EXOR (exclusive OR gates) I5: EXOR13 output _V P 16: EXOR14 output _VE 17: adder 19, arithmetic circuits 20a, 20b, 21a,
21b, 22a, 22b of the output _V PE 18: the loop filter 3 of the output 19: adder 20a, 20b, 21a, 21b, 22a, 22b: arithmetic circuits 35 and 36: AND gate 37: Output of AND gate 35 38 : Output of AND gate 36: buffer 40: phase comparator 51: differential amplifier 52: multipliers 53 to 56: resistors 57 a and 57 b: reference voltage generator 58: differential amplifier 59: multiplier 60 to 63 : Resistor 64: multiplier 65: differential amplifier 66: multiplier 67 to 69: resistor 70: frequency divider 71: delay circuit 72: EXOR

Continuing on the front page (72) Inventor Takachi Enoki 2-3-1 Otemachi, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Shoji Hiratsuka 1-12-1 Dogenzaka, Shibuya-ku, Tokyo N (72) Inventor Masahiro Muraguchi 1-12-1 Dogenzaka, Shibuya-ku, Tokyo NTT Electronics Corporation F-term (reference) 5J106 AA04 CC01 CC21 CC41 DD44 JJ02 KK05

Claims (6)

[Claims] 1. A voltage controlled oscillator whose oscillation frequency is controlled by a voltage, and a phase including a DC voltage component proportional to the phase difference, detecting a phase difference between an output signal of the voltage controlled oscillator and an input signal from an input terminal. a comparison signal V _P, to detect the edge density of the input signal and a phase comparator for outputting an edge density signal V _E including a direct-current voltage component proportional to the edge density, the α and arbitrary constants, the phase comparison signal inputs the V _P and the edge density signal V _E, the arithmetic circuit for outputting _{α (V P -V E) /} V E, a predetermined band following components from the output signal of said arithmetic circuit is taken out, the voltage A clock recovery circuit comprising: a loop filter for applying a control voltage to a control oscillator; and obtaining a recovery clock from an output signal of the voltage control oscillator. Wherein said arithmetic circuit is characterized a resistor group for determining the alpha, that is composed of a differential amplifier and a multiplier for performing computation of the _{(V P -V E) / V} E Claim 1
2. A clock recovery circuit according to claim 1. 3. A voltage controlled oscillator whose oscillation frequency is controlled by a voltage, and a phase including a DC voltage component proportional to the phase difference by detecting a phase difference between an output signal of the voltage controlled oscillator and an input signal from an input terminal. a comparison signal V _P, a phase comparator for outputting an edge density signal V _E containing a DC voltage component which is proportional to the edge density detecting an edge density of the input signal, an edge density of the phase comparator is the reference a reference voltage generator for generating a reference edge density signal V _E0 having the same DC component and an edge density signal V _E to be output when the input signal is input, the α and arbitrary constants, and the phase comparison signal V _P type and the edge density signal _{V E} and the reference edge density signal _{V E0,} an operation circuit for outputting α a _{(V P -V E) (V} E0 / V E), or an output signal of said arithmetic circuit Taking out a predetermined bandwidth following ingredients, and a loop filter for applying a control voltage to said voltage controlled oscillator, a clock recovery circuit, characterized in that to obtain a reproduced clock from the output signal of the voltage controlled oscillator. 4. The arithmetic circuit according to claim 1, wherein the resistor group determines the α.
And (V_P-V_E) (V_E0/ V _E)
Characterized by comprising a dynamic amplifier and a multiplier
The clock recovery circuit according to claim 3. 5. A voltage controlled oscillator whose oscillation frequency is controlled by a voltage, and a phase including a DC voltage component proportional to the phase difference, detecting a phase difference between an output signal of the voltage controlled oscillator and an input signal from an input terminal. a comparison signal V _P, to detect the edge density of the input signal and a phase comparator for outputting an edge density signal V _E including a direct-current voltage component proportional to the edge density, the α and arbitrary constants, the phase comparison signal An arithmetic circuit for inputting _VP and the edge density signal _VE and outputting α ( _VP / _VE ); extracting a component below a predetermined band from an output signal of the arithmetic circuit; A clock recovery circuit comprising: a loop filter for applying a control voltage; and obtaining a recovered clock from an output signal of the voltage controlled oscillator. 6. The arithmetic circuit according to claim 5, wherein said arithmetic circuit comprises a resistor group for determining said α, a differential amplifier and a multiplier for performing said ( _VP / _VE ) operation. 2. A clock recovery circuit according to claim 1.