KR860001258B1 - Clock regenerating circuit - Google Patents

Abstract

The circuit compares a received signal phase with a generated clock signal phase to generate clock signals. The clock signals are used to demodulate the run-length limited signals. A received signal is temporarily stored in the first memory(9) with the frequency divider syncronization pulse. The second memory(11) stores the content of the first memory with the syncronization pulse. When the output signal phase of two OR gates (10, 12) are compared, the action generates clock signals.

Description

Clock regeneration circuit

1 is a block diagram showing a conventional clock reproduction circuit.

2 is a circuit block diagram showing one embodiment of the present invention.

3 to 5 are each output waveform diagram in each state of the circuit of FIG.

6 is a graph showing the characteristics of the phase comparing means formed in the circuit of FIG.

* Explanation of symbols for main parts of the drawings

9, 11: D-type flip flop 10, 12: Exclusive logic gate

14: LPF 15: VOC

16: divider

The present invention relates to a clock regeneration circuit, and more particularly, to a clock regeneration circuit for demodulating a modulated signal by a run-length limited modulation scheme.

As a modulation signal processing method for transmitting digital information signals, such as a PCM (pcm) signal, to a recording medium or a transmission medium, so-called run limited limited modulation methods capable of self-clocking in consideration of high density have been adopted. In this run-length limited modulation system, it is common to reproduce a demodulation clock signal from a signal obtained from a recording medium or a transmission medium at the time of demodulation.

1 is a block diagram showing a conventional example of a clock reproducing circuit for reproducing a clock signal. In this figure, an input signal consisting of a modulation signal by a run length limited modulation method reproduced from a recording medium such as a digital audio disc is a differential circuit 1 and a memory circuit 2 comprising a D-type flip flop or the like. Is being supplied to.

When each of the rising edge and the falling edge of the input signal arrives by the differential circuit 1, positive and negative pulses are output and supplied to the full-wave rectifying circuit 3, respectively. do. In the full-wave rectifying circuit 3, since the polarity of the negative pulse output by the differential circuit 1 is inverted, a positive pulse is obtained each time the incoming and outgoing edges of the input signal arrive.

The output of the full-wave rectification circuit 3 is supplied to the trigger input terminal of the monostable multivibrator (hereinafter referred to as monostable multi). The inversion time of the monostable multi 4 is set to the same time as half of the cycle of the regeneration clock obtained.

The Q output is supplied to the phase comparator 5 as the monostable multi (4). The phase comparator 5 forms a phase locked loop (PII) together with the LPF (low pass filter) 6 and the VCO (voltage controlled oscillator) 7. That is, the output of the VCO is compared with the output of the monostable multi 4 in the phase comparator 5, so that a signal corresponding to the difference in the frequency and phase of these two signals is controlled by the control voltage of the VCO 7 through the LPF 6. Becomes The output of the VCO 7 is provided by the phase adjusting circuit 8 for compensating for the phase delay caused by the signal delay time in the differential circuit 1, the full-wave rectifier circuit 3, and the monostable multi-component 4.

As described above, the conventional clock regeneration circuit is complicated in construction and requires a time setting capacitor and a resistor for determining the inversion time of the monostable multi (4). Since an external attachment terminal such as the back is required, there is a defect that is not suitable for IC. It is therefore an object of the present invention to provide a clock reproducing circuit suitable for IC, without the need for a terminal having a simple configuration and externally attaching a capacitor for time setting.

The clock reproducing circuit according to the present invention is a signal obtained by performing exclusive logic with a signal corresponding to the storage contents of the first storage means for temporarily storing the state of the input signal in synchronization with the input signal and the pulse output from the pulse generating means. The pulse width and the pulse width of the signal obtained by performing exclusive logic with the second storage means for temporarily storing the state of the output of the first storage means and the output of the first storage means in synchronization with the pulses are equal to each other. By controlling the repetition frequency, the pulse is output as a regeneration clock while eliminating the phase difference between the input signal and the pulse.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2 to 6.

In Fig. 2, the input signal a consisting of a modulated signal according to the run-length limited modulation method is the D input terminal of the D-type flip-flop 9 as the first storage means and one input terminal of the exclusive logic gate 10. Is being supplied to. The Q output b of the D-type flip-flop 9 is supplied to the D input terminal of the D-type flip-flop 11 as the second storage means, and at the same time, the input terminal and the exclusive logic gate of the exclusive logic gate 10 It is supplied to one input terminal of 12). The Q output C of the D flip-flop 11 is supplied to the other input terminal of the gate 12.

The output of the gate (12), d is supplied to the top (正相) input terminal of the operational amplifier ₁ by interposing the resistor R 13. The capacitor C ₁ is connected between the normal input terminal of the operational amplifier 13 and the ground.

In addition, the output e of the gate 10 is supplied to the reverse phase input terminal of the operational amplifier 13 via the resistor R ₂ , and a capacitor (a) is connected between the reverse phase input terminal and the output terminal of the operational amplifier 13. c ₂ ) is connected.

The operational amplifier 13, the capacitors C ₁ and C ₂ , and the resistors R ₁ and R ₂ form an LPF 14 which extracts and outputs the low frequency component of the signal obtained by amplifying the difference between the two inputs. The control voltage is supplied from the operational amplifier 13 to the VCO 15. The output of the VCO 15 is divided by two by the divider 16.

Thus, the? Phase output f of the divider 16 is supplied to the clock of the D flip-flop 11 and is supplied to a demodulation circuit (not shown) as a demodulation reproducing clock. In addition, the zero-phase output g of the divider 16 is supplied to the clock input terminal of the D flip-flop 9 so that the input signal a is latched on the D flip-flop 9, and the input signal from the flip flop 9 is input. A signal obtained by delaying a by half a clock of the reproduction clock is output and supplied to the demodulation circuit (not shown) as a data output.

The operation of each part in the above configuration will be described with reference to FIGS. 3 to 6.

The D flip-flops 9 and 11 are to latch the signal supplied to the D input terminal at the granularity of the clock input.

3 (a) to 3 (g) show the phase of the π-phase output f so that the timing of appearance of the rising edge and the falling edge of the input signal a coincides with the appearance timing of the rising edge of the π-phase output f as a regeneration clock. 3 (a) is a waveform of zero-phase output g, 3 (b) is a waveform of π-phase output f, and 3 (c) is a waveform of the input signal a. 3 (d) is the waveform of the Q output b of the D flip-flop 9, 3 (e) is the waveform of the Q output C of the D flip-flop 11, and 3 (f) is the exclusive logic. The waveform of the output e of the gate 10 and FIG. 3 (g) show the waveform dynamics of the output d of the exclusive logic gate 12, respectively.

4 (a) to 4 (g) show a case in which the timing of appearance of the standing edge and the incoming edge of the input signal a is shifted forward than the timing of appearance of the standing edge of the π-phase output f because the phase of the input signal a is accelerated. The waveform of the same signal as each of FIG. 3 (a)-FIG. 3 (g) is shown, respectively. 5 (a) to 5 (g) show that the phase timing of the input signal a is delayed so that the appearance timing of the granular paper and the granular paper in the input signal a is shifted backward than the appearance timing of the granular paper of the? Phase output f. The waveforms of the same signal as those in FIGS. 3 (a) to 3 (g)

As is apparent from FIGS. 3 to 5, the output e of the exclusive logic gate 10 is generated whenever the rising and falling edges of the input signal a arrive and the phase relationship between the input signal a and the π-phase output f again. In other words, a pulse having a pulse width that changes in response to the difference between the timing of appearance of the rising edge and the falling edge of the input signal a and the rising edge of the π-phase output.

The output d of the exclusive logic gate 12 is a pulse whose pulse width is equal to the pulse width of the zero-phase output g and the π-phase output f. Therefore, when the timing of appearance at the input signal a and the appearance timing at the arrival coincide with the appearance timing of the formation edge at π phase appearance f, the pulse width of the output e of the exclusive logic gate 10 is exclusive logic gate 12. Is equal to the pulse width of the output d.

When the phase of the input signal a becomes faster, the pulse width of the output e becomes wider than the pulse width of the output d. On the contrary, when the phase of the input signal a is late, the pulse width of the output e becomes narrower than the pulse width of the output d. .

As described above, the amount of the DC component of the signal obtained by integrating the output of the exclusive logic gate 10 including the phase information varies with the probability of occurrence of the edge of the reproduction signal. The signal obtained by integrating the output of the one exclusive logic gate 12 becomes a signal whose level changes only by the probability of appearance of the edge of the reproduction signal. Therefore, by supplying the outputs e and d of these exclusive logic gates 10 and 12 to the LPF 14 including the differential amplifier, it is possible to obtain a signal whose level changes only by the phase information.

In other words, the D-type flip-flops 9 and 11 and the exclusive logic gates 10 and 12 detect the phase difference between the input signal a and the π phase output f, and from 1π to π of the input phase difference as shown in FIG. The phase comparison means in which the output changes linearly with respect to the change reaching the range of. The D-type flip flops 9 and 11 and the exclusive logic gates 10 and 12 forming the phase comparison means form a PLL together with the LPE 14, the VCO 15 and the divider 16, and The phase output f coincides with the appearance timing of the granular edge and the appearance timing of the granular edge and the incoming edge of the reproduction signal a, and is output as a demodulation reproduction clock of the π phase output f.

In the above operation, the D-type flip flop 9 is latched by the π-phase output f with the input signal a as the regeneration clock, and π as the regeneration clock together with the D flip-flop 11 and the gates 10 and 12. Since the phase comparison means of the PLL generating the phase output f is formed, there is no phase delay, and the memory circuit 2 is free from the D-type flip flop 9 without a circuit like the phase adjustment circuit 8 in FIG. You can get a signal equal to the output of. In addition, the input signal a is directly supplied to the D-type flip flop 9 forming the phase comparing means, and the differential circuit 1, the full-wave rectification circuit 3, and the monostable multi-component 4 are not necessary in FIG. As a result, not only the configuration is simple but also external attachment terminals such as time-limiting capacitors are unnecessary, so that the IC can be easily formed.

In the above embodiment, the output b of the D flip-flop 9 becomes a data output and the π-phase output f is output as a reproduction clock. However, the output C of the D flip-flop 11 becomes a data output and 0 The phase output g may be output as a reproduction clock. In addition, in the above embodiment, the oscillation frequency of the VCO 15 is twice the clock frequency, but when the duty cycle of the VCO 15 is 50%, the oscillation frequency of the VCO 15 is made equal to the clock frequency. It is possible to omit the divider 16. Also, in the above embodiment, an exclusive logic crab

As described above, the clock reproducing circuit according to the present invention has a configuration in which the phase of the regeneration clock is controlled by directly comparing the input signal and the regeneration clock by two storage means and two exclusive logic means. In addition, since external terminals such as time limiting capacitors are unnecessary, IC is facilitated.

Claims (1)

A pulse generating means, first storage means 9 for temporarily storing an input signal a in synchronization with a pulse output from the pulse generating means, and temporarily storing the contents of the first storage means in synchronization with the pulse. Second storage means (11) for storing, first exclusive logic means (10) for taking exclusive logic of the signal corresponding to the input signal and the contents of the storage of the first storage means, and the first and second memories. And second exclusive logic means 12 for taking exclusive logic of two signals each representing the respective stored contents of the means, wherein the pulse widths of the respective outputs of the first and second exclusive logic means are equal to each other. And controlling the repetition frequency of the pulse so as to output the pulse to the regeneration clock while eliminating the phase difference between the input signal and the pulse.

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