JP3477375B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention protects an integrated circuit portion including a semiconductor element such as a transistor, secures an electrical connection to an external device, enables higher density mounting, and allows external mounting. The present invention relates to a semiconductor device with less influence of noise and unnecessary radiation to the outside and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, as electronic devices have become smaller and more sophisticated, semiconductor devices have been required to have smaller size, higher density, and higher speed. Therefore, for example, LOC (lead-on-chip) and SON (small outline non-lead) are used as memory packages.
, Etc., or μBG using TAB tape
A (micro ball grid array)
6-504408) has been developed.

A conventional semiconductor device called μBGA and its manufacturing method will be described below with reference to FIG. FIG. 5 is a sectional view showing a conventional semiconductor device called a μBGA. In FIG. 5, 101 is a semiconductor chip containing a semiconductor element such as a transistor, 102 is a wiring circuit sheet provided on the semiconductor chip 101, and 10 is a wiring circuit sheet.
3 is a flexible low elastic modulus material interposed between the semiconductor chip 101 and the wiring circuit sheet 102, 104 is a partial lead included in the wiring circuit sheet 102, 105 is an electrode included in the semiconductor chip 101, and 106 is a wiring circuit sheet 102.
And an external electrode for connecting the semiconductor device and an external device. As shown in FIG. 5, a semiconductor device called μBGA has a structure in which a wiring circuit sheet 102 is bonded onto a semiconductor chip 101 via a low elastic modulus material 103, and an electrode 105 of the semiconductor chip 101 and a wiring circuit sheet. The external electrode 106 of 102 and the partial lead 104
Are electrically connected via.

Next, a conventional method of manufacturing a semiconductor device called μBGA will be described with reference to FIG. First, the external electrode 106 and the external electrode 106 are formed on the semiconductor chip 101.
A wired circuit sheet 102 having a partial lead 104 extended from the substrate is placed via a low elastic modulus material 103.
Next, by the conventional thermocompression bonding technique or ultrasonic bonding technique usually used when electrically connecting in the "TAB" (tape automated bonding) work,
The partial lead 104 and the electrode 105 are electrically connected.
A semiconductor device called μBGA was manufactured by the above method.

[0005]

However, according to the above conventional semiconductor device, the electrode 105 and the partial lead 1 are provided.
Since 04 has a structure that is not electrically shielded, the semiconductor chip 101 is easily affected by noise components from the outside, and unnecessary radiation of the semiconductor chip 101 itself increases, which is not suitable for high-speed operation. Had.

In view of the above problems of the prior art, the present invention uses a metal wiring layer electrically connected to a reference potential electrode of a semiconductor chip as an electrical shielding layer, so that it is affected by noise components from the outside. It is an object of the present invention to provide a semiconductor device that is difficult and that can reduce unnecessary radiation of the semiconductor device itself, and a manufacturing method thereof.

[0007]

In order to achieve this object, a semiconductor device according to the present invention includes a semiconductor chip in which an electrode and a reference potential electrode connected to a reference potential are arranged on a main surface, A first insulating layer which is provided on the surface and in which an upper corresponding portion of the electrode and an upper corresponding portion of the reference potential electrode are respectively opened, and the first insulating layer is connected to the electrode through the opening of the first insulating layer, and The wiring extending to the insulating layer and the external electrode terminal provided on the first insulating layer and connected to the wiring for transmitting and receiving a signal to and from an external device, and covering the electrode and the wiring. A second insulating layer is formed in which the upper corresponding portion of the reference potential electrode and the upper corresponding portion of the external electrode terminal are respectively opened, and the second insulating layer is covered and the reference potential electrode is electrically connected through the opening of the second insulating layer. And a conductive layer electrically connected to each other.

As a result, the conductive layer electrically connected to the reference potential electrode is provided on the second insulating layer that covers the wiring and the electrodes of the semiconductor chip, so that it is affected by noise components from the outside. It becomes a semiconductor device that is difficult to generate and does not easily generate unnecessary radiation from the semiconductor chip itself.

Here, it is preferable that the semiconductor device of the present invention further comprises a protective film which covers the conductive layer and has an opening corresponding to the upper portion of the external electrode terminal. As a result, the portions other than the external electrode terminals are covered with the protective film, so that disconnection or short circuit of the wiring in the portions other than the external electrode terminals is prevented, and the semiconductor device has high reliability.

In the semiconductor device of the present invention, the protruding electrode may be provided on the external electrode terminal. Thereby, a signal can be more reliably transmitted and received between the semiconductor device and the external device via the protruding electrode.

Further, in the method of manufacturing a semiconductor device according to the present invention, the first insulating layer is provided on the main surface of the semiconductor chip having the electrode and the reference potential electrode connected to the reference potential and the corresponding portion above the electrode and the reference. A step of forming the corresponding upper part of the potential electrode in an open state, a wiring connected to the electrode through the opening of the first insulating layer and extending to the first insulating layer, and a first insulating layer Forming a second insulating layer that covers the electrodes and the wiring and opens the corresponding upper part of the reference potential electrode and the corresponding upper part of the external electrode terminal, respectively. And a step of forming a conductive layer which covers the second insulating layer and is electrically connected to the reference potential electrode through the opening of the second insulating layer.

According to this method, since the conductive layer is formed on the second insulating layer and the conductive layer is electrically connected to the reference potential electrode at the same time, a dedicated process for connecting the conductive layer and the reference potential electrode is performed. It can be unnecessary. Therefore, with less man-hours, it is less likely to be affected by external noise components,
Moreover, it is possible to manufacture a semiconductor device in which unnecessary radiation from the semiconductor chip itself is unlikely to occur.

Here, it is preferable that the method for manufacturing a semiconductor device of the present invention further comprises the step of forming a protective film covering the conductive layer and opening the corresponding upper part of the external electrode terminal. As a result, the portions other than the external electrode terminals are covered with the protective film, so that disconnection or short circuit of the wiring in the portions other than the external electrode terminals can be prevented, and a highly reliable semiconductor device can be obtained.

The method of manufacturing a semiconductor device according to the present invention is
A protruding electrode may be provided on the external electrode terminal. This makes it possible to obtain a semiconductor device capable of more reliably transmitting and receiving a signal between the semiconductor device and an external device via the protruding electrode.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device and a method of manufacturing the same according to the present invention will be described with reference to the drawings. Figure 1
(A) is a perspective view showing the outline of the semiconductor device according to the present invention by partially opening the solder resist, the shielding metal layer, and the second insulating layer, and partially removing the metal balls,
FIG. 1B is a sectional view taken along the line I-I of FIG.

In FIGS. 1A and 1B, 10 is a semiconductor chip having a semiconductor element such as a transistor, 11A.
Is a normal electrode provided on the outer periphery of the main surface of the semiconductor chip 10 for exchanging signals with the outside, and 11B is provided on the outer periphery of the main surface of the semiconductor chip 10 with a reference potential of the semiconductor chip 10. Connected reference potential electrode,
Reference numeral 12 denotes a normal electrode 11 on the main surface of the semiconductor chip 10.
It is a passivation film provided by exposing A and the reference potential electrode 11B.

Further, 20 is a first insulating layer formed on the main surface of the semiconductor chip 10, 21 is a first insulating layer formed on the first insulating layer 20, and the first electrode 11A and the reference potential electrode 11B are exposed. Opening portions, 22A are metal wirings connected to the normal electrode 11A in the first opening portion 21 and extending onto the first insulating layer 20, and 22B are connected to the reference potential electrode 11B in the first opening portion 21 and are connected to the first potential layer 11B. Metal wirings 23A and 23B extending onto the insulating layer 20 are lands integrally formed on one end of the metal wirings 22A and 22B on the first insulating layer 20, respectively.

Further, 24 is a second insulating layer formed by exposing the lands 23A and 23B and the metal wiring 22B on the reference potential electrode 11B on the main surface of the semiconductor chip 10.
Reference numeral 5 is a second opening formed in the second insulating layer 24 to expose the lands 23A and 23B, and 26 is formed in the second insulating layer 24 to expose the metal wiring 22B on the reference potential electrode 11B. The third opening 27 is formed on the second insulating layer 24, and the metal wiring 2 is formed in the third opening 26.
A shield metal layer electrically connected to the reference potential electrode 11B via 2B, a solder resist 28 formed by exposing the lands 23A and 23B on the main surface of the semiconductor chip 10, and 29 on the lands 23A and 23B. Are metal balls bonded to each.

Here, the semiconductor device of the present invention is characterized in that the shielding metal layer 27 formed on the second insulating layer 24 so as to cover the normal electrode 11A and the metal wiring 22A of the semiconductor chip 10 is They are electrically connected as follows. That is, the shielding metal layer 27 is connected to the reference potential of the semiconductor chip 10 through the metal wiring 22B and the reference potential electrode 11B in that order, and is also connected to the corresponding land 23B of the lands that are external electrode terminals. ing. Further, after the semiconductor device is mounted on the external device, the shielding metal layer 27 is connected to the metal wiring 22B and the land 2.
3B and the metal balls 29 in order, and the semiconductor chip 1
It is connected to the reference potential of the external device that is equal to the reference potential of 0. Therefore, due to the shielding metal layer 27 having a potential equal to the reference potential of the semiconductor device, it is less susceptible to noise components from the outside, and the semiconductor chip 10 is not affected.
A semiconductor device that can reduce unnecessary radiation from itself is realized.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. Figure 2
(A)-(d) is sectional drawing which shows each process until a plating resist pattern formation in the manufacturing method which concerns on this invention, respectively.

First, as shown in FIG. 2A, on the main surface of the semiconductor chip 10 on which the normal electrode 11A and the reference potential electrode 11B are exposed and the passivation film 12 is provided,
The photosensitive insulating material 30 is applied to a thickness of, for example, about 100 μm. Here, the photosensitive insulating material 30 may be a polymer having photosensitivity and insulation, such as ester bond type polyimide or acrylate epoxy.

Next, as shown in FIG. 2B, the photosensitive insulating material 30 is patterned by sequentially performing drying, exposure and development, and the normal electrode 11A and the reference potential electrode 11B.
First insulating layer 2 having first opening 21 exposing
Form 0.

Next, as shown in FIG. 2C, a thin film metal layer 31 made of, for example, Ti / Cu, 0.05 μ, is formed on the entire main surface of the semiconductor chip 10 by a vacuum deposition method.
It is formed to a thickness of about m. Here, instead of the vacuum deposition method, electroless plating method, sputtering method, or CV
The D method may be used.

Next, as shown in FIG. 2D, a negative photosensitive resist is applied on the thin film metal layer 31 and exposed to light,
A portion of the finished product other than the desired pattern portion, that is, the photosensitive portion is cured. After that, the desired pattern part,
That is, the plating resist pattern 32 is formed by removing the unexposed portion. Although a negative photosensitive resist is used here to form the plating resist pattern 32, a positive photosensitive resist may be used.
In this case, a black-and-white inverted photomask is used at the time of exposure.

3 (a) to 3 (d) are cross-sectional views showing respective steps from the formation of the thick metal layer to the formation of the second insulating layer in the manufacturing method according to the present invention.

After the step shown in FIG. 2D, the process shown in FIG.
As shown in (a), the thin film metal layer 3 other than the portion where the plating resist pattern 32 is formed is formed by electrolytic plating.
A thick metal layer 33 is selectively formed on the first layer 1. here,
The thick metal layer 33 is formed to a thickness of about 20 μm using Cu, for example.

Next, as shown in FIG. 3B, the plating resist pattern 32 is melted and removed.

Next, as shown in FIG. 3 (c), after the entire surface of Cu is etched using an etching solution for melting the thin film metal layer 31 and the thick film metal layer 33, for example, a cupric chloride solution, EDTA is used. The entire surface of Ti is etched using a solution. As a result, the thin film metal layer 31 having a smaller layer thickness than the thick film metal layer 33 is removed first. Therefore, in each of the desired regions, the thick film metal layer 33 is formed.
And metal wirings 22A and 22 composed of a thin film metal layer 31 and
B, lands 23A and 23B are formed. Here, after removing the plating resist pattern 32, the thick film metal layer 33 may be protected by forming an etching resist on a desired pattern using a photolithography technique.

Next, as shown in FIG. 3D, after a photosensitive insulating material is applied to the entire main surface of the semiconductor chip 10, the first insulating layer 20 shown in FIG. 2B is formed. The second insulating layer 24 is formed in the same manner as the step. Due to the formed second insulating layer 24, the lands 23A and 23B and the reference potential electrode 1 are formed on the main surface of the semiconductor chip 10.
The metal wiring 22B on 1B is exposed and the remaining portion is protected. At this time, the second opening 25 is formed in the lands 23A and 23B, and the third opening 26 is formed in the metal wiring 22B on the reference potential electrode 11B.

FIGS. 4A to 4D are cross-sectional views showing respective steps from the formation of the shielding metal layer to the metal ball bonding in the manufacturing method according to the present invention.

After the step shown in FIG. 3D, the process shown in FIG.
As shown in (a), a shielding metal layer 27 made of, for example, Cu is formed to a thickness of about 0.5 μm on the entire main surface of the semiconductor chip 10 by a vacuum evaporation method. As a result, the shielding metal layer 27 is formed on the second insulating layer 2 respectively.
The metal wiring 2 in the third opening 26 formed in
2B is electrically connected to the reference potential electrode 11B via 2B, and the lands 23A, 2 are formed in the second opening 25.
It is electrically connected to 3B. Here, instead of the vacuum vapor deposition method, an electroless plating method, a sputtering method, or a CVD method may be used.

Next, as shown in FIG. 4B, an etching resist pattern 34 is formed on the shield metal layer 27 in a region other than the lands 23A and 23B by a photolithography technique, and the etching resist pattern 34 is formed.
The shielding metal layer 27 not covered with is etched using, for example, a cupric chloride solution. As a result, the shielding metal layer 27 on the second opening 25, that is, the shielding metal layer 2
The portion where 7 is short-circuited with the lands 23A and 23B is removed. In this case, in order to surely remove the short-circuited portion, the etching resist pattern 34 is formed so as to have an opening larger than the second opening 25 of the second insulating layer 24.

Next, as shown in FIG. 4C, after removing the etching resist pattern 34, a solder resist 28 is formed on the main surface of the semiconductor chip 10 in regions other than the lands 23A and 23B. This exposes only the lands 23A and 23B and protects the shielding metal layer 27.

Next, as shown in FIG. 4D, the land 2
After the metal balls 29 are placed on the 3A and 23B, the metal balls 29 and the lands 23A and 23B are melted and joined. Here, as the material of the metal ball 29, solder,
Copper, nickel, or a solder-plated metal is used.

As described above, according to the method for manufacturing a semiconductor device of the present invention, the surface of the second insulating layer 24 provided so as to cover the normal electrode 11A and the metal wiring 22A of the semiconductor chip 10. A shielding metal layer 27 is formed on the second insulating layer 24, and at the same time, a third opening 26 is formed in the second insulating layer 24.
At, the shielding metal layer 27 and the reference potential electrode 11B of the semiconductor chip 10 are electrically connected. By this,
It is possible to eliminate a dedicated process for electrically connecting the shielding metal layer 27 and the reference potential electrode 11B. Therefore, the shielding metal layer 27 makes it possible to manufacture a semiconductor device which is less likely to be affected by noise components from the outside and which can reduce unnecessary radiation from the semiconductor chip 10 itself, by reducing the number of steps and at low cost.

Although a liquid material is applied as the photosensitive insulating material 30 in the above description, a photosensitive material and an insulating material formed in advance in a film shape may be used instead. . In this case, a film-shaped photosensitive insulating material 30 is attached on the main surface of the semiconductor chip 10, exposed and developed to form the first opening 21 in the first insulating layer 20, The normal electrode 11A and the reference potential electrode 11B of the semiconductor chip 10 are exposed.

Instead of the photosensitive insulating material 30, an insulating material having no photosensitivity may be used. In this case,
The semiconductor chip 1 is formed by mechanical processing such as laser, plasma, or sandblasting or chemical processing such as etching.
The normal electrode 11A of 0 and the reference potential electrode 11B may be exposed.

Instead of the shielding metal layer 27 made of Cu, a shielding layer made of a conductive resin containing particles of Cu, Ag or the like may be used. In this case, the conductive resin is applied to the second insulating layer 24 by using a printing method, a spin coating method, or the like.
A coating layer can be formed by applying it on top.

Furthermore, the normal electrode 11A and the reference potential electrode 11
Although the case where B is provided in the outer peripheral portion on the main surface of the semiconductor chip 10 has been described, the present invention is not limited to this, and the normal electrode 11A and the reference potential electrode 11B are provided in the central portion on the main surface of the semiconductor chip 10. It is needless to say that the semiconductor device and the manufacturing method thereof according to the present invention can be applied even when the first opening 21 is formed in the first insulating layer 20 at the center thereof.

[0040]

According to the semiconductor device of the present invention, the shielding metal layer formed on the second insulating layer so as to cover the normal electrode of the semiconductor chip and the metal wiring serves as the reference electrode of the semiconductor chip. Since they are electrically connected, they are less likely to be affected by noise components from the outside, and unnecessary radiation from the semiconductor chip can be reduced.

Further, according to the method for manufacturing a semiconductor device of the present invention, the semiconductor device of the present invention can be manufactured with a small number of steps by eliminating the need for a dedicated step for electrically connecting the shielding metal layer and the reference potential electrode. can do.

[Brief description of drawings]

FIG. 1 (a) is a partial opening of some of the components,
FIG. 3B is a perspective view schematically showing a semiconductor device according to the present invention with another part of the constituent elements removed, and FIG.
It is sectional drawing in the I line.

2 (a) to 2 (d) are cross-sectional views showing respective steps up to formation of a plating resist pattern in the manufacturing method according to the present invention.

3 (a) to 3 (d) are cross-sectional views showing respective steps from the formation of the thick metal layer to the formation of the second insulating layer in the manufacturing method according to the present invention.

4 (a) to 4 (d) are cross-sectional views showing respective steps from the formation of the shielding metal layer to the metal ball bonding in the manufacturing method according to the present invention.

FIG. 5 is a cross-sectional view showing a conventional semiconductor device called μBGA.

[Explanation of symbols]

10 semiconductor chips 11A Normal electrode 11B Reference potential electrode 12 passivation film 20 First insulating layer 21 First opening 22A, 22B Metal wiring (wiring) 23A, 23B land (external electrode terminal) 24 Second insulating layer 25 Second opening 26 Third opening 27 Shielding metal layer (conductive layer) 28 Solder resist (protective film) 29 Metal balls (protruding electrodes) 30 Photosensitive insulating material 31 Thin film metal layer 32 plating resist pattern 33 Thick film metal layer 34 Etching resist pattern

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshifumi Nakamura 1-1 Sachimachi, Takatsuki, Osaka Prefecture Matsushita Electronics Industrial Co., Ltd. (72) Takahiro Kumakawa 1-1, Sachimachi Takatsuki, Osaka Matsushita Electronics Kogyo Co., Ltd. (56) Reference JP-A-8-31982 (JP, A) JP-A-10-22411 (JP, A) JP-A-10-289966 (JP, A) JP-A-8-330356 ( JP, A) JP 11-176876 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 23 / 12,21 / 60 H05K 9/00

Claims (6)

(57) [Claims] 1. A semiconductor chip in which an electrode and a reference potential electrode connected to a reference potential are arranged on a main surface, and a corresponding upper portion of the electrode and the reference potential electrode which are provided on the main surface. A first insulating layer having upper corresponding portions opened respectively; a wire connected to the electrode through the opening of the first insulating layer and extending above the first insulating layer; An external electrode terminal provided on the first insulating layer to be connected to the wiring for transmitting and receiving a signal to and from an external device; and a portion corresponding to above the reference potential electrode and covering the electrode and the wiring. A second insulating layer having openings corresponding to upper portions of the external electrode terminals, and a second insulating layer that covers the second insulating layer and is electrically connected to the reference potential electrode through the opening of the second insulating layer. And a conductive layer. Conductor device. 2. The semiconductor device according to claim 1, further comprising a protective film covering the conductive layer and having an opening corresponding to an upper portion of the external electrode terminal. 3. The semiconductor device according to claim 1, wherein a protruding electrode is provided on the external electrode terminal. 4. A first insulating layer is formed on the main surface of a semiconductor chip having an electrode and a reference potential electrode connected to a reference potential, and the upper corresponding portion of the electrode and the upper corresponding portion of the reference potential electrode are opened respectively. And the step of forming in the state described above, connecting to the electrode through the opening of the first insulating layer,
And wiring extending above the first insulating layer,
Providing an external electrode terminal connected to the wiring on the insulating layer, and covering the electrode and the wiring and opening an upper corresponding portion of the reference potential electrode and an upper corresponding portion of the external electrode terminal, respectively. A step of forming a second insulating layer; and a step of covering the second insulating layer and forming a conductive layer electrically connected to the reference potential electrode through an opening of the second insulating layer. A method of manufacturing a semiconductor device, comprising: 5. The method of manufacturing a semiconductor device according to claim 4, further comprising the step of forming a protective film that covers the conductive layer and opens an upper corresponding portion of the external electrode terminal. Device manufacturing method. 6. The method for manufacturing a semiconductor device according to claim 4, wherein a protruding electrode is provided on the external electrode terminal.