JP3395720B2 - Mask structure of semiconductor memory device and method of manufacturing semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask structure of a semiconductor memory device and a method of manufacturing the semiconductor memory device, and more particularly to a mask structure of the semiconductor memory device suitable for a mask ROM and a method of manufacturing the semiconductor memory device.

[0002]

2. Description of the Related Art The prior art will be described below. Here, in particular, an ion implantation data writing process of a large capacity FLATNOR type mask ROM having fine processing of sub-half micron or less will be described. In addition, NAND
The same applies to the mold.

FIG. 10 is a sectional view showing a conventional structure in a high energy ion implantation data writing process using a photoresist mask, and FIG. 11 is a sectional view in the manufacturing process thereof.
FIG. 12 is a diagram for explaining a conventional problem when the code data is densely distributed.

As shown in FIGS. 10 and 11, in order to write OFF in the middle bit of the FLAT cell (increase the threshold voltage), it is necessary to penetrate through the interlayer insulating film 4 and directly under the gate oxide film 2. Boron is implanted to a depth of 05 to 0.1 μm, but as miniaturization progresses, the influence on the threshold voltage of ON bits adjacent to the left and right cannot be ignored.

For example, the polycide gate electrode 3 as a base has a pitch of 0.28 μmL / S (line and space), the total film thickness of (interlayer insulating film 4 + polycide gate electrode 3 + gate oxide film 2) is 0.6 μm, When the data aperture is 0.24 μm, boron is 250 to 300 keV
With a accelerating voltage of 1.0 to 2.0E14 cm ^−2, but at this time, since boron spreads laterally in the vicinity of the projection range (hereinafter abbreviated as Rp) directly below the gate oxide film 2, it is adjacent. The threshold voltage of the ON bit rises by 0.1 to 0.3v. Then, in the worst case, the sense amplifier circuit makes an erroneous decision, and the ON bit is turned off.
It can be recognized as an F bit. Therefore, in the conventional technology,
There is a problem that a stable yield of devices cannot be obtained.

To solve this, for example, Nikkei Microdevices December 1991 P. 104 to 109, thin the interlayer insulating film 4, and
A method of lowering the acceleration voltage, and JP-A-5-48042.
Japanese Patent Application Laid-Open No. 5-48045 discloses a method of forming an opening smaller than the minimum resolution dimension by the two-layer resist method.

However, when the fine processing of sub-half micron or less (0.24 μm or less) is performed with the increase in capacity, even with these methods, the adjacent bits are damaged due to the spread of ions in the lateral direction in the vicinity of Rp. It has become difficult to suppress the fluctuation of the threshold voltage to a level at which the sense amplifier circuit does not make an erroneous determination.

Another problem has arisen with the miniaturization. That is, although the write data pattern varies depending on the customer, there are always dense areas and sparse areas (not shown) as shown in FIG. When the light exposure technique is used in such a state, if a sparse pattern is opened as the mask passes, as shown in FIG. 12B in a dense place as shown in FIG. Due to the proximity effect due to the diffraction of light, overexposure occurs, and the resist in the portion that separates the opening becomes thin. For this reason, in an extreme case, as shown in FIG.
Further, there is a problem that the collapsed mask becomes an implantation mask, and ions are not implanted where they should be implanted.

In the prior art, because of the above problems, it is difficult to reduce the chip size and increase the capacity by further miniaturization.

[0010]

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks of the prior art, and particularly in the vicinity of the projection range directly under the gate oxide film when writing data by high energy injection through the interlayer film. A new semiconductor that can control only the threshold voltage of a desired data write bit with high accuracy without affecting the threshold voltage of adjacent bits by suppressing the spread of ions in the lateral direction. A mask structure of a memory device and a method of manufacturing a semiconductor memory device are provided.

Another object of the present invention is that when the data write mask is a photoresist film, the resist opening becomes considerably larger than the target due to the optical proximity effect in the area where the write data is dense, and the openings are separated from each other. Even if the resist becomes thin, by forming the cross-sectional shape of the opening into an inverted triangle or a trapezoidal trapezoid, the mask can have a shape that spreads toward the bottom of the opening. Thus, it is possible to provide a novel mask structure for a semiconductor memory device and a method for manufacturing the semiconductor memory device in which the resist pattern collapse is suppressed and the yield is improved.

[0012]

In order to achieve the above-mentioned object, the present invention basically adopts the technical constitution as described below.

That is, in the first aspect of the mask structure of the semiconductor memory device according to the present invention, a plurality of MOS transistors are arranged on the substrate, and a resist mask is selectively used in the channel portions of these predetermined transistors to selectively. A mask structure of a semiconductor memory device in which data is written by performing ion implantation, wherein a sectional shape of an opening of the resist mask for writing data is tapered. And, in the second aspect,
A mask structure of a semiconductor memory device in which a plurality of MOS transistors are arranged on a substrate, and data is written by selectively performing ion implantation by using a resist mask in a channel portion of these predetermined transistors, The cross-sectional shape of the opening of the resist mask for writing data is formed to be large on the front surface side of the substrate, and is formed in an inverted triangular shape in which no opening is formed on the transistor side, A third aspect is a semiconductor memory device in which a plurality of MOS transistors are arranged on a substrate and data is written by selectively ion-implanting a channel portion of these predetermined transistors using a resist mask. In the mask structure of FIG. 3, the cross-sectional shape of the opening of the resist mask for writing data is shown on the substrate surface. Formed larger on the side, which is characterized in that formed small in transistor side, or,
The fourth aspect is disposed a plurality of MOS transistors on the base plate, the mask using the mask to the channel portion of a given transistor, the semiconductor memory device for writing data by performing selective ion implantation In the structure, an opening for writing data is provided in an interlayer insulating film formed on the entire surface so as to cover the transistor, and a cross-sectional shape of the opening is formed to be large on the front surface side of the substrate. It is characterized in that it is formed in an inverted triangular shape in which no opening is formed on the gate.

According to the first aspect of the method for manufacturing a semiconductor memory device of the present invention, a plurality of MOS transistors are arranged on a substrate, and a resist mask is selectively used for the channel portions of these predetermined transistors to selectively remove them. A method of manufacturing a semiconductor memory device in which data is written by performing ion implantation, wherein a cross-sectional shape of an opening of the resist mask for writing data is formed to be large on a front surface side of a substrate and is formed on a transistor side. And a second step of performing an ion implantation through the opening formed in the first step, and a second step of processing into an inverted triangular shape in which the opening is not formed. In the second aspect, a plurality of MOS transistors are arranged on the substrate, and a resist mask is used for the channel portions of these predetermined transistors to selectively erase the transistors. A method of manufacturing a semiconductor memory device in which data writing is performed by performing an ion implantation, wherein a cross-sectional shape of an opening of the resist mask for writing data is formed large on a front surface side of a substrate and And a second step of performing ion implantation through the opening formed in the first step,
And a third aspect,
In the first step, an opening is formed in the resist mask by etching,
Further, a fourth aspect is characterized in that the resist mask is processed by an electron beam direct writing method in the first step, and a fifth aspect is that a plurality of MOS transistors are arranged on a substrate. A method for manufacturing a semiconductor memory device in which data is written by selectively performing ion implantation using a mask on a channel portion of these predetermined transistors, which is formed on the entire surface so as to cover the transistors. An opening for writing data is provided in the interlayer insulating film, and the cross-sectional shape of the opening is formed to be large on the front surface side of the substrate and etched in an inverted triangular shape in which no opening is formed on the gate. a first step, Ru der those comprising a, a second step of performing ion implantation through an opening formed in the first step.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION The mask structure of a semiconductor memory device according to the present invention is particularly applicable to a region where data writing is to be performed in an ion implantation data writing process of a large capacity mask ROM having fine processing of sub-half micron or less. The cross-sectional shape of the mask opening is an inverted triangle or an inverted trapezoid.

As a result, when data is written by high-energy injection through the interlayer film, the spread of ions in the lateral direction in the vicinity of the projection range (hereinafter abbreviated as Rp) directly below the gate oxide film is suppressed, and adjacent bits are adjacent to each other. The threshold voltage of only the desired data write bit can be stably controlled without affecting the threshold voltage.

When the data write mask is a photoresist film, the resist opening becomes considerably larger than the target due to the optical proximity effect in the area where the write data is dense, and the resist separating the openings becomes thin. Even in such a case, by making the cross-sectional shape of the opening into an inverted triangle or a trapezoidal trapezoid, the mask becomes a shape that spreads toward the bottom of the opening, which enhances the adhesion to the base,
The resist pattern collapse can be suppressed, and the yield can be improved.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific examples of a mask structure of a semiconductor memory device and a method of manufacturing the semiconductor memory device according to the present invention will be described in detail below with reference to the drawings.

(First Embodiment) FIG. 1 is a sectional view showing the structure of a first embodiment of the present invention, FIG. 2 is a sectional view showing a manufacturing process, and FIG. 3 is a code data densely distributed. It is a diagram showing the effect of the present invention in the case of, in these figures, a plurality of MOS transistors are arranged on the substrate, using a resist mask in the channel portion of these predetermined transistors,
In the mask structure of a semiconductor memory device in which data is written by selectively performing ion implantation, the cross-sectional shape of the opening 6A of the resist mask 6 for writing data has a taper T. A mask structure of a semiconductor memory device is shown, and an opening 6 of the resist mask 6 for writing the data is shown.
The cross-sectional shape of A is formed large on the surface 11 side of the substrate 1,
Inverted triangle 21 in which no opening is formed on the transistor 12 side
1 shows a mask structure of a semiconductor memory device characterized by being formed into a shape, and further, a plurality of MOS transistors are arranged on a substrate, and a resist mask is used for a channel portion of these predetermined transistors to selectively A method for manufacturing a semiconductor memory device in which data is written by performing ion implantation, wherein a cross-sectional shape of an opening 6A of the resist mask 6 for writing data is formed large on a surface 11 side of a substrate. Including a first step of processing into an inverted triangular shape 21 in which no opening is formed on the transistor 12 side, and a second step of performing ion implantation through the opening 6A formed in the first step. A method of manufacturing a semiconductor memory device is described.

The first specific example will be described in more detail below.

The ion implantation data writing process of a large capacity FLATNOR type mask ROM having fine processing of sub-half micron or less will be described here, but the present invention can be similarly applied to the NAND type. it can.

The cross-sectional shape of the opening of the present invention has an inverted triangular cross-sectional shape obtained by taper-etching the first resist film 6 using the second resist film 5 as a mask. p + diffusion layer 7 does not reach the adjacent bit,
It has a structure that suppresses fluctuations in threshold voltage.

Next, the manufacturing method of the first embodiment of the present invention will be described.

As shown in FIG. 1, after a gate oxide film 2 is formed on the P-type silicon substrate 1 in a thickness of 0.005 to 0.03 μm, a polycide gate electrode 3 is formed to a thickness of 0.25 to 0.40.
and an L / S of 0.15 to 0.24 μm. Subsequently, when the interlayer insulating film 4 is formed to have a thickness of 0.3 to 0.7 μm,
The base of the mask ROM is completed.

Next, after the first and second resist films 6 and 5 are applied, an opening 5A of 0.15 to 0.24 .mu.m is formed in the second resist film 6 by the light exposure technique only in the write data area. Form.

Subsequently, the first resist film 6 is taper-etched by using the second resist film 5 as a mask so that the cross-sectional shape of the first resist film 6 becomes an inverted triangle 21.

Then, the acceleration voltage of 100 to 380 keV
And dose 1.0-3.0E14cm ^-2Inject boron
Then, the p + diffusion layer 7 is formed.

Here, the opening 6A of the first resist film 6 is formed.
Since the cross-sectional shape is a reverse triangle, the boron implantation region shifts toward the interlayer insulating film 4 side as the distance from the vertex of the reverse triangle increases. Therefore, even if there is a lateral spread near Rp, it does not reach the P-type silicon substrate 1 of the adjacent bit, so that it is possible to suppress the influence on the threshold voltage of the adjacent transistor.

Further, if a sparse pattern is opened according to the mask, in a dense area as shown in FIG.
As shown in FIG. 12B, due to the proximity effect due to the diffraction of light, overexposure occurs and the resist in the portion separating the opening becomes thin, but the cross-sectional shape of the opening of the mask is an inverted triangle, that is, the opening bottom. Since it is formed in a shape that widens toward the end, the adhesion of the mask to the base can be improved as compared with the conventional technique, resist pattern collapse can be suppressed, and the yield can be stabilized.

(Second Embodiment) FIG. 4 is a sectional view showing a structure of a second embodiment of the present invention, and FIG. 5 is a sectional view showing a manufacturing method thereof.

The difference between this specific example and the first specific example is that the electron beam direct writing method is used for producing a data write mask. Thereby, the process can be simplified as compared with the multilayer resist method of the first specific example.

That is, as shown in FIG. 5B, the shape of the opening is made into an inverted triangular shape by gradually narrowing the electron beam from the surface of the first resist film 5 toward the interlayer insulating film 4. To do.

(Third Concrete Example) The concrete example of FIG. 6 is an example in which the shape of the opening is formed slightly larger than that of the first concrete example to form an inverted trapezoidal shape. FIG. FIG.

Therefore, in the mask structure of the semiconductor memory device of this specific example, a plurality of MOS transistors are arranged on the substrate, and the resist mask is used for the channel portions of these predetermined transistors to selectively perform ion implantation. Thus, in the mask structure of the semiconductor memory device for writing data, the cross-sectional shape of the opening 6B of the resist mask for writing data is formed large on the surface 11 side of the substrate 1 and on the transistor 12 side. Further, in the method for manufacturing the semiconductor memory device of this specific example, a plurality of MOS transistors are arranged on the substrate, and a resist mask is provided on the channel portions of these predetermined transistors. Is a method of manufacturing a semiconductor memory device in which data is written by selectively performing ion implantation. The first step of forming the cross-sectional shape of the opening 6B of the resist mask 6 for writing data large on the front surface 11 side of the substrate and small on the transistor 12 side, and the first step And a second step of performing ion implantation through the formed opening 6B.

(Fourth Embodiment) FIG. 7 is a sectional view showing the structure of the fourth embodiment of the present invention, and FIG. 8 is a sectional view showing the manufacturing method thereof.

The difference between this specific example and the above-described specific examples is that ion implantation is performed using the interlayer insulating film as a mask. Thereby, the process can be simplified as compared with the above-mentioned multilayer resist method. Furthermore, since ion implantation can be performed with an accelerating voltage sufficient to penetrate the polycide gate electrode 3, the lateral spread of the ions in the vicinity of Rp can be reduced to the first and second directions.
There is an effect that it can be further suppressed as compared with the specific example.

As shown in FIG. 8B, after the opening 16A is formed in the first resist film 16 by using the conventional light exposure technique, the interlayer insulating film 4 is taper-etched by the dry etching technique. A hole 4B having an inverted trapezoidal cross section can be obtained. The hole 4B of the interlayer insulating film 4 may be filled with, for example, a BPSG film after data writing.

Therefore, in the mask structure of the semiconductor device of this specific example, a plurality of MOS transistors are arranged on the substrate, and a channel portion of these predetermined transistors is masked to selectively perform ion implantation. A mask structure of a semiconductor memory device for writing data, comprising:
An opening 4 for writing data is formed in the interlayer insulating film 4 formed on the entire surface so as to cover the transistor 12.
B is provided, and the sectional shape of the opening 4B is formed to be large on the surface 11 side of the substrate 1 and small on the gate 3.

Further, in the mask structure of the semiconductor device of this specific example, a plurality of MOS transistors are arranged on the substrate,
A method of manufacturing a semiconductor memory device in which data is written by selectively performing ion implantation by using a mask for a channel portion of these predetermined transistors, which is formed on the entire surface so as to cover the transistor 12. An opening 4B for writing data is provided in the interlayer insulating film 4, and a cross-sectional shape of the opening 4B is formed to be large on the surface 11 side of the substrate 1 and etched small on the gate 3. It is characterized by including a step and a second step of performing ion implantation through the opening 4B formed in the first step.

(Fifth Specific Example) The specific example of FIG. 5 is an example in which the cross-sectional shape of the opening is formed in an inverted triangular shape.
FIG. 4 is a sectional view showing the structure.

Therefore, in the mask structure of the semiconductor memory device of this specific example, a plurality of MOS transistors are arranged on the substrate, and the mask is used for the channel portions of these predetermined transistors to selectively perform ion implantation. In a mask structure of a semiconductor memory device for writing data in, the interlayer insulating film 4 formed on the entire surface so as to cover the transistor 12 is provided with an opening 4A for writing data, and the opening is formed. The cross-sectional shape of the portion 4A is
It is characterized in that it is formed large on the surface 11 side of the substrate 1 and formed in an inverted triangular shape with no opening formed on the gate 3.

Further, in the method of manufacturing the semiconductor memory device of this specific example, a plurality of MOS transistors are arranged on the substrate, and the ion implantation is selectively performed by using a mask in the channel portions of these predetermined transistors. A method of manufacturing a semiconductor memory device in which data is written by means of an opening 4A for writing data in an interlayer insulating film 4 formed on the entire surface so as to cover the transistor 12.
And the cross-sectional shape of the opening 4A is
Forming a large size on the surface 11 side of the gate 3 and etching into an inverted triangular shape without forming an opening on the gate 3, and a second step of performing ion implantation through the opening 4A formed in the first step. And the steps of.

[0043]

Since the mask structure of the semiconductor memory device and the method of manufacturing the semiconductor memory device according to the present invention are configured as described above, when data writing is performed by high energy implantation of the interlayer film through, directly under the gate oxide film. By suppressing the spread of ions in the lateral direction near the projection range, it is possible to control the threshold voltage of only the desired data write bit without affecting the threshold voltage of adjacent bits. became.

When the data write mask is a photoresist film, the resist opening becomes considerably larger than the target due to the optical proximity effect in the area where the write data is dense, and the resist separating the openings becomes thin. Even when the opening cross-sectional shape is formed into an inverted triangle or a trapezoidal trapezoid, the mask has a shape that spreads toward the bottom of the opening, which enhances the adhesion to the underlying layer. Disappeared and the yield improved.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a first example of the present invention.

FIG. 2 is a cross-sectional view showing the manufacturing process of the first specific example.

FIG. 3 is a diagram showing an effect of the first specific example.

FIG. 4 is a sectional view showing a structure of a second example of the present invention.

FIG. 5 is a cross-sectional view showing the manufacturing process of the second specific example.

FIG. 6 is a diagram showing a structure of a third specific example.

FIG. 7 is a sectional view showing the structure of the fourth example of the present invention.

FIG. 8 is a cross-sectional view showing the manufacturing process of the fourth specific example.

FIG. 9 is a diagram showing a structure of a fifth specific example.

FIG. 10 is a cross-sectional view showing the structure of the prior art.

FIG. 11 is a cross-sectional view showing a conventional manufacturing process.

FIG. 12 is a diagram showing a problem of the conventional technique.

[Explanation of symbols]

1 P-type silicon substrate 2 Gate oxide film 3 Gate electrode 4 Interlayer insulation film 4A, 4B opening 5 Second resist film 6 First resist film 6A, 6B opening 11 surface 12 transistors 21 inverted triangle T taper

Claims (9)

(57) [Claims] 1. A mask of a semiconductor memory device in which a plurality of MOS transistors are arranged on a substrate, and data is written by selectively performing ion implantation using a resist mask in a channel portion of these predetermined transistors. A mask structure of a semiconductor memory device, wherein a cross-sectional shape of an opening of the resist mask for writing data is tapered. 2. A mask of a semiconductor memory device in which a plurality of MOS transistors are arranged on a substrate, and a resist mask is used for a channel portion of these predetermined transistors to selectively perform ion implantation to write data. The structure is characterized in that the cross-sectional shape of the opening of the resist mask for writing data is formed to be large on the front surface side of the substrate and formed in an inverted triangular shape in which no opening is formed on the transistor side. Structure for semiconductor memory device. 3. A mask of a semiconductor memory device in which a plurality of MOS transistors are arranged on a substrate, and a resist mask is used for a channel portion of these predetermined transistors to selectively write ions to perform data writing. A mask structure of a semiconductor memory device, wherein a cross-sectional shape of an opening of the resist mask for writing data is large on the front surface side of the substrate and small on the transistor side. 4. A plurality of MOS transistors are arranged on a substrate.
Placed in the channel part of these predetermined transistors
Selective ion implantation using a mask
The mask structure of the semiconductor memory device that writes
The insulating layer formed on the entire surface to cover the transistor.
An opening for writing data is provided in the edge film.
At the same time, make the cross-sectional shape of the opening larger on the surface side of the substrate.
In the shape of an inverted triangle that does not form an opening on the gate.
A mask structure of a semiconductor memory device characterized by being formed.
Structure. 5. A plurality of MOS transistors are arranged on a substrate.
Placed in the channel part of these predetermined transistors
Selective ion implantation using a resist mask.
Method for manufacturing semiconductor memory device in which data is written by using
Of the resist mask for writing data.
The mouth of the cross-sectional shape, formed larger in the surface side of the base plate, tiger
Processed into an inverted triangle shape with no openings on the transistor side
A first step, ion implantation through an opening formed in the first step
A second step of performing the method, and a method of manufacturing a semiconductor memory device. 6. A plurality of MOS transistors are arranged on a substrate.
Placed in the channel part of these predetermined transistors
Selective ion implantation using a resist mask.
Method for manufacturing semiconductor memory device in which data is written by using
Of the resist mask for writing data.
The cross-sectional shape of the mouth is made large on the front side of the board,
Ion implantation is performed through the first step of forming small on the transistor side and the opening formed in the first step.
A second step of performing the method, and a method of manufacturing a semiconductor memory device. 7. In the first step, the etching process is performed before.
An opening is formed in the resist mask.
A method of manufacturing a semiconductor memory device according to claim 5 or 6. 8. The electron beam direct writing in the first step
A method characterized in that the resist mask is processed by a method
A method for manufacturing a semiconductor memory device according to claim 5 or 6. 9. A plurality of MOS transistors are arranged on a substrate.
Placed in the channel part of these predetermined transistors
Selective ion implantation using a mask
It is a method of manufacturing a semiconductor memory device that writes
The insulating layer formed on the entire surface to cover the transistor.
An opening for writing data is provided in the edge film.
At the same time, make the cross-sectional shape of the opening larger on the surface side of the substrate.
In the shape of an inverted triangle that does not form an opening on the gate.
A first step of etching, ion implantation through an opening formed in the first step
A second step of performing the method, and a method of manufacturing a semiconductor memory device.