TW202312447A - Memory device and method of manufacturing the same - Google Patents

Abstract

Provided is a memory device including a substrate, a plurality of word lines extending in a first direction, arranged in a second direction, disposed on the substrate; a dummy structure, adjacent to ends of the plurality of word lines, disposed on the substrate, wherein the dummy structure includes a body part that extends in the second direction; and a plurality of extension parts that extend in the first direction are connected to the body part, and are interposed between the body part and the plurality of word lines.

Description

Memory element and manufacturing method thereof

The present invention relates to a semiconductor element and its manufacturing method, and in particular to a memory element and its manufacturing method.

With the advancement of technology, all kinds of electronic products are becoming thinner and smaller, and the critical dimensions of memory components are gradually shrinking, which makes the lithography process more and more difficult. In conventional lithography processes, methods for reducing critical dimensions include using optical components with larger numerical aperture (NA), shorter exposure wavelengths (such as EUV), or interfacial media other than air (such as water immersion ). As the resolution of conventional lithography processes approaches the theoretical limit, manufacturers have turned to double-patterning (DP) methods to overcome the optical limit and increase the integration of memory devices.

However, in the current patterning method, due to the difference in pattern density between the center and the end of the array area, the etching process will face a loading effect, which will lead to inconsistent outlines of the memory cells at the center and end of the array area. resulting in electrical problems.

The present invention provides a memory element, comprising: a base; a plurality of word lines extending in a first direction and arranged in a second direction on the base; a dummy structure adjacent to ends of the plurality of word lines , located on the base, wherein the dummy structure includes: a main body extending in the second direction; and a plurality of extensions extending in the first direction and connected to the main body and between between the main body and the plurality of character lines.

The present invention provides a method for manufacturing a memory element, comprising: providing a substrate; forming a target layer and a hard mask layer on the substrate; patterning the hard mask layer to form a patterned hard mask layer, and The patterned hard mask layer includes: a plurality of first patterns, a second pattern and a plurality of third patterns, wherein the plurality of first patterns extend in a first direction and are arranged in a second direction, and the first patterns are arranged in a second direction. The two patterns are comb-shaped and located between the plurality of first patterns and the third patterns, the plurality of third patterns extend in the second direction and are arranged in the first direction; and the plurality of third patterns extend in the second direction; and a patterned hard mask layer, transferring the plurality of first patterns, the second patterns, and the plurality of third patterns to the target layer to form a plurality of word lines, comb-shaped dummy structures, and Multiple landing pads.

Based on the above, the embodiments of the present invention add dummy patterns in the array region and the routing region to reduce the loading effect between the end and the center of the array region during the etching process.

Referring to FIGS. 1A and 1B , a memory element 100 is formed on a substrate 10 . In the direction D2, the substrate 10 can be divided into a plurality of blocks A0, A1, A2, A3, . . . and so on. Each block, illustrated by block A1 , may include an array region R1 , a transition region R2 and a routing region R3 , and the transition region R2 is located between the array region R1 and the routing region R3 .

The memory device 100 includes a plurality of word lines WL and a plurality of select gates SG. One end of each word line WL is located in the array area, and the other end extends to the routing area. In some embodiments, one ends of the plurality of word lines WL are aligned with each other, and are arranged in an "I" shape; the other ends of the plurality of word lines WL are not aligned, but are arranged in a horizontal "V". type.

For example, the plurality of word lines WL includes a plurality of word lines WL ₀ , WL ₁ , WL ₂ . A plurality of word lines WL ₀ /WL ₂ are disposed in the array region R1 of the blocks A0/A2 and their ends E ₀₀ /E ₂₀ also extend to the routing region R3 , and are respectively arranged in a horizontal “V” shape. The other ends (not shown) of the plurality of word lines WL ₀ /WL ₂ are located in the array region R1 without extending to another winding region (not shown), and are respectively aligned and arranged as "I" type. A plurality of word lines WL ₁ /WL ₃ are disposed in the array region R1 of the blocks A1/A3 and their ends E ₁₀ /E ₃₀ do not extend to the routing region R3 , and are respectively aligned and arranged in an “I” shape. The other ends (not shown) of the plurality of word lines WL ₁ /WL ₃ are located in the array region R1 and extend to another winding region (not shown), and are respectively arranged in a horizontal "V" type.

The memory element 100 further includes a plurality of select gates SG, respectively disposed on two sides of the word lines WL. A plurality of selection gates SG are disposed in the array region R1.

The multiple selection gates SG include selection gates SG ₀₀ (not shown) and SG ₀₁ disposed on both sides of the multiple word lines WL ₀ , multiple selection gates SG _{10 and SG 01 disposed} on both sides of the multiple word lines WL 1 SG ₁₁ , a plurality of selection gates SG ₂₀ and SG ₂₁ disposed on both sides of a plurality of word lines WL ₂ , and a plurality of selection gates SG ₃₀ and SG ₃₁ (not shown) disposed on both sides of a plurality of word lines WL ₃ ).

The memory device 100 further includes a plurality of landing pads LP disposed in the routing region R3 as pick-ups of the word lines WL. The landing pad LP includes landing pads LP ₀₁ , LP ₂₀ , LP ₂₁ (shown on the left side of FIG. 1A ). The landing pads LP ₀₁ , LP ₂₀ , and LP ₂₁ each extend in the direction D2 and are arranged in the direction D1. Furthermore, the landing pads LP ₀₁ , LP ₂₀ , LP ₂₁ are aligned with each other in the direction D2. The landing pads LP ₀₁ and LP ₂₀ are separated from each other, disposed at the ends E ₁₀ of the plurality of word lines WL ₁ , and arranged along the direction D2. The landing pad LP ₀₁ extends from the block A1 to the block A0 , and is connected to the end E ₀₀ of part of the plurality of word lines WL ₀ . The landing pad LP ₂₀ extends from the block A1 to the block A2 , and is connected to the ends E ₂₀ of some of the plurality of word lines WL ₂ . The landing pad LP ₂₁ is disposed at the end E ₃₀ of the plurality of word lines WL ₃ , extends from the block A3 to the block A2 , and is connected to another part of the ends E ₂₀ of the plurality of word lines WL ₂ . The landing pad LP also includes other landing pads, respectively disposed on the other ends of the word lines WL ₀ and WL ₂ relative to E ₀₀ and E ₂₀ (not shown on the right side of _FIG . WL ₃ connections.

In an embodiment of the present invention, the memory device 100 further includes a dummy structure DS disposed between the routing region R3 and the array region R1 . The dummy structure DS is disposed beside a plurality of word lines WL whose ends are arranged to be flush. In FIG. 1A , the dummy structure DS may include dummy structures DS ₁ and DS ₃ . The dummy structure _DS1 is disposed in the block A1 near the end _E10 of the plurality of word lines _WL1 ; the dummy structure _DS3 is disposed in the block A3 near the end _E30 of the plurality of word lines _WL3 . The dummy structure DS may also include other dummy structures, which are respectively disposed in the blocks A0 and A2 and located beside the other ends (not shown) of the plurality of word lines WL ₀ and WL ₂ . The dummy structure DS may be floating without being connected to external circuits.

The dummy structure DS is, for example, comb-shaped. The dummy structure DS includes a main body MP and a plurality of extension parts EP. The main body portion MP is located in the transition region R2, and the main body portion MP is adjacent to the landing pad LP at a non-zero distance. The shape and orientation of the main body MP are more similar to those of the landing pad LP than the plurality of extensions EP. Both the main body MP and the landing pad LP are solid blocks. The extending direction of the main body MP is the same as the extending direction of the landing pad LP, both extending along the direction D2.

A plurality of extensions EP are located in the array region R1. The shape and the arrangement direction of the plurality of extension parts EP are more similar to the shape and arrangement direction of the word line WL than the main body part MP. The extending direction of the plurality of extending portions EP is the same as the extending direction of the word line WL, and both extend along the direction D1. The arrangement direction of the plurality of extension parts EP is also the same as the arrangement direction of the word lines WL, both of which are arranged along the direction D2. The plurality of extension parts EP are connected to the main body part MP, and are adjacent to the plurality of word lines WL at a non-zero distance. The distance d1 between the extension part EP and the plurality of word lines WL is less than 114 nm, for example, between 30 nm and 114 nm. The select gates _SG10 and _SG11 protrude from the end of the word line _WL1 , and the length L of the main body MP is smaller than the distance d3 between the select gates _SG10 and _SG11 on both sides of the word line _WL1 .

The width W ₂ of the extension portion EP is greater than twice the width W ₁ of the plurality of word lines WL, for example, 2.5 to 3.5 times the width W ₁ of the plurality of word lines WL. The width W ₃ of the main body MP is greater than the width W ₂ of the extension EP, for example, 6 to 9 times the width W ₁ of the plurality of word lines WL.

The dummy structure DS is formed by pattern transfer of a hard mask pattern (also called a dummy pattern). The arrangement of the dummy structure DS can improve the loading effect during the etching process for forming the word line WL and the landing pad LP, so that the center and the end of the array region have similar profiles. The manufacturing process of the above-mentioned memory device 100 can be described with reference to the following embodiments, but is not limited thereto.

An embodiment of the present invention provides a method for manufacturing a memory element, the steps of which are as follows. First, please refer to FIG. 2A to FIG. 5A , a substrate 10 is provided. The substrate 10 may include an array region R1 , a transition region R2 and a routing region R3 . In this embodiment, the array region R1 may be a memory array region having one or more memory cells, and the routing region R3 may be a routing region having one or more word line contacts. The transition region R2 is located between the array region R1 and the routing region R3. In an embodiment, the substrate 10 may be, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor-on-insulator (SOI) substrate. In this embodiment, the substrate 10 is a silicon substrate.

Next, the target layer 12 is formed on the substrate 10 . The target layer 12 may be a stacked layer 110 stacked in the direction D3. Specifically, as shown in the enlarged view of FIG. 5A , the stacked layer 110 may sequentially include a tunneling dielectric layer 102, a patterned floating gate layer 104, an inter-gate dielectric layer 106, and a control gate from bottom to top. layer 108 , metal layer 112 and capping layer 114 .

The material of the tunneling dielectric layer 102 can be, for example, silicon oxide. The patterned floating gate layer 104 may extend along the direction D2, and its material may include conductive material, such as doped polysilicon, non-doped polysilicon or a combination thereof. The inter-gate dielectric layer 106 can be, for example, a composite layer composed of Nitride/Oxide/Nitride/Oxide/Nitride, NONON, but the present invention is not limited thereto , this composite layer can be three layers, five layers or more layers. The material of the control gate layer 108 may include conductive material, such as doped polysilicon, non-doped polysilicon or a combination thereof. The material of the metal layer 112 can be, for example, W, TiN or a combination thereof. The material of the cap layer 114 may include a dielectric material such as silicon nitride, silicon oxynitride or a combination thereof.

Then, a sacrificial layer 14 and a hard mask layer 16 are formed on the stack layer 110 . The sacrificial layer 14 may also be referred to as a hard mask layer. The sacrificial layer 14 may be a silicon oxide layer. The hardmask layer 16 may be a single layer or multiple layers. The hard mask layer 16 is, for example, a polysilicon layer. Afterwards, a core layer 18 is formed on the hard mask layer 16 . The core layer 18 includes core patterns 18 a , 18 b , and 18 c in the array region R1 , the transition region R2 and the routing region R3 respectively. The core pattern 18a extends in the direction D1; the core patterns 18b, 18c extend in the direction D2. The direction D1 and the direction D2 are perpendicular to each other. The core pattern 18b is connected to the core pattern 18a and separated from the core pattern 18c.

In an embodiment, the core layer 18 may include a carbide layer. In another embodiment, the core layer 18 may include a carbide layer and an anti-reflection layer. The material of the carbide layer may be, for example, spin-on-carbon (SoC). The material of the anti-reflection layer can be, for example, silicon oxynitride. The method for forming the core layer 18 is, for example, first forming a carbide material layer and an anti-reflection material layer, and then forming a photoresist pattern on the anti-reflection material layer through a lithography process. In some embodiments, after forming the photoresist pattern, a trimming process is performed to reduce the width of the formed photoresist pattern. Thereafter, an etching process is performed to transfer the pattern of the photoresist pattern down to the anti-reflection material layer and the carbide material layer. After that, the photoresist pattern is removed.

Referring to FIGS. 2B to 5B and FIGS. 2C to 5C , a self-aligned double patterning (Self-Aligning Double Patterning, SADP) process is performed to form spacers 20 on the hard mask layer 16 . The material of the spacer 20 includes oxide, such as silicon oxide. In an alternative embodiment, a self-aligned quadruple patterning (SAQP) process may also be performed to form the spacers 20 with a higher pattern density. The formation method of the spacer 20 is, for example, to firstly form the spacer material layer 19 on the hard mask layer 16 and the top surface and sidewall of the core layer 18 , as shown in FIGS. 2B to 5B . An anisotropic etching process is then performed on the spacer material layer 19 to remove part of the spacer material layer 19 until the top surfaces of the hard mask layer 16 and the core layer 18 are exposed to form a layer on the sidewall of the core layer 18. spacer wall 20 . Afterwards, with the spacer 20 and the core layer 18 as the mask, the etching is continued to remove the hard mask layer 16 not covered by the spacer 20 and the core layer 18, so that the array region R1, the transition region R2 and the routing region R3 form hard mask patterns 16a, 16b, 16c, respectively. During the process of etching the hard mask layer 16 , the core layer 18 is also etched away, exposing part of the top surfaces of the hard mask patterns 16 a , 16 b , 16 c , as shown in FIGS. 2C to 5C . The hard mask pattern 16a extends in a direction D1; the hard mask patterns 16b, 16c extend in a direction D2. The hard mask pattern 16b is connected to the hard mask pattern 16a and separated from the hard mask pattern 16c.

Referring to FIG. 2D to FIG. 5D and FIG. 2E to FIG. 5E , a cutting process of the spacer 20 is performed to form spacers 20 a , 20 b , and 20 c separated from each other. The dicing process of the spacer 20 is described as follows.

First, referring to FIGS. 2D to 5D , a mask layer 22 is formed on the sacrificial layer 14 . The mask layer 22 is, for example, a patterned photoresist layer. The mask layer 22 includes mask patterns 22a, 22b, 22c. The mask pattern 22a partially covers the array region R1; the mask pattern 22b covers part of the routing region R3 and the transition region R2; and the mask pattern 22c covers another part of the routing region R3 and the transition region R2. The mask patterns 22a, 22b, 22c are separated from each other. Between the mask patterns 22a and 22b and between the mask patterns 22a and 22c are exposed spacers 20, hard mask patterns 16a, 16b at the end of the array region R1 and at one side of the transition region R2 (near the array region R1). and a sacrificial layer 14 . Between the mask patterns 22b and 22c are exposed the spacer 20 , the hard mask patterns 16c, 16b and the sacrificial layer 14 located in the routing region R3 and on the other side of the transition region R2 (away from the array region R1 ).

Referring to FIGS. 2E to 5E, an etching process, such as an anisotropic etching process, is performed to remove the spacers 20 not covered by the mask patterns 22a, 22b, 22c to form the spacers 20a, 20b, 20c. After that, the mask patterns 22a, 22b, 22c are removed. The spacers 20 a are separated from each other and located in the array region R1 , and their respective lengths in the direction D1 are smaller than the length of the sacrificial layer 14 not covered by the hard mask pattern 16 a in the array region R1 . The spacers 20 b are located in the transition region R2 , extend in the direction D2 and are separated from each other in the direction D2 . The spacers 20 c are located in the winding region R3 , extend in the direction D2 and are separated from each other in the direction D2 .

Referring to FIG. 2F to FIG. 5H , the patterning process of the target layer 12 is performed to form target patterns 12 a , 12 b , and 12 c. The patterning process of the target layer 12 is described as follows. In the target layer 12, the hard mask layer 16' shown in FIG. 2G is used as an etching mask, and the formation method of the hard mask layer 16' can be described as follows with reference to FIG. 2F to FIG. 5G.

Referring to FIGS. 2F to 5G , a mask layer 24 is formed on the substrate 10 . The mask layer 24 is, for example, a patterned photoresist layer. The mask layer 24 has openings OP1 and OP2. The opening OP1 exposes the spacer 20a, the hard mask pattern 16a and the sacrificial layer 14 in the array region R1. The opening OP2 extends in directions D1 and D2. The shape of the opening OP2 is, for example, a double-row comb shape composed of a plurality of crosses. The opening OP2 exposes the hard mask pattern 16c and the sacrificial layer 14 in the routing region R3 in the direction D1. The opening OP2 exposes the hard mask pattern 16c in the routing region R3 in the direction D2.

Referring to FIG. 2G to FIG. 5G, the hard mask patterns 16a, 16b and 16c are patterned into the hard mask layer 16' by using the mask layer 24 and the spacer 20a as a mask. The hard mask layer 16' includes hard mask patterns 16a', 16b', 16c'. The hard mask pattern 16a' covers the array region R1; the hard mask pattern 16b' covers the transition region R2 and extends to the array region R1; the hard mask pattern 16c' covers the routing region R3.

The hard mask pattern 16b' can also be called a dummy pattern. The hard mask pattern 16b' is, for example, comb-shaped. The hard mask pattern 16b' includes a main body mp and a plurality of extensions ep. The main body mp is a solid block extending along the direction D2, located in the transition region R2, and adjacent to the hard mask pattern 16c' with a non-zero distance d2'. The plurality of extensions ep extend along the direction D1, are arranged along the direction D2, and are located in the array region R1. The plurality of extension parts ep are connected to the main part mp, and are adjacent to the hard mask pattern 16a' with a non-zero distance d1'. The width W ₃ ′ of the main body mp is greater than the width W ₂ ′ of each extension ep, and the width W _{2 ′} of each extension ep is greater than the width W ₁ ′ of each hard mask pattern 16a ′. The distance d1' between the hard mask pattern 16b' and the hard mask pattern 16a' is controlled according to the capability of the process, so as to reduce the loading effect of the subsequent etching process. For example, the distance d1' is controlled to be less than 114 nm, such as between 30 nm and 114 nm.

2H to FIG. 5H, the hard mask layer 16' is used as a mask to perform an etching process, which may be an anisotropic etching process, such as a reactive ion etching (RIE) process, so that the sacrificial layer 14 and the target Layer 12 is patterned, thereby forming a patterned oxide layer and target patterns 12a, 12b, 12c. After that, the mask layer 24 and the spacers 20a are removed. Since the distance d1' between the hard mask pattern 16b' and the hard mask pattern 16a' is controlled within an appropriate range and is a solid block, the central area of R1 in the array area can be reduced during the etching process. The loading effect between the central zone and the terminal zone makes the target pattern 12a have a similar profile between the central zone and the terminal zone.

The target pattern 12a may include a plurality of target patterns 12a ₁ . A plurality of target patterns _12a1 are located in the array region R1, extend along the direction D1, and are arranged along the direction D2.

A plurality of target patterns 12c are located in the routing region R3. The plurality of target patterns 12c includes a plurality of target patterns 12c ₀ and 12c ₁ extending along the direction D2 respectively. The plurality of target patterns 12c ₀ and 12c ₁ both extend along the direction D2 and are arranged along the direction D1. The target pattern 12c ₀ and the target pattern 12c ₁ are separated from each other and arranged in a row along the direction D2. The width of the target pattern 12c is, for example, 4 to 6 times the width _W1 of the target pattern _12a1 .

The target pattern 12b is located between the plurality of target patterns _12a1 and the plurality of target patterns 12c. The target pattern 12b is also referred to as a dummy structure, such as a comb shape. The target pattern 12b includes a main body MP and a plurality of extension parts EP. The main body MP is a solid block extending along the direction D2, located in the transition region R2, and adjacent to the target pattern 12c with a non-zero distance. The plurality of extension parts EP extend along the direction D1, are arranged along the direction D2, and are located in the array region R1. The plurality of extension parts EP are connected to the main body part MP, and are adjacent to the target pattern _12a1 at a non-zero distance d1, and adjacent to the target pattern 12c at a non-zero distance d2. The distance d1 between the extension part EP and the target pattern 12 a ₁ is less than 114 nm, for example, between 30 nm and 114 nm.

The width W ₂ of the extension EP is greater than twice the width W ₁ of the target pattern, for example, 2.5 to 3.5 times the width W ₁ of the target pattern. The width W ₃ of the main body MP is greater than the width W ₂ of the extension EP, for example, 4 to 9 times the width W ₁ of the target pattern 12 a ₁ .

Referring to FIG. 1B , the target pattern 12a may further include a plurality of target patterns 12a ₁₀ , 12a ₁₁ . The target patterns 12a ₁₀ , 12a ₁₁ are located on both sides of the target pattern 12a ₁ . The target patterns 12a ₁₀ , 12a ₁₁ are located in the array region R1, extend along the direction D1, and are arranged along the direction D2. The width of the target pattern 12a ₁₀ , 12a ₁₁ is, for example, 4 to 6 times the width W ₁ of the target pattern 12a ₁ .

Referring to FIG. 1A and FIG. 1B , in some embodiments, the target pattern 12a ₁ is a patterned stacked layer 110a including the word line WL ₁ (as shown in the partial enlarged view of FIG. 5H ). The patterned stack layer 110 a includes a tunneling dielectric layer 102 , a patterned floating gate layer 104 a , an inter-gate dielectric layer 106 a , a control gate layer 108 , a metal layer 112 a and a capping layer 114 a. In other embodiments, the tunneling dielectric layer 102 can also be patterned. The aspect ratio of the patterned stacked layer 110a is, for example, 10-12. The target patterns 12a ₁₀ and 12a ₁₁ are respectively patterned stacked layers including the selection lines SG ₁₀ and SG ₁₁ . The target patterns 12c ₀ , 12c ₁ are patterned stacked layers including the landing pad LP ₀₁ for the word line WL ₀ and the landing pad LP ₂₀ for the word line WL ₂ , respectively. The target pattern 12b is a patterned stacked layer including the dummy structure _DS1 .

Although the above embodiment uses the flash memory as an example to illustrate a series of patterning steps, the present invention is not limited thereto. In other embodiments, the patterning step can also be used to form a dynamic random access memory (DRAM) or similar target layer/film.

In summary, the embodiment of the present invention can improve the loading effect during the etching process of forming word lines and landing pads by setting the hard mask pattern (also called dummy pattern) used to form the dummy structure DS, so that the array area The center and ends of the tube have similar profiles to avoid bridging or defects. In this case, the target layer in the array area and the routing area can be patterned simultaneously, thereby forming multiple stacked structures with different pattern densities in the array area and the routing area.

10: substrate 12: target layer 12a, 12a1, 12a10, 12a11, 12b, 12c, 12c0, 12c1: target pattern 14: sacrificial layer 16, 16': hard mask layer 16a, 16a', 16b, 16b', 16c, 16c': hard mask pattern 18: core layer 18a, 18b, 18c: core pattern 19: spacer material layer 20, 20a, 20b, 20c: spacer 22, 24: mask layer 22a, 22b, 22c: mask Pattern 50: area 100: memory element 102: tunneling dielectric layer 104, 104a: floating gate layer 106, 106a: intergate dielectric layer 108, 108a: control gate layer 110, 110a: stacked layer 112, 112a : metal layer 114, 114a: cap layer A0, A1, A2, A3: block D1, D2, D3: direction DS, DS ₁ , DS ₃ : dummy structure E ₀₀ , E ₁₀ , E ₂₀ , E ₃₀ : terminal ep, EP: extension L: length LP, LP ₀₁ , LP ₂₀ , LP ₂₁ : landing pad mp, MP: main body OP1, OP2: opening R1: array area R2: transition area R3: winding area SG, SG ₀₁ , SG ₁₀ , SG ₁₁ , SG ₂₀ , SG ₂₁ , SG ₃₀ , SG ₃₁ : selection gate W ₁ , W ₁ ', W ₂ , W ₂ ', W ₃ , W ₃ ': width WL, WL ₀ , WL ₁ , WL ₂ , WL ₃ : word line d1, d1', d2, d2', d3: distance III-III, IV-IV, VV: line

FIG. 1A is a top view of a memory device according to an embodiment of the present invention. FIG. 1B is a partially enlarged view of the region 50 of FIG. 1A . 2A to 2H are top views of a manufacturing method of a memory device according to an embodiment of the present invention. 3A to 3H are cross-sectional views along line III-III of FIGS. 2A to 2H . 4A to 4H are cross-sectional views along line IV-IV of FIGS. 2A to 2H . 5A to 5H are cross-sectional views along line V-V of FIGS. 2A to 2H .

10: Base

50: area

100: memory element

A0, A1, A2, A3: blocks

D1, D2: direction

DS, DS ₁ , DS ₃ : dummy structures

E ₀₀ , E ₁₀ , E ₂₀ , E ₃₀ : end

EP: extension

LP, LP ₀₁ , LP ₂₀ , LP ₂₁ : Landing Pads

MP: Main body

R1: array area

R2: transition zone

R3: winding area

SG, SG ₀₁ , SG ₁₀ , SG ₁₁ , SG ₂₀ , SG ₂₁ , SG ₃₀ : selection gate

WL, WL ₀ , WL ₁ , WL ₂ , WL ₃ : word line

Claims (10)

A memory element comprising: base; a plurality of word lines extending in a first direction and arranged in a second direction on the base; a dummy structure on the substrate adjacent to ends of the plurality of word lines, wherein the dummy structure includes: a main body extending in said second direction; and A plurality of extension parts extend in the first direction, are connected with the main body part, and are interposed between the main body part and the plurality of word lines. The memory device according to claim 1, wherein the dummy structure is comb-shaped. The memory device according to claim 1, wherein the width of the main body portion of the dummy structure is greater than the width of each extension portion, and the width of each extension portion is greater than the width of each word line. The memory element according to claim 1, wherein the main body of the dummy structure is a solid block. The memory device according to claim 1 further includes two selection gates respectively located on two sides of the plurality of word lines, wherein the length of the main body is smaller than the distance between the two selection gates. The memory element according to claim 1, further comprising a plurality of landing pads extending in the second direction and respectively connected to other plurality of word lines, wherein the dummy structure is located between the plurality of landing pads and the Between multiple character lines. A method of manufacturing a memory element, comprising: provide the basis; forming a target layer and a hard mask layer on the substrate; The hard mask layer is patterned to form a patterned hard mask layer, and the patterned hard mask layer includes: a plurality of first patterns, a second pattern and a plurality of third patterns, wherein the a plurality of first patterns extending in a first direction and arranged in a second direction, the second patterns are comb-shaped and located between the plurality of first patterns and the third patterns, the plurality of third patterns extending in the second direction and aligned in the first direction; and Using the patterned hard mask layer, transferring the plurality of first patterns, the second patterns and the plurality of third patterns to the target layer to form a plurality of word lines, comb-like False structures and multiple landing pads. The method for manufacturing a memory element according to claim 7, wherein the second pattern includes a main body and a plurality of extensions, the main body extends in the second direction, and the plurality of extensions extends in the first direction and arranged in the second direction. The method of manufacturing a memory device as claimed in claim 8, wherein the width of the main body portion is larger than the width of each extension portion, and the width of each extension portion is larger than the width of each first pattern. The method for manufacturing a memory element according to claim 8, wherein the main body is a solid block.

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