JP3139223B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for converting an alternating current into a direct current or converting a frequency by a switching system such as a switching power supply, an inverter type fluorescent lamp, and a motor control inverter. The present invention relates to a semiconductor device having a switching semiconductor element and a control semiconductor integrated circuit that controls conduction and cutoff of the switching semiconductor element and a method of manufacturing the same.

[0002]

2. Description of the Related Art Semiconductor devices used for inverters and the like include switching power MOSFETs and IGBTs.
(A conductivity modulation type transistor or an insulated gate type bipolar transistor) or the like, and a switching semiconductor element is used.
Alternatively, a zener diode is often inserted between a gate terminal, which is a control input for adjusting the switching speed, and a ground side such as a source terminal. These techniques are described in JP-A-4-115715 and JP-A-60-1985.
139018 etc.

[0003]

When such a power switching semiconductor device is subjected to switching control by a flyback system or a voltage resonance system, if a current flows intermittently in the switching semiconductor device or the current fluctuates rapidly. Although this is not a problem with normal (small current, low speed switching) switching semiconductor devices, feedback capacitance (parasitic capacitance, coupling capacitance) between the output terminal and the control terminal of the switching semiconductor device is apparent due to the large current and high speed switching. And charging and discharging occur in this. The current due to the feedback capacitance appears at a control terminal via a gate electrode in an insulated gate semiconductor device such as a power MOS or IGBT, and appears at a base terminal in a bipolar transistor. May flow through a path on the side of a control semiconductor integrated circuit (control unit) that outputs a control signal from the control input to the control input. For this reason, the discharge current may cause the opening / closing control circuit in the preceding stage of the main switching semiconductor element to malfunction or apply a voltage higher than the guaranteed voltage to the transistors constituting the same, thereby destroying the control circuit.

By the way, in a conventional input protection circuit in which a Zener diode is connected between a control input of a main switching semiconductor element and a source terminal or the like, a forward rising voltage of the Zener diode is high and one of discharge currents is reduced. Since the section inevitably spreads to the preceding circuit, protection of the main switching semiconductor element is incomplete from the viewpoint of protection of the control section (low breakdown voltage element).

FIG. 22 schematically shows a conventional semiconductor device which performs switching. In this semiconductor device 10, the main power supply 2 is turned on / off by a power MOSFET 11 of a main switching element connected in series with a transformer 1 (only the primary side is shown). Power MOSFE
T11 is a control terminal 12 connected to the gate electrode 11G.
The semiconductor device 10 is driven to open and close by a control signal input from the semiconductor device 10, and the control signal is output from an output terminal 21 of the control unit 20 of the semiconductor device 10. The control terminal 12 and the output terminal 21 are, for example, control resistors (gate resistors) of discrete components.
15 are connected. Further, the control unit 20 controls the NP driven based on an input signal from a logic circuit (not shown).
It is composed of a push-pull circuit of an N-type transistor 22 and a PNP transistor 23. When the NPN transistor 22 is turned on and the PNP transistor 23 is turned off, the power MOSFET 11 is turned on, and when the PNP transistor 23 is turned on, the NPN transistor is turned on. When the power supply 22 is turned off, the power MOSFET 11 is in a bias 0 or reverse bias state and is turned off.

In such a semiconductor device 10, when the power MOSFET 11 is off and in a bias 0 or reverse bias state (when the drain current _ID is 0),
When the output voltage _VDS changes as shown in FIG. 23, particularly when the voltage shifts from a high voltage to a low voltage as shown in a region 31, for example, in a flyback switching power supply, a period in which the load current is small and the transformer current does not flow occurs. In such a case, the capacitance (feedback capacitance) 14 existing between the output terminal (source terminal) of the power MOSFET 11 and the control terminal 12 is discharged, and a discharge current 16 flows.
The path of the discharge current 16 is connected to the control terminal 12 of the power MOSFET 11 from the main power supply 2 via the parasitic diode of the PNP transistor 23 in the OFF state of the control unit 20 and from the control resistor 15 as indicated by the broken line arrow. Flow through Accordingly, such a discharge current flows in a direction opposite to the forward direction of the PNP transistor 23, so that the operation of the control unit 20 becomes unstable, and at the same time, when the reverse bias voltage exceeds the guaranteed voltage, the transistor 23 is damaged. May be connected. Further, since the discharge current 16 flows in the opposite direction to the operation direction of the PNP transistor 23, a delay occurs in the subsequent ON operation of the PNP transistor 23. As a result, a discrepancy occurs in the push-pull operation between the NPN transistor 22 and the PNP transistor 23, and both transistors are temporarily turned on, so that a through current flows, and current consumption in the control unit 20 increases. The problem also arises.

FIG. 24 shows a configuration of a semiconductor device 10 similar to the above, except that a bias power supply 25 is added downstream of the control unit 20. In such a semiconductor device 10 as well, the power MOSFET 1
1 is the output voltage V _DS as shown in a region 31 in FIG.
Changes, the discharge current 16 flows through the bias power supply 25, the parasitic diode of the PNP transistor 23 in the OFF state of the control unit 20, and the control resistor 15. As a result, the reverse bias voltage V _GS generated between the control terminal 12 of the power MOSFET 11 and the output terminal 13 serving as the ground terminal is expressed by the following equation (1), and the value is shown in FIG. Change so rapidly.

The reverse bias voltage V _GS = the voltage of the reverse bias power supply 25 + the reverse saturation voltage of the PNP transistor 23 of the control section 20 + the control resistor 15 × the feedback capacitance 14 × the change amount of the output voltage (dV / dt) 1) Therefore, in this case, the reverse bias voltage V _GS becomes PN
It is easy to exceed the guaranteed voltage of the P transistor 23, and the control unit 2
There is a problem that destruction of the 0 transistor or the like is more likely to occur.

As described above, the reason that the reverse bias current spreads to the control unit 20 side is that the power MOSFET described above.
In addition to the case of discharging the feedback capacitance of No. 11, there are also the following cases. Figure 26 shows a drive circuit of a H bridge driven by inductive load L ₁ four main Suichingu for IGBT (conductivity modulation type transistors) T ₁ through T _4. In this figure, D _{1 to} D ₄ are diodes for absorbing a back electromotive force at the time of cutoff, and IC _{1 to} IC ₄ are IGBTT ₁ to
The semiconductor integrated circuit of the switching control of T _4, R ₁ ~R ₄ is controlled resistor, the main power of 2 IGBTT, V _cc is the power supply of the semiconductor integrated circuit, C ₁ -C ₄ are capacitors fluctuation absorbing power V _cc It is. Now, when the IGBT (T ₂ , T ₃ ) is off and the IGBT (T ₁ , T ₄ ) is on,
Load L ₁ to a current flows in the current path shown by a broken line arrow, IGBT (T ₂₎ and the parasitic wiring inductance L ₂₁ in its current change -di / dt to the ground wire between the IGBT (T ₄₎ Is generated, and a current flows through a current path indicated by a solid arrow in the drawing.

Due to this change in current, FIGS. 26 and 2
The wiring inductance L ₁₁ and L ₁₂ shown in 7 current flows in the current path and a dotted arrow in the current path of the solid arrow with. At this time, the IGBT (T ₂ ) is off, the PNP transistor 23 of the semiconductor integrated circuit IC ₂ is on, and the NPN transistor 22 is off.

[0011] The current due to the wiring inductance L ₁₂ is PN
Although there is no particular problem because it is the forward direction with respect to P-type transistor 23, a current due to the wiring inductance L ₁₁ is P
Since the NP-type transistor 23 and the NPN transistor 22 are reverse-biased and flow through these parasitic diodes, the potential of the OUT terminal (V _CC terminal) becomes a negative potential compared to that of the GND terminal, and the semiconductor integrated circuit IC ₂
In some cases, the power supply abnormality detection circuit (comparison circuit) COM operates and the alarm signal ALM is generated. The reverse bias to the NPN transistor 22 and the PNP transistor 23 caused by the back electromotive force due to the wiring inductance causes the above-mentioned problems (malfunction of switching control, destruction of transistor, power loss due to through current, etc.). In particular, when performing high current, high speed switching,
Since -di / dt has a very large value, the above problem becomes more and more prominent.

Therefore, in the present invention, in view of the above problem, the discharge of the feedback capacitance due to the conduction / interruption of the main switching element and the reverse bias current that spreads to the control unit in the preceding stage due to the back electromotive force of the wiring inductance. It is an object of the present invention to realize a semiconductor device capable of preventing malfunction and destruction of a control unit by eliminating the influence, and further suppressing current consumption of the control unit. Another object of the present invention is to provide a method of manufacturing a semiconductor device which meets the above-mentioned object.

[0013]

According to the present invention, a Schottky barrier diode is provided so that a discharge current can bypass a control unit. That is, in a semiconductor device having a switching semiconductor element that conducts and interrupts a current in accordance with a control signal, and a switching control semiconductor integrated circuit including a control unit that supplies a control signal to a control input of the switching semiconductor element, A current bypass path is formed by a Schottky barrier diode with respect to a discharge path having a reverse bias element generated in the control unit as the element is opened and closed, and a switch is provided in the bypass path.
An overcurrent detection resistor of the semiconductor chip is included . Further, the Schottky barrier diode forming a bypass path switching semiconductor element, or scan
Formed on the same substrate as the semiconductor integrated circuit for switching control
It is characterized by .

Further, in the present invention, by employing a special circuit configuration, the bypass path can be formed by a rectifier diode. That is, a switching semiconductor device that conducts and interrupts a current in accordance with a control signal, a switching control semiconductor integrated circuit including a control unit that supplies a control signal to a control input of the switching semiconductor device, and output and control of the control unit. In the semiconductor device having a control resistor connected between the input and the input, in the semiconductor device having a reverse bias element generated in the control unit with the opening and closing of the switching semiconductor element, forming a current bypass path with a rectifier diode, This bypass path is formed by including a control resistor, and a voltage drop means is connected between the output of the control unit and the control resistor. It is preferable that the voltage drop means be a rectifier diode. Also, a resistor can be used as the voltage drop means. In the configuration in which the voltage drop means is connected, it is preferable to provide a rectifier diode connected in parallel to the voltage drop means and having a forward direction opposite to the voltage applied to the voltage drop means at the time of the reverse bias. As still another circuit configuration, a diode that blocks an inflow current when a reverse bias is applied to the discharge path may be provided.

A first manufacturing method for forming a Schottky barrier diode constituting a bypass path on the same substrate as a switching semiconductor element is as follows. A step of forming a crystalline silicon layer, a step of masking a part of the polycrystalline silicon layer to further increase the impurity concentration of the polycrystalline silicon layer, and a step of forming a polycrystalline silicon layer having a high impurity concentration on the formed polycrystalline silicon layer. Forming an insulating layer and then forming a contact hole in the masked portion, and forming the same layer of a metal layer on the insulating layer that is to be an output electrode layer of the switching semiconductor element and masking the portion Contacting with the polycrystalline silicon layer.

In a second manufacturing method, a step of forming a polycrystalline silicon layer having a high impurity concentration of the same layer which is to be partly used as a control electrode layer of a switching semiconductor element; A step of forming an opening, a step of forming a single-crystal silicon layer having an impurity concentration lower than the surrounding impurity concentration in the opening by epitaxial growth, and a step of forming an insulating layer on the polycrystalline silicon layer having a high impurity concentration. Forming a contact hole at a portion of the low-impurity-concentration single-crystal silicon layer, and forming the same metal layer to be an output electrode layer of a switching semiconductor element on the insulating layer, and Contacting with the crystalline silicon layer.

[0017]

In the above-described semiconductor device, since the forward rise voltage of the Schottky barrier diode is lower than that of the rectifier diode or the like, a voltage lower than the reverse saturation voltage of the reverse-biased element in the discharge path is obtained. It is possible to bypass the discharge current to the bypass path. Therefore, even when a voltage fluctuation occurs when the switching semiconductor element is in the off state, the discharge current of the feedback capacitance due to the opening and closing of the switching semiconductor element and the current due to the back electromotive force of the wiring inductance flow through the discharge path of the control unit in the preceding stage. It will flow through the bypass path without passing through. Therefore, malfunction and destruction of the control element of the control unit can be prevented. Furthermore, since a delay in the operation of the control element can be prevented, when the control unit is configured by a push-pull circuit (complementary circuit) or the like, the through current is suppressed, and the current consumption can be reduced. In particular, limit overcurrent in the bypass path
Therefore, the overcurrent detection resistor of the switching semiconductor element is included.
Therefore, it can also be used as a current limiting resistor.

The above-described effect can also be obtained when a bypass path is formed by the rectifier diode as described above for the discharge path. Because the voltage drop of the voltage drop means is superimposed on the voltage drop of the parasitic diode due to the reverse bias at the time of discharging, the bypass path is formed by the rectifier diode (of course, the bypass path is formed by the Schottky barrier diode). However, since the load on the discharge path side is relatively larger than that on the bypass path side, the discharge current flows through the bypass path. Although the voltage drop means may be a rectifier diode or a resistor, the electric charge accumulated in the feedback capacitance of the switching semiconductor element is usually discharged via the ON element of the control unit. There is a possibility that the discharge path at the time is obstructed. For this reason, by providing a diode in parallel with the voltage drop means, it is possible to allow the discharge current passing through the ON element to pass without any trouble.

Further, in the case where a diode is provided for blocking a current flowing into the discharge path during reverse bias, the discharge current does not flow into the off element in the reverse bias state, and the discharge current completely flows only into the bypass path. Will flow.

In the case where the first manufacturing method in which the Schottky barrier diode forming the bypass path is formed on the same substrate as the switching semiconductor element is adopted, the switching semiconductor element is controlled not on the main surface of the semiconductor substrate (bulk). Since a Schottky barrier diode can be formed in the electrode layer, a layout with a high degree of freedom can be achieved as well as a single chip. Further, since the Schottky barrier diode can be formed by directly using the process for forming the switching semiconductor element, there is an advantage that the number of steps is not increased. On the other hand, when the second manufacturing method is employed, the Schottky barrier diode can be formed not on the semiconductor substrate but on a single crystal of the same layer as the control electrode layer, so that a Schottky barrier diode having good characteristics can be obtained. Can be.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 shows the configuration of a switching circuit (drive circuit) using a semiconductor device according to an embodiment. In the circuit configuration of this example, the main power supply 2 is turned on / off by a power MOSFET 11 connected in series with the transformer 1 (only the primary side is shown), in substantially the same manner as the conventional circuit configuration described above. The N-type power MOSFET 11 is opened and closed by a control signal output from an output terminal 21 of a control unit 20 of the semiconductor integrated circuit and input to a control terminal 12 via a control resistor (gate resistor) 15 for preventing overcurrent. You. Similarly, the control unit 20 also includes an NPN transistor 22 and a PNP transistor 2 driven based on an input signal from a logic circuit (not shown).
When the NPN transistor 22 is turned on and the PNP transistor 23 is turned off, the power MOSFET 11 is turned on, and the PNP transistor 23 is turned on and the NPN transistor 22 is turned on.
Is turned off, the MOS 11 is in a bias 0 or reverse bias state, and is turned off. The semiconductor device 10
The power MOSFET 11 and the control unit 20 may be built in a single resin case, or may be housed in separate cases and connected between terminals.

A point to be noted in the semiconductor device 10 of this embodiment is that a bypass path including a Schottky barrier diode (SBD) 27 is provided between the control terminal 12 and the output terminal 13 which is a ground terminal. is there. The Schottky barrier diode 27 has an anode side 27A.
Are connected to the output terminal (source terminal) 13 side, the cathode side 27K is connected to the control terminal 12 side, and a current flows from the ground side to the control terminal 12 through the Schottky barrier diode 27. . Therefore, as shown by the dashed arrow in FIG. 1, when the output voltage V _DS changes when the power MOSFET 11 is in the bias 0 or reverse bias state (when the drain current _ID is 0), the output terminal 13 of the power MOSFET 11 The discharge current 16 generated by discharging the capacitance (feedback capacitance) 14 existing between the control terminals 12 flows through the Schottky barrier diode 27, and the PNP in the ON state of the control unit 20
It becomes possible to bypass the current that is going to flow through the parasitic diode of the type transistor 23. Therefore, it is possible to prevent malfunction and destruction due to reverse bias of the control unit 20 due to the discharge current 16 which has been a problem in the conventional semiconductor device, or reduce current consumption.

As described above, the transistor 23 of the control unit 20
In order to prevent the destruction or the like, the characteristics of the diode 27 constituting the bypass path must satisfy the following expression (2).

The transient (forward voltage) V _{F of the} diode 27 <the reverse saturation voltage of the transistor 23 constituting the control unit (2) A Zener diode conventionally provided for protecting the gate of the power MOSFET 11 due to an overvoltage. And PN
In a junction diode or the like, the forward voltage is high, so that characteristics satisfying the above relationship cannot be obtained. As a result, protection of the control unit 20 cannot be achieved. However, since there is no cumulative effect of minority carriers because the Schottky barrier diode 27 is a multiple carrier device carrier a number governs the operation, a forward rising voltage is very low, transient lower (forward voltage) V _F Characteristics can be satisfied.

In the semiconductor device shown in FIG. 1, the current consumption of the integrated circuit in which the control unit 20 is actually formed is 30 mA.
To 16 mA. this is,
The discharge current flowing through the parasitic diode of the PNP transistor 23 included in the control unit 20 can be bypassed by the Schottky barrier diode 27 installed in the device of the present example. This is considered to be because it was possible to prevent the through current and reduce the through current. Similarly, since the operation near the point where the voltage of the control signal supplied from the control unit 20 becomes 0 becomes stable, the unstable operation of the integrated circuit constituting the control unit 20 is eliminated, and the control circuit 20 is used for an inverter module or the like. The operation instability of the control circuit is also eliminated.

(Embodiment 2) FIG. 2 shows a modification of the semiconductor device similar to that of FIG. 1, in which an overcurrent detection resistor 17 for detecting an overcurrent is provided on the ground terminal 13 side of the power MOSFET 11. Is shown. In this example, the bypass path does not include the overcurrent detection resistor 17.

(Embodiment 3) FIG. 3 (a) shows that the resonance capacitor 3 is mounted in parallel with the primary side of the output transformer 1, and FIG. 3 (b) shows that the resonance capacitor 3 has the output. An example is shown in which the transformer 1 is mounted in series with the primary side.

(Embodiments 4 and 5) FIGS. 4 and 5 show an example of a device in which a path for bypassing a discharge current is formed by including a control resistor 15 or an overcurrent detection resistor 17 in addition to a diode 27. Is shown. In such a case, the resistor 1
5 or the overcurrent detection resistor 17 causes a current limit of the bypass current. In particular, in order to prevent malfunction of the transistors 22 and 23 of the control unit (integrated circuit) 20,
It is necessary to select a diode having a low forward voltage drop of the diode 27. However, since the diode 27 is not a Zener diode or a junction diode but a Schottky barrier diode, the resistor 15 or the resistor 15 is not activated without operating the parasitic diode of the transistor 23. It is possible to bias via the overcurrent detection resistor 17.

Furthermore, in the semiconductor device as shown in FIGS. 4 and 5, it should be noted that the Schottky barrier diode 27 for bypass is formed integrally with the control unit 20 or the power MOSFET 11 of the semiconductor integrated circuit (one chip). ). FIG. 6 shows an example of a configuration on a semiconductor substrate when the Schottky barrier diode 27 is integrated with the control unit 20 as an integrated circuit in the device including the control resistor 15 in the bypass path shown in FIG. In this device, an n ⁺ -type buried layer 33 is formed above a P ⁺ -type semiconductor substrate 32, and an n ⁻ -type epitaxial layer 34 is further formed thereon. The P ⁺ -type base layer 35 and the n ⁺ -type emitter or collector layer 36 form NPN-type transistors 22 and 23b. As shown in an equivalent circuit in FIG. 7, the PNP transistor 23 described above is actually a PNP transistor 23a.
And an NPN-type transistor 23b, which is shown in FIG. 6 as an NPN-type transistor 23b. Further, an aluminum cathode electrode 37 connected to the collector layer 36 is in contact with the isolated island of the NPN transistor 23b,
A Schottky barrier diode (S
BD) 27 is made. A p ⁺ -type guard ring 3 is provided around the Schottky barrier diode 27.
9 are formed. By arranging the Schottky barrier diode 27 upstream of the control resistor 15 in this manner, the Schottky barrier diode 27 for protecting the control unit 20 can be formed on the same substrate as the control unit 20. Thus, the control unit 20 can be protected with a compact configuration without increasing the number of parts.

FIG. 8 shows an example in which a Schottky barrier diode 27 is integrated with the power MOSFET 11 in the semiconductor device having the configuration shown in FIG. In the configuration of the power MOSFET 11 side, as shown in an equivalent circuit of FIG. 9, a Schottky barrier diode 27 is provided between an output terminal (source) 13 between a control terminal 12 and a gate terminal 11G of the power MOSFET 11 (N-channel type). The overcurrent detection resistor and the like can be installed downstream of the output terminal 13.

The power MOSFE on the semiconductor substrate
The configuration of T11 (N-channel type) includes an n ⁻ -type epitaxial layer 39 formed on an n ⁺ -type substrate 38,
The p ⁺ -type diffusion region 40 a, the p-type channel region 40, the n ⁺ -type source region layer 41 formed by the double diffusion, and the n ⁺⁺ -type polysilicon layer 44 formed via the gate insulating layer 42 It has a gate electrode 44G and a source electrode 46S of an aluminum wiring 46 which is in conductive contact with the source region 41 on the interlayer insulating film 45. The MOSFET of this example
Since 11 has a vertical double diffusion structure, a drain electrode (back electrode) (not shown) is formed on the back surface of the substrate 38. In the region adjacent to the part where the double-diffusion type power MOSFET 11 is formed, the anode electrode of the Schottky barrier diode 27 is provided on a part of the same n ^{+ +} -type polycrystalline silicon layer 44 connected to the gate electrode 44G. Is formed, an n ⁺ -type polycrystalline silicon layer 44a constituting
A portion 46k of the same-layer aluminum wiring 46 connected to the source electrode 46 of the power MOSFET 11 contacts the n ⁺ -type polycrystalline silicon layer 44a via a contact hole of the insulating layer 45 as a canode electrode of the Schottky barrier diode 27. are doing. Thus, the power MOSF
By making a part of the polycrystalline silicon gate wiring of the ET11 a low impurity region, the Schottky barrier diode 27 can be replaced with the power MOSFET 11 instead of the bulk main surface.
Can be formed on a part of the gate wiring, and a single chip can be achieved while reducing the layout space.

Such a semiconductor structure is manufactured by the steps shown in FIG. First, as shown in FIG.
After forming an n ⁻ -type epitaxial layer 39 on the n ⁺ -type substrate 38 by epitaxial growth, a gate insulating layer 44G of polycrystalline silicon is formed via a gate insulating layer 42. Then, the gate insulating layer 44 is formed by using the double diffusion method.
G is used as a mask to diffuse a p-type impurity element such as boron by self-alignment to form ap ⁺ -type diffusion region 40a and a p-type channel region 40.
The mask (not shown) formed between the gate insulating layer 44
Using G as a mask, an n-type impurity element such as phosphorus is diffused to form an n ⁺ -type source region layer 41. The process so far is the same as the conventional method, except that the polycrystalline silicon layer of the gate insulating layer 44G is of the n ⁺ type. In order to further reduce the gate wiring resistance, it is necessary to increase the concentration of the polycrystalline silicon layer 44 including the portion of the gate insulating layer 44G (to make it n ⁺⁺ ). The concentration of the silicon layer 44 is increased. In this example, this ion implantation is also performed.
As shown in (b), a mask 52a for preventing ion implantation into the active region of the power MOSFET 11 is formed, and a part 44a of the polycrystalline silicon layer 44 in the adjacent region is covered with the mask 52b. Then, the polysilicon layer 4 is formed by ion implantation of an n-type impurity element.
4. Except for a part 44a of 4, the concentration is increased (to make n ⁺⁺ ). The concentration of the portion 44a remains n ⁺ and serves as the anode electrode of the above-described Schottky barrier diode. Next, after removing the masks 52a and 52b, as shown in FIG. 10C, an interlayer insulating layer 45 is formed on the polycrystalline silicon layer 44, and the active region of the power MOSFET 11 and the polycrystalline silicon layer 44 are formed. The contact holes 45a and 45b are opened in the low concentration portion 44a. Then, as shown in FIG. 8, an aluminum layer 46 serving as a source electrode wiring is formed on the interlayer insulating layer 45, and is brought into contact with the source region 41 and the low concentration portion 44a of the polycrystalline silicon layer 44. As a result, the cathode electrode 46k of the Schottky barrier diode 27 is formed. As described above, in the ion implantation for reducing the wiring resistance of the gate wiring, a part 44a of the polycrystalline silicon layer 44 is also masked in the masking step of the active region of the power MOSFET 11, and the window of the active region of the power MOSFET 11 is opened. In the process, a window is also opened on a portion 44a of the polycrystalline silicon layer 44, thereby forming the Schottky barrier diode 27.
Can be formed. Therefore, the Schottky barrier diode 27 is
Can be formed, so that no new process is added. In addition, since the portion where the Schottky barrier diode 27 is formed does not occupy the main surface of the bulk (epitaxial layer 39) and a part of the gate wiring can be used, the degree of freedom in layout is high.

In place of the aluminum layer 46 constituting the cathode electrode of the Schottky barrier diode 27, a metal layer such as molybdenum or titanium may be used.

FIG. 11 is a sectional view showing a semiconductor structure different from the semiconductor structure shown in FIG. In this figure, the same parts as those shown in FIG. 8 are denoted by the same reference numerals, and description thereof will be omitted.

The structure shown in FIG. 11 differs from the structure shown in FIG. 8 in that anode electrode 54a of Schottky barrier diode 27 is formed as a low impurity (n ⁺ type) single crystal silicon layer. is there. A Schottky barrier diode 27 having higher characteristics than an anode electrode of polycrystalline silicon can be obtained. The semiconductor structure shown in FIG. 11 can be obtained by the method shown in FIG. First, as shown in FIG. 12A, an n ⁻ -type epitaxial layer 3 is formed on an n ⁺ -type substrate 38 by epitaxial growth.
After forming the gate insulating film 9, a gate insulating layer 44G of polycrystalline silicon is formed via the gate insulating layer 42. Then, a p-type impurity element such as boron is diffused by self-alignment using the gate insulating layer 44G as a mask by a double diffusion method to form p ⁺
After forming the p-type diffusion region 40a and the p-type channel region 40, an n-type impurity element such as phosphorus is further removed using the mask (not shown) formed between the gate insulating layers 44G and the gate insulating layer 44G as a mask. Diffusion is performed to form an n ⁺ -type source region layer 41. Thus, the polycrystalline silicon layer of the gate insulating layer 44G is of the n ⁺ type. Next, FIG.
As shown in FIG. 2B, a mask 52a for preventing ion implantation into the active region of the power MOSFET 11 is formed, and the polycrystalline silicon layer 44 is made highly concentrated (n ⁺⁺ ) by ion implantation of an n-type impurity element. Then, the Schottky barrier diode 2 of the polycrystalline silicon layer 44 is formed.
After removing the portion 44b where the 7 should be formed, FIG.
As shown in FIG. 7, an n ⁺ -type single-crystal silicon layer 54a is formed on the removed portion 44b by epitaxial growth.
Next, after removing the mask 52a, as shown in FIG. 12D, an interlayer insulating layer 45 is formed on the polycrystalline silicon layer 44, and the active region of the power MOSFET 11 and the portion of the single crystal silicon layer 54a are formed. The contact holes 45a and 45b are opened. Then, as shown in FIG. 11, an aluminum layer 46 serving as a source electrode wiring is formed on the interlayer insulating layer 45, and is brought into contact with the source region 41 and the single crystal silicon layer 54a. As a result, the cathode electrode 46k of the Schottky barrier diode 27 is formed. In this manufacturing method, a step of partially removing the polycrystalline silicon layer 44 and an epitaxial growth step are added. However, since the anode region (electrode) of the Schottky via diode 27 is made of single-crystal silicon, the element is Characteristics can be improved.

(Embodiment 6) FIG. 13 shows a configuration substantially the same as the above-described semiconductor device, except that a bias power supply 25 is added downstream of the control unit 20. 27 shows a configuration of a semiconductor device in which the control unit 20 is protected by using 27. In the semiconductor device 10 of the present example, the discharge current 16
Are discharged via the Schottky barrier diode 27, bypassing the PNP transistor 23 in the control unit 20. Therefore, the reverse bias voltage applied to the transistor 23 is significantly reduced, and malfunction or destruction of the transistor 23 can be prevented.

According to the measurement, the peak value of the reverse bias voltage is reduced from −35 V to −17 V in the voltage resonance circuit to which −15 V is added as the reverse bias power supply by installing the Schottky barrier diode 27. . Of course, also in the device of this example, it is necessary to employ a diode having characteristics satisfying the relationship of the above-described expression (1), and a Schottky barrier diode having a fast rise and a low forward voltage drop is required. It is desirable to use

FIG. 14 shows an example in which an inverter circuit is constituted by the semiconductor device according to the sixth embodiment. A Schottky barrier diode for protecting a control unit in each of the upper arm 45 and the lower arm 46 of the inverter circuit. 27a and 27b are provided.

(Embodiment 7) FIG.
5 shows a configuration of a semiconductor device in which a Schottky barrier diode 27 according to the present invention is installed in a device in which a Zener diode 26 for constant voltage is connected in parallel.
At the time of bypass, the Schottky barrier diode 2
The anode voltage of 7 is fixed to the Zener voltage.

(Embodiment 8) FIG.
In this case, it is desirable to install a rectifier diode 28 in series with the control resistor 15 in order to secure an operation balance. If a rectifier diode 28 is installed in series with such a control resistor 15,
Since the forward voltage of the path through the parasitic diode of the transistor 23 is twice that of the bias path, the apparent threshold voltage of a switching semiconductor element such as a power MOSFET can be increased,
Since the current reliably flows to the bypass path via the rectifier diode 27, it is possible to improve noise immunity.

By the way, there is a parasitic capacitance between the gate and the source of the power MOSFET 11, and the electric charge stored in the parasitic capacitance needs to be discharged via the transistor 22 when the transistor 22 is on and the transistor 23 is off. However, as described above, if the rectifier diode 28 is inserted to ensure that the rectifier diode 27 allows the bypass current to flow, the discharge of the gate-source parasitic capacitance is impaired. Therefore, in order to improve this, a circuit configuration as shown in FIG. 17 is adopted.

(Embodiment 9) In the circuit configuration of FIG. 17, a diode 282 connected in parallel with the rectifier diode 28 in reverse polarity is added. As a result, the charge of the gate-source parasitic capacitance 141 is reduced by the rectifier diode 2
Since the power is discharged via the resistor 82, the operation of the power MOSFET can be performed normally. Since the forward voltage drop of the parasitic diode 231 and the diode 28 is larger than the forward voltage drop of the diode 27, the current flows through the diode 27 before the current flows through the parasitic diode 231. There is no.

(Embodiment 10) FIG. 18 shows an example in which a resistor 152 is used in place of the diode 28 shown in FIG.

The resistance of the gate-source parasitic capacitance 141 can also be discharged by the resistor 152. However, it is necessary that the sum of the forward voltage drop of the parasitic diode 231 and the voltage drop of the resistor 152 is smaller than the forward voltage drop of the diode 27. In addition, power MOS
The gate resistance of the FET 11 is the sum of the resistance 151 and the resistance 152, and is the same as the value of the resistance 15 shown in FIG.

(Embodiment 11) FIG. 19 shows an improved example of the example shown in FIG. In the circuit configuration shown in FIG. 4, the discharge current is discharged via the diode 27 and the gate resistor 15. If the diode 27 is a Schottky barrier diode, the voltage is discharged through this bypass path because the forward voltage drop is low. If the diode 27 is a rectifier diode, current may flow through the parasitic diode 231 of the transistor 23. . Therefore, in this example, a diode 282 for blocking a reverse bias current is provided on the collector side of the transistor 23. As a result, the discharge current can be completely bypassed to the diode 27 side.

(Embodiment 12) FIG. 20 shows another improved example. This example differs from the example in FIG. 19 in that a diode 282 for blocking a reverse bias current is provided on the emitter side of the transistor 28, and the same effect as in the example in FIG. 19 can be obtained.

Embodiment 13 FIG. 21 shows an embodiment in which the present invention is applied to an H-bridge driver circuit. Note that FIG.
In FIG. 1, the same portions as those shown in FIG. 27 are denoted by the same reference numerals, and description thereof will be omitted. This circuit also has an IGBT (T ₂ ) as a main switching semiconductor element and a semiconductor integrated circuit IC _{2 as a} control circuit. A Schottky barrier diode 27 in a bypass path is provided between the collector and the emitter of the transistor 23. I have. by this,
Since bypass the current generated by the counter electromotive force induced in the wiring inductance L _11, similarly to the above example, it is possible to prevent malfunction or breakdown of the transistors 22 and 23, it is possible to reduce the power loss due to the through current.

[0049]

As described above, the present invention provides the first
Second, a current bypass path is formed by a Schottky barrier diode having a low rising voltage. Second, a current bypass path is formed by a rectifier diode.
The circuit is characterized in that it employs a circuit configuration that allows a discharge current to flow reliably into the bypass path, and has the following effects.

When a Schottky barrier diode having a low forward rise voltage and a small forward voltage drop is used to form a bypass path, a discharge current generated in the switching semiconductor element can flow by bypassing the control unit. It is possible. Therefore, even if the charge of the feedback capacitance when the switching semiconductor element is in the off state or a discharge current due to the reverse power due to the wiring inductance is generated, malfunction or destruction of the switching control semiconductor integrated circuit can be prevented.
Furthermore, since a delay in the operation of the semiconductor can be prevented, the through current can be suppressed, and the current consumption can be reduced. In particular, to limit overcurrent in the bypass path,
The overcurrent detection resistor of the switching semiconductor element is included.
Thus, it can also be used as a current limiting resistor.

Further, even when a bypass path is formed by a rectifier diode, the above-described effect can be obtained by adding a voltage drop unit to the discharge path on the control unit side. This is because the voltage drop of the voltage drop means is superimposed on the voltage drop of the parasitic diode due to the reverse bias at the time of discharging, so that the load on the bypass path becomes smaller, and the discharge current necessarily flows through the bypass path.

Since the electric charge accumulated in the feedback capacitance of the switching semiconductor element is usually discharged through the ON element of the switching control semiconductor integrated circuit, the discharge path in the normal state is blocked by the voltage drop means. However, by providing a diode in parallel with the voltage drop means, the discharge current can be passed without any trouble.

Further, in the case where a diode for blocking the inflow current at the time of reverse bias into the discharge path is provided, the discharge current does not flow into the off element in the reverse bias state, and the discharge current completely flows only into the bypass path. Will flow.

In the case where the first manufacturing method in which the Schottky barrier diode forming the bypass path is formed on the same substrate as the switching semiconductor element is adopted, not the main surface of the semiconductor substrate but the control electrode layer of the switching semiconductor element. Since a Schottky barrier diode can be formed, a layout with a high degree of freedom can be achieved as well as a one-chip configuration. Further, since the Schottky barrier diode can be formed by directly using the process for forming the switching semiconductor element, there is an advantage that the number of steps is not increased.

When the second manufacturing method is adopted,
Since the Schottky barrier diode can be formed not on the semiconductor substrate but on a single crystal of the same layer as the control electrode layer, a Schottky barrier diode having good characteristics can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration of a semiconductor device according to a second embodiment of the present invention.

FIGS. 3A and 3B are circuit diagrams illustrating a configuration of a semiconductor device according to a third embodiment of the present invention. FIG. 3A is a circuit diagram in which a resonance capacitor is connected in parallel with a transformer, and FIG. It is the circuit diagram which was connected.

FIG. 4 is a circuit diagram illustrating a configuration of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a semiconductor device according to Embodiment 5 of the present invention.

6 is a cross-sectional view showing a cross-sectional structure of the semiconductor device shown in FIG.

7 is a circuit diagram showing an equivalent circuit of the cross-sectional structure shown in FIG.

8 is a cross-sectional view showing a cross-sectional structure of the semiconductor device shown in FIG.

9 is a sectional view showing an equivalent circuit of the sectional structure shown in FIG.

FIG. 10 is a cross-sectional view showing a step of manufacturing the semiconductor structure shown in FIG. 8;

11 is a cross-sectional view showing another cross-sectional structure of the semiconductor device shown in FIG.

FIG. 12 is a cross-sectional view showing a step of manufacturing the semiconductor structure shown in FIG. 11;

FIG. 13 is a circuit diagram showing a configuration of a semiconductor device according to Embodiment 6 of the present invention.

FIG. 14 is a circuit diagram illustrating an inverter circuit configured using a semiconductor device according to a sixth embodiment of the present invention.

FIG. 15 is a circuit diagram showing a configuration of a semiconductor device according to a seventh embodiment to which a reverse bias power supply is added as in FIG. 13;

FIG. 16 shows a semiconductor device according to an eighth embodiment of the present invention in which a bypass path is formed using a rectifier diode.
FIG. 3 is a circuit diagram showing the configuration of FIG.

FIG. 17 shows a ninth embodiment in which a bypass path is formed using a rectifier diode in a semiconductor device according to the present invention.
FIG. 3 is a circuit diagram showing the configuration of FIG.

FIG. 18 is a diagram illustrating a semiconductor device according to a first embodiment of the present invention in which a rectifier diode is used to form a bypass path.
FIG. 3 is a circuit diagram illustrating a configuration of a zero.

FIG. 19 is a diagram illustrating a semiconductor device according to a first embodiment of the present invention in which a rectifier diode is used to form a bypass path.
1 is a circuit diagram showing a configuration of FIG.

FIG. 20 is a diagram illustrating a semiconductor device according to an embodiment of the present invention, in which a rectifier diode is used to form a bypass path.
2 is a circuit diagram showing a configuration of FIG.

FIG. 21 is a circuit diagram showing a thirteenth embodiment in which the present invention is applied to an H-bridge driver circuit.

FIG. 22 is a circuit diagram showing a configuration of a conventional semiconductor device.

FIG. 23 shows a power MO in the semiconductor device shown in FIG. 19;
FIG. 4 is a graph showing a change in voltage applied to an SFET.

FIG. 24 is a circuit diagram showing a configuration of a conventional semiconductor device having a reverse bias power supply.

FIG. 25A is a graph showing the power M of the semiconductor device shown in FIG. 24;
FIG. 4 is a graph showing a change in voltage applied to the OSFET;
(B) is a graph showing the fluctuation of the reverse bias voltage.

FIG. 26 is a circuit diagram showing a conventional H-bridge driver circuit.

FIG. 27 is a circuit diagram showing details of a switching control semiconductor integrated circuit of the driver circuit shown in FIG. 26;

[Explanation of symbols]

1 Transformer 2 Main power supply 3 Resonant capacitor 10 Semiconductor device 11 Power MOSFET 12 Power MOSFET control input terminal 13 Power MOSFET output terminal 14 Power MOSFET Feedback capacitance (between gate and drain) 15. Control resistor 16. Discharge current 17. Overcurrent detection resistor 20. Control unit 21. Output terminal of switching control semiconductor integrated circuit 22. NPN transistor 23. ··· PNP transistor 25 ··· Reverse bias power supply 27 ··· Schottky barrier diode (SBD) 28 ··· Rectifier diode 38 ··· n ⁺ type semiconductor substrate 39 ··· n ⁻ type epitaxial layer 40 ··· p type channel diffusion layer 40a ... p ⁺ -type diffusion layer 41 ... n ⁺ source region 42 ... gate insulating layer 44, Polycrystalline silicon layer 44a Low polycrystalline silicon layer (anode electrode) 44G Gate electrode layer 45 Interlayer insulating layer 46 Aluminum layer 46S Source electrode 46 Cathode electrode 54a Low concentration Single-crystal silicon layer (anode electrode) 141... Feedback capacitance of power MOSFET (gate
Source) 231 ... parasitic diode 282 .. diode _{T 1 ~T 4 ·· IGBT D 1} ~D 4 back electromotive force absorbing diode IC ₁ ~IC during · · blocking ₄ · switching control semiconductor integrated circuit R ₁ to R ₄ are controlled resistance _{L 11, L 12, L 21} , L 22 ·· wiring inductance L · · inductive load

Continuation of the front page (51) Int.Cl. ⁷ Identification code FI H03K 17/60 17/695 (72) Inventor Masanori Mitamura 1-1-1, Tanabe Shinda, Kawasaki-ku, Kawasaki-shi, Kanagawa Prefecture Fuji Electric Co., Ltd. (56) References JP-A-4-115715 (JP, A) JP-A-1-133415 (JP, A) JP-A-2-7714 (JP, A) JP-A-3-57314 (JP, A) −500593 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/06 H01L 27/082 H03K 17/00-17/70 H01L 21/8249 H01L 21/8228 H01L 29 / 78

Claims (10)

(57) [Claims] 1. A semiconductor device comprising: a switching semiconductor element for conducting and interrupting a current in accordance with a control signal; and a switching control semiconductor integrated circuit including a control unit for supplying the control signal to a control input of the switching semiconductor element. Wherein a current bypass path is formed by a Schottky barrier diode with respect to a discharge path having a reverse bias element generated in the control unit as the switching semiconductor element is opened and closed, and the bypass path is connected to the switch.
A semiconductor device including an overcurrent detection resistor of a semiconductor chip . 2. The semiconductor device according to claim 1, wherein
A semiconductor device, wherein the Schottky barrier diode is formed on the same substrate as the switching semiconductor element. 3. The current is turned on / off according to a control signal.
A switching semiconductor element and the switching semiconductor element
A switch including a control unit for supplying the control signal to the control input of the
Semiconductor device having a switching control semiconductor integrated circuit.
And the control unit is opened and closed with the opening and closing of the switching semiconductor element.
The discharge path with the reverse bias element generated in
Current bypass with Schottky barrier diode
A path is formed, and the Schottky barrier diode is
Mode is the same as that of the switching control semiconductor integrated circuit.
A semiconductor device formed on a plate . 4. A semiconductor integrated circuit for switching control including a switching semiconductor element for conducting and interrupting a current according to a control signal, a control unit for supplying the control signal to a control input of the switching semiconductor element, and the control unit And a control resistor connected between said output and said control input, wherein a rectifier diode is provided for a discharge path having a reverse-biased element generated in said control unit with opening and closing of said switching semiconductor element. A semiconductor device, wherein a path for bypassing a current is formed by the method, the bypass path includes the control resistor, and a voltage drop unit is connected between an output of the control unit and the control resistor. . 5. The semiconductor device according to claim 4 , wherein
2. The semiconductor device according to claim 1, wherein said voltage drop means is a rectifier diode. 6. The semiconductor device according to claim 4 , wherein
2. The semiconductor device according to claim 1, wherein said voltage drop means is a resistor. 7. The semiconductor device according to claim 4 , wherein
A semiconductor device, comprising: a rectifier diode connected in parallel to the voltage drop means and having a forward direction opposite to a voltage applied to the voltage drop means during the reverse bias. 8. The semiconductor device according to claim 5 , wherein
A semiconductor device comprising: a diode for preventing a current flowing into the discharge path at the time of the reverse bias. 9. The current is turned on / off in response to a control signal.
A switching semiconductor element and the switching semiconductor element
A switch including a control unit for supplying the control signal to the control input of the
A semiconductor integrated circuit for controlling switching, the switch comprising:
Occurs in the control unit as the switching semiconductor element opens and closes
Schottky for discharge path with reverse biased element
A current bypass path is formed with a barrier diode.
And the Schottky barrier diode is
A method of manufacturing a semiconductor device formed on the same substrate as an etching semiconductor element, comprising forming an impurity-doped polycrystalline silicon layer of the same layer to be partially used as a control electrode layer of the switching semiconductor element. Performing a step of masking a part of the polycrystalline silicon layer to further increase the impurity concentration of the polycrystalline silicon layer; and forming an insulating layer on the formed polycrystalline silicon layer having a high impurity concentration. Forming a contact hole in the masked part after forming the same, and forming the same layer of a metal layer that is to be an output electrode layer of the switching semiconductor element on the insulating layer and masking the part. Contacting the polycrystalline silicon layer with a polycrystalline silicon layer. 10. A current is turned on / off according to a control signal.
Switching semiconductor element and the switching semiconductor
A switch including a control unit for supplying the control signal to a control input of the element.
A semiconductor integrated circuit for switching control.
Occurs in the control unit as the switching semiconductor element opens and closes.
Schottky for discharge path with reverse biased element
-A current bypass path is formed with a barrier diode
And the Schottky barrier diode is
A method for manufacturing a semiconductor device formed on the same substrate as a switching semiconductor element, comprising forming a polycrystalline silicon layer with a high impurity concentration in the same layer that is to be partially used as a control electrode layer of the switching semiconductor element. Forming an opening in a part of the polycrystalline silicon layer; forming a single-crystal silicon layer having an impurity concentration lower than the surrounding impurity concentration in the opening by epitaxial growth; A step of forming an insulating layer on the high-concentration polycrystalline silicon layer and then forming a contact hole in the portion of the low-concentration single-crystal silicon layer, and a part of the step becomes an output electrode layer of the switching semiconductor element Forming a metal layer of the same layer on the insulating layer and contacting the single crystal silicon layer with a low impurity concentration. Method of manufacturing location.