JPH06318678A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To prevent malfunction and breakdown of semiconductor constituting a control part, and reduce the consumption current of a semiconductor integrated circuit for switching control, by making the discharge current due to the feedback capacitance or the like of a switching element bypass the semiconductor integrated circuit for switching control, in a semiconductor device having a power MOSFET constituting an inverter or the like and a switching element like an IGBT. CONSTITUTION:A current bypass route is formed by arranging a Schottky barrier diode 27, from the output terminal 13 of a power MOSFET 11 toward a control terminal 12 in which a control signal is inputted. The Schottky barrier diode 27 has a small voltage drop in the forward direction and can bypass a discharge current by a voltage lower than or equal to the backward saturation voltage of a transistor 23 in a control part 20, so that malfunction and breakdown of the transistor 23 can be prevented, and a consumption current can be reduced by decreasing the penetration current.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for converting alternating current to direct current or converting frequency by a switching system such as a switching power source, an inverter type fluorescent lamp, a motor control inverter, etc. The present invention relates to a semiconductor device having a switching semiconductor element and a control semiconductor integrated circuit for controlling conduction / interruption of the switching semiconductor element and a manufacturing method thereof.

[0002]

2. Description of the Related Art Semiconductor devices used for inverters and the like include power MOSFETs and IGBTs for switching.
A switching semiconductor element such as (conductivity modulation type transistor or insulated gate bipolar transistor) is used, and input protection of this switching semiconductor element,
Alternatively, a Zener diode is often inserted between a gate terminal which is a control input for adjusting the switching speed and a ground side such as a source terminal. These techniques are described in JP-A-4-115715 and JP-A-60-
Detailed in 139018 etc.

[0003]

When such a power switching semiconductor device is switching-controlled by a flyback system or a voltage resonance system, if a current flows intermittently in the switching semiconductor device or the current fluctuates rapidly. , It is not a problem for normal (small current, low speed switching) switching semiconductor elements, but the feedback capacitance (parasitic capacitance, coupling capacitance) between the output terminal and control terminal of the switching semiconductor element is apparent due to the large current and high speed switching. And charge / discharge occurs in this. The current due to the feedback capacitance appears at the control terminal via the gate electrode in the insulated gate semiconductor element such as power MOS and IGBT, and at the base terminal in the bipolar transistor, so that the discharge current is the main switching semiconductor element. May flow via a path on the side of the control semiconductor integrated circuit (control unit) that outputs a control signal from the control input to the control input. For this reason, the discharge current may cause the switching control circuit in the preceding stage of the main switching semiconductor device to malfunction, or a voltage higher than the guaranteed voltage may be applied to the transistors forming the switching circuit to destroy the control circuit.

By the way, in the conventional input protection circuit in which a Zener diode is connected between the control input of the main switching semiconductor element and the source terminal, the forward rising voltage of the Zener diode is high and discharge current Since the section inevitably spreads to the preceding circuit, it is incomplete in terms of protection of the control section side (low breakdown voltage element) aside from protection of the main switching semiconductor element.

FIG. 22 shows an outline of a conventional semiconductor device which performs switching. In this semiconductor device 10, a main power supply 2 is turned on / off by a power MOSFET 11 as a main switching element connected in series with a transformer 1 (only the primary side is shown). Power MOSFE
T11 is a control terminal 12 connected to the gate electrode 11G.
It is driven to open and close by a control signal input from, and the control signal is output from the output terminal 21 of the control unit 20 of the semiconductor device 10. The control terminal 12 and the output terminal 21 are, for example, control resistors (gate resistors) of discrete components.
It is connected via 15. The control unit 20 also drives an NP driven based on an input signal from a logic circuit (not shown).
The push-pull circuit includes an N-type transistor 22 and a PNP-type transistor 23. When the NPN-type transistor 22 is turned on and the PNP-type transistor 23 is turned off, the power MOSFET 11 is turned on and the PNP-type transistor 23 is turned on and the NPN-type transistor 23 is turned on. When 22 is turned off, the power MOSFET 11 is in a bias 0 or reverse bias state and is turned off.

In such a semiconductor device 10, when the power MOSFET 11 is in the off state and the bias is 0 or the reverse bias state (when the drain current I _D is 0).
When the output voltage V _DS changes as shown in FIG. 23, especially when the voltage shifts from a high voltage to a low voltage as shown in the region 31, for example, in the flyback type switching power supply, a period in which the load current is small and the transformer current does not flow occurs. In such a case, the capacitance (feedback capacitance) 14 existing between the output terminal (source terminal) of the power MOSFET 11 and the control terminal 12 is discharged, and the discharge current 16 flows.
The path of this discharge current 16 is from the main power supply 2 through the parasitic diode of the PNP transistor 23 in the off state of the control unit 20, and further from the control resistor 15 to the control terminal 12 of the power MOSFET 11, as shown by the dashed arrow. Flowing through. Therefore, such a discharge current flows in the direction opposite to the forward direction of the PNP type transistor 23, which makes the operation of the control section 20 unstable and, at the same time, destroys the transistor 23 when the reverse bias voltage exceeds the guaranteed voltage. It may be connected. Further, since the discharge current 16 flows in the direction opposite to the operation direction of the PNP type transistor 23, a delay occurs in the subsequent ON operation of the PNP type transistor 23. As a result, the push-pull operations of the NPN-type transistor 22 and the PNP-type transistor 23 disagree with each other, and both transistors are temporarily turned on, so that a through current flows and the current consumption in the control unit 20 increases. The problem also occurs.

FIG. 24 shows the structure of a semiconductor device 10 similar to that described above, but with a bias power supply 25 added downstream of the controller 20. Also in such a semiconductor device 10, the power MOSFET 1
1 indicates the output voltage V _DS as shown in the area 31 in FIG.
Changes, the discharge current 16 flows through the bias power supply 25, the parasitic diode of the PNP transistor 23 in the OFF state of the control unit 20, and the control resistor 15. As a result, the reverse bias voltage V _GS generated between the control terminal 12 of the power MOSFET 11 and the output terminal 13 which is the ground terminal is expressed by the following equation (1), and its value is shown in FIG. 25 (b). It changes rapidly.

Reverse bias voltage V _GS = voltage of reverse bias power supply 25 + reverse saturation voltage of PNP transistor 23 of control unit 20 + control resistor 15 × feedback capacitance 14 × change amount of output voltage (dV / dt) ( 1) Therefore, in this case, the reverse bias voltage V _GS is PN
It is easy to exceed the guaranteed voltage of the P-transistor 23, and the control unit 2
There is a problem that breakdown of 0 transistors and the like is more likely to occur.

As described above, the reason why the reverse vice current spreads to the control section 20 side is that the above power MOSFET is used.
Not only the case of discharging the feedback capacitor 11 but also the following cases. FIG. 26 shows an H-type bridge drive circuit for driving the inductance load L ₁ by four main switching IGBTs (conductivity modulation type transistors) T _{1 to} T ₄ . In this figure, D _{1 to} D ₄ are diodes for absorbing back electromotive force at the time of interruption, and IC _{1 to} IC ₄ are IGBTT ₁ to
A semiconductor integrated circuit for controlling switching of T ₄ , R _{1 to} R ₄ are control resistors, 2 is a main power source of the IGBT, V _cc is a power source of the semiconductor integrated circuit, and C _{1 to} C ₄ are capacitors for absorbing fluctuation of the power source V _cc. Is. Now, in the case where the IGBTs (T ₂ , T ₃ ) are off and the IGBTs (T ₁ , T ₄ ) are on,
Although a current flows through the load L ₁ through the current path indicated by the broken line arrow in the figure, the current variation of the wiring inductance L ₂₁ parasitic on the ground wiring between the IGBT (T ₂ ) and the IGBT (T ₄ ) is −di / dt. An electromotive force proportional to is generated, and a current flows through the current path indicated by the solid arrow in the figure.

Due to this change in the current, FIG. 26 and FIG.
Due to the wiring inductances L ₁₁ and L ₁₂ shown in FIG. 7, current flows in the current path indicated by the solid arrow and the current path indicated by the broken arrow. At this time, the IGBT (T ₂ ) is off, the PNP transistor 23 of the semiconductor integrated circuit IC ₂ is on, and the NPN transistor 22 is off.

The current due to the wiring inductance L ₁₂ is PN
There is no particular problem because it is in the forward direction with respect to the P-type transistor 23, but the current due to the wiring inductance L ₁₁ is P
Since the NP-type transistor 23 and the NPN transistor 22 are reverse-biased and flow through these parasitic diodes, the potential of the OUT terminal (V _CC terminal) becomes a negative potential as compared with that of the GND terminal, and the semiconductor integrated circuit IC ₂
The power supply abnormality detection circuit (comparison circuit) COM therein operates and an alarm signal ALM may be generated. The reverse bias to the NPN transistor 22 and the PNP transistor 23 due to the counter electromotive force due to the wiring inductance causes the above-mentioned problems (malfunction of switching control, breakdown of the transistor, power loss due to through current, etc.). Especially when performing high-speed high-speed switching,
Since -di / dt has a very large value, the above problem becomes more and more prominent.

In view of the above problem, therefore, in the present invention, the reverse bias current which is transmitted to the control unit at the preceding stage due to discharge of the feedback capacitance and back electromotive force of the wiring inductance accompanying conduction / interruption of the main switching element. By eliminating the influence, it is an object of the present invention to realize a semiconductor device capable of preventing malfunction and destruction of the control unit and further suppressing current consumption of the control unit. Another object of the present invention is to provide a method of manufacturing a semiconductor device which meets the above-mentioned object.

[0013]

In order to solve the above problems, in the present invention, a Schottky barrier diode is provided so that the discharge current can bypass the control section. That is, in a semiconductor device having a switching semiconductor element that conducts / blocks a current according to a control signal, and a switching control semiconductor integrated circuit including a control unit that supplies a control signal to a control input of the switching semiconductor element, a switching semiconductor It is characterized in that a path for bypassing a current is formed by using a Schottky barrier diode with respect to a discharge path having a reverse bias element generated in the control unit when the element is opened and closed. Of course, it is common to provide a control resistor in order to limit the overcurrent applied to the control input depending on the operating conditions of the switching semiconductor element. In such a case, however, the control resistor may be included in the bypass path. Further, an overcurrent detection resistor of the switching semiconductor element may be included in the bypass path. The Schottky barrier diode forming the bypass path can be formed on the same substrate as the switching semiconductor element, or can be formed on the same substrate as the switching control semiconductor integrated circuit.

Further, in the present invention, the bypass path can be formed by the rectifying diode by adopting a special circuit configuration. That is, a switching semiconductor element that conducts and blocks a current according to a control signal, a switching control semiconductor integrated circuit including a control section that supplies a control signal to a control input of the switching semiconductor element, and an output and a control of the control section. In a semiconductor device having a control resistance connected between the input and the input, a path for current bypassing is formed by a rectifying diode with respect to a discharge path having a reverse bias element generated in a control unit with opening and closing of a switching semiconductor element, This bypass path is formed by including a control resistor, and a voltage drop means is connected between the output of the control unit and the control resistor. A rectifier diode is preferable as the voltage drop means. A resistor can also be used as the voltage drop means. In the configuration in which the voltage drop means is connected, it is preferable to provide a rectifier diode connected in parallel to the voltage drop means and having a forward direction in the direction opposite to the applied voltage applied to the voltage drop means during the reverse bias. As yet another circuit configuration, a diode that blocks an inflow current to the discharge path at the time of reverse bias may be provided.

As a first manufacturing method in which the Schottky barrier diode forming the bypass path is formed on the same substrate as the switching semiconductor element, a part of the same layer, which is to be a control electrode layer of the switching semiconductor element, is often doped with impurities. A step of forming a crystalline silicon layer, a step of masking a part of the polycrystalline silicon layer to further increase the impurity concentration of the polycrystalline silicon layer, and a step of forming a polycrystalline silicon layer with a high impurity concentration on the formed polycrystalline silicon layer. The step of forming a contact hole in the masked portion after forming the insulating layer, and the masked portion in which a metal layer of the same layer that should partially serve as the output electrode layer of the switching semiconductor element is formed on the insulating layer. And the step of bringing the polycrystalline silicon layer into contact with each other.

As a second manufacturing method, a step of forming a polycrystalline silicon layer having a high impurity concentration in the same layer, which is to be a control electrode layer of a switching semiconductor element, and a part of the polycrystalline silicon layer A step of forming an opening, a step of forming a single crystal silicon layer having an impurity concentration lower than the surrounding impurity concentration by epitaxial growth in the opening, and a step of forming an insulating layer on the polycrystalline silicon layer having a high impurity concentration. A step of forming a contact hole in a portion of a single crystal silicon layer having a low impurity concentration and a step of forming a metal layer of the same layer, which is to be an output electrode layer of a switching semiconductor element, on an insulating layer to form a contact hole having a low impurity concentration. And a step of contacting with the crystalline silicon layer.

[0017]

In the semiconductor device as described above, since the forward rising voltage of the Schottky barrier diode is lower than that of the rectifying diode or the like, the voltage is lower than the reverse saturation voltage of the reverse bias element in the discharge path. It is possible to bypass the discharge current to the bypass path. Therefore, even if a voltage fluctuation occurs when the switching semiconductor element is in the off state, the discharge current of the feedback capacitance due to the opening and closing of the switching semiconductor element and the current due to the back electromotive force of the wiring inductance flow through the discharge path of the control unit in the preceding stage. It will flow through the bypass path without passing through. Therefore, malfunction and destruction of the control element of the control unit can be prevented. Further, since the delay in the operation of the control element can be prevented, when the control unit is configured by a push-pull circuit (complementary type circuit) or the like, the through current is suppressed, and the current consumption can be reduced.

Further, the above effect can be obtained also when the bypass path is constituted by the rectifying diode as described above with respect to the discharge path. Because the voltage drop of the voltage drop means is superimposed on the voltage drop of the parasitic diode due to the reverse bias at the time of discharging, so even if the bypass path is formed by the rectifying diode (of course, the bypass path is formed by the Schottky barrier diode). However, since the load on the discharge path side is relatively larger than that on the bypass path side, the discharge current will flow through the bypass path. The voltage drop means may be a rectifier diode or a resistor, but since the charge accumulated in the feedback capacitance of the switching semiconductor element may be discharged through the ON element of the control unit, the voltage drop means should be used instead of the normal state. There is a possibility that the discharge path at that time may be obstructed. Therefore, by providing a diode in parallel with the voltage drop means, the discharge current passing through the ON element can be passed without any trouble.

Further, when a diode for blocking the inflow current to the discharge path at the time of reverse bias is provided, the discharge current does not flow into the OFF element in the reverse bias state, and the discharge current is completely supplied only to the bypass path. It will flow.

When the first manufacturing method in which the Schottky barrier diode forming the bypass path is formed on the same substrate as the switching semiconductor element, the switching semiconductor element is controlled not on the main surface of the semiconductor substrate (bulk). Since the Schottky barrier diode can be formed in the electrode layer, it is possible to realize a layout with a high degree of freedom as well as one chip. Moreover, since the Schottky barrier diode can be configured by directly using the formation process of the switching semiconductor element, there is an advantage that the number of steps is not increased. On the other hand, when the second manufacturing method is adopted, the Schottky barrier diode can be formed not on the semiconductor substrate but on the single crystal in the same layer as the control electrode layer, so that a Schottky barrier diode having good characteristics can be obtained. You can

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 shows a configuration of a switching circuit (drive circuit) using a semiconductor device according to an embodiment. In the circuit configuration of this example, the main power supply 2 is turned on / off by the power MOSFET 11 connected in series with the transformer 1 (only the primary side is shown), similar to the conventional circuit configuration described above. The N-type power MOSFET 11 is controlled to be opened and closed by a control signal output from the output terminal 21 of the control unit 20 of the semiconductor integrated circuit and input to the control terminal 12 through the control resistor (gate resistor) 15 for preventing overcurrent. It Similarly, the control unit 20 similarly drives the NPN transistor 22 and the PNP transistor 2 which are driven based on an input signal from a logic circuit (not shown).
When the NPN transistor 22 is turned on and the PNP transistor 23 is turned off, the power MOSFET 11 is turned on and the PNP transistor 23 is turned on and the NPN transistor 22 is turned on.
When is off, the MOS 11 is in a bias 0 or reverse bias state and is off. The semiconductor device 10
The power MOSFET 11 and the control unit 20 may be built in one resin case, or they may be housed in separate cases and the terminals may be connected to each other.

A point to be noted in the semiconductor device 10 of this example is that a bypass path composed of a Schottky barrier diode (SBD) 27 is provided between the control terminal 12 and the output terminal 13 which is a ground terminal. is there. This Schottky barrier diode 27 has an anode side 27A.
Is connected to the output terminal (source terminal) 13 side, the cathode side 27K is connected to the control terminal 12 side, and a current flows from the ground side to the control terminal 12 through the Schottky barrier diode 27. . Therefore, as shown by the broken line arrow in FIG. 1, when the output voltage V _DS changes when the power MOSFET 11 is in the bias 0 or reverse bias state (when the drain current I _D is 0), the output terminal 13 of the power MOSFET 11 changes. A discharge current 16 generated by discharging the capacitance (feedback capacitance) 14 existing between the control terminals 12 flows through the Schottky barrier diode 27, and the control unit 20 turns on the PNP.
It becomes possible to bypass the current that tries to flow through the parasitic diode of the type transistor 23. Therefore, it is possible to prevent malfunction or destruction due to reverse bias of the control unit 20 due to the discharge current 16 which has been a problem in the conventional semiconductor device, or to reduce current consumption.

In this way, the transistor 23 of the control unit 20
In order to prevent the breakdown of the diode, the characteristics of the diode 27 forming the bypass path must satisfy the following expression (2).

Transient (forward voltage) V _{F of the} diode 27 <reverse saturation voltage of the transistor 23 constituting the control unit (2) Conventionally, a Zener diode installed for gate protection or the like due to overvoltage of the power MOSFET 11. Or PN
Since the forward voltage is high in the junction diode or the like, it is not possible to obtain the characteristics satisfying the above relationship, and it is impossible to protect the control unit 20 after all. However, since the Schottky barrier diode 27 is a majority carrier device in which majority carriers control the operation, it has no effect of accumulating minority carriers, so that the forward-direction rising voltage is very low and the transient (forward voltage) V _F is low. It is possible to satisfy the characteristic.

In the semiconductor device shown in FIG. 1, the consumption current of the integrated circuit in which the control unit 20 is actually configured is 30 mA.
It has been found that it can be reduced to 16 mA. this is,
The Schottky barrier diode 27 installed in the device of this example was able to bypass the discharge current flowing in the parasitic diode of the PNP transistor 23 forming the control unit 20, so that the delay in the operation of the transistor of the control unit 20 could be prevented. It is considered that this is because it is possible to prevent this and to reduce the through current. Further, similarly, since the operation in the vicinity where the voltage of the control signal supplied from the control unit 20 becomes 0 is stable, the unstable operation of the integrated circuit constituting the control unit 20 is eliminated, and the integrated circuit used in the inverter module is used. This has the effect of eliminating the unstable operation of the control circuit.

(Embodiment 2) FIG. 2 is a modification of the semiconductor device similar to that of FIG. 1, in which an overcurrent detection resistor 17 for detecting an overcurrent is installed on the ground terminal 13 side of the power MOSFET 11. It is shown. In this example, the overcurrent detection resistor 17 is not included in the bypass path.

(Embodiment 3) Further, FIG. 3 (a) shows that the resonance capacitor 3 is attached in parallel with the primary side of the output transformer 1, and FIG. 3 (b) shows that the resonance capacitor 3 outputs. An example of what is attached in series with the primary side of the transformer 1 is shown.

(Embodiments 4 and 5) FIGS. 4 and 5 show an example of a device in which a path for bypassing the discharge current is formed by including the control resistor 15 or the overcurrent detection resistor 17 in addition to the diode 27. It is shown. In such a case, the resistance 1
5 or the current limit of the bypass current occurs due to the overcurrent detection resistor 17, in particular, in order to prevent malfunction of the transistors 22 and 23 of the control unit (integrated circuit) 20,
It is necessary to select a diode 27 having a low forward voltage drop. However, since the diode 27 is not a Zener diode or a junction diode but a Schottky barrier diode, the parasitic diode of the transistor 23 is not operated and the resistor 15 or It can be biased via the overcurrent detection resistor 17.

Further, a point to be noted in the semiconductor device as shown in FIGS. 4 and 5 is that the bypass Schottky barrier diode 27 is formed integrally with the control unit 20 or the power MOSFET 11 of the semiconductor integrated circuit (one chip). It can be done. FIG. 6 shows an example of the configuration on the semiconductor substrate when the Schottky barrier diode 27 is integrated with the control unit 20 as an integrated circuit in the device including the control resistor 15 shown in FIG. 4 in the bypass path. In this device, an n ⁺ type buried layer 33 is formed on a P ⁺ type semiconductor substrate 32, and an n ⁻ type epitaxial layer 34 is further formed thereon. The P ⁺ type base layer 35 and the n ⁺ type emitter or collector layer 36 form NPN type transistors 22 and 23b. As shown in the equivalent circuit of FIG. 7, the PNP transistor 23 described above is actually the PNP transistor 23a.
And an NPN-type transistor 23b are combined, which is shown as an NPN-type transistor 23b in FIG. Further, an aluminum cathode electrode 37 connected to the collector layer 36 is in contact with the isolation island of the NPN transistor 23b,
The Schottky barrier diode (S
BD) 27 is built in. Around the Schottky barrier diode 27 is a p ⁺ type guard ring 3
9 is formed. As described above, by installing the Schottky barrier diode 27 upstream of the control resistor 15, the Schottky barrier diode 27 that protects the control unit 20 can be formed in the same substrate as the control unit 20. It is possible to protect the control unit 20 with a compact structure without increasing the number of parts.

FIG. 8 shows an example in which the Schottky barrier diode 27 is integrally incorporated on the power MOSFET 11 side in the semiconductor device having the structure shown in FIG. As shown in FIG. 9, the configuration on the power MOSFET 11 side is such that a Schottky barrier diode 27 is provided between the control terminal 12 and the gate terminal 11G of the power MOSFET 11 (N-channel type) from the output terminal (source) 13 to the output terminal (source) 13. It is installed, and an overcurrent detection resistor or the like can be installed downstream of the output terminal 13.

Then, the power MOSFE on the semiconductor substrate
The structure of T11 (N channel type) includes an n ⁻ type epitaxial layer 39 formed on an n ⁺ type substrate 38,
The p ⁺ type diffusion region 40a, the p type channel region 40, the n ⁺ type source region layer 41 formed by double diffusion, and the n ⁺⁺ type polycrystalline silicon layer 44 formed via the gate insulating layer 42. It has a gate electrode 44G and a source electrode 46S of an aluminum wiring 46 which is in conductive contact with the source region 41 on the interlayer insulating film 45. The MOSFET of this example
Since 11 has a vertical double diffusion structure, a drain electrode (back surface electrode) not shown is formed on the back surface of the substrate 38. In such a region adjacent to the built-in portion of the double diffusion type power MOSFET 11, the anode electrode of the Schottky barrier diode 27 is formed in a part of the n ⁺⁺ type polycrystalline silicon layer 44 of the same layer connected to the gate electrode 44G. And an n ⁺ -type polycrystalline silicon layer 44a constituting the
A portion 46k of the aluminum wiring 46 in the same layer connected to the source electrode 46 of the power MOSFET 11 contacts the n ⁺ type polycrystalline silicon layer 44a as a cathode electrode of the Schottky barrier diode 27 through the contact hole of the insulating layer 45. is doing. In this way power MOSF
By making a part of the polycrystalline silicon gate wiring of the ET11 a low impurity region, the Schottky barrier diode 27 is not provided in the bulk main surface but in the power MOSFET 11
Can be formed on a part of the gate wiring, and a single chip can be achieved while reducing the layout space.

Such a semiconductor structure is manufactured by the process shown in FIG. First, as shown in FIG.
An n ⁻ type epitaxial layer 39 is formed on the n ⁺ type substrate 38 by epitaxial growth, and then a gate insulating layer 44G of polycrystalline silicon is formed via a gate insulating layer 42. Then, the gate insulating layer 44 is formed by using the double diffusion method.
A p-type impurity element such as boron is diffused by self-alignment using G as a mask to form the p ⁺ -type diffusion region 40a and the p-type channel region 40, and then the gate insulating layer 44G.
A gate insulating layer 44 and a mask (not shown) formed between
Using G as a mask, an n-type impurity element such as phosphorus is diffused to form an n ⁺ -type source region layer 41. The process up to this point is the same as in the conventional method, but the polycrystalline silicon layer of the gate insulating layer 44G is of the n ⁺ type. In order to further reduce the resistance of the gate wiring, it is necessary to increase the concentration (n ⁺⁺ ) of the polycrystalline silicon layer 44 including the portion of the gate insulating layer 44G. Usually, the polycrystalline silicon of the gate wiring is formed by ion implantation. The concentration of the silicon layer 44 is increased. In this example also, this ion implantation is carried out.
As shown in (b), a mask 52a for preventing ion implantation to the active region of the power MOSFET 11 is formed, and a part 44a of the polycrystalline silicon layer 44 in this adjacent region is also covered with the mask 52b. Then, the polycrystalline silicon layer 4 is formed by ion implantation of an n-type impurity element.
The concentration is increased (n ⁺⁺ conversion) except for a part 44a of 4. The concentration of the portion 44a remains n ⁺ and serves as the anode electrode of the Schottky barrier diode described above. Next, after removing the masks 52a and 52b, an interlayer insulating layer 45 is formed on the polycrystalline silicon layer 44 as shown in FIG. 10C, and the active region of the power MOSFET 11 and the polycrystalline silicon layer 44 are formed. The contact holes 45a and 45b are opened in the low-concentration region 44a. Then, as shown in FIG. 8, an aluminum layer 46 serving as a source electrode wiring is formed on the interlayer insulating layer 45, and is brought into contact with the source region 41 and the low-concentration portion 44 a of the polycrystalline silicon layer 44. As a result, the cathode electrode 46k of the Schottky barrier diode 27 is formed. As described above, during the ion implantation for reducing the wiring resistance of the gate wiring, a part 44a of the polycrystalline silicon layer 44 is also masked in the masking step of the active region of the power MOSFET 11, and the window of the active region of the power MOSFET 11 is opened. In the process, the Schottky barrier diode 27 is also opened by opening a window on the part 44a of the polycrystalline silicon layer 44.
Can be formed. Therefore, the Schottky barrier diode 27 is incorporated by using the formation process of the power MOSFET 11.
Can be formed, so that no new process is added. In addition, since the portion where the Schottky barrier diode 27 is formed does not occupy the main surface of the bulk (epitaxial layer 39) and a part of the gate wiring can be used, the degree of freedom in layout is high.

A metal layer such as molybdenum or titanium may be used instead of the aluminum layer 46 which constitutes the cathode electrode of the Schottky barrier diode 27.

FIG. 11 is a sectional view showing a semiconductor structure different from the semiconductor structure shown in FIG. In this figure, the same parts as those shown in FIG. 8 are designated by the same reference numerals, and the description thereof will be omitted.

The portion of the structure shown in FIG. 11 different from the portion shown in FIG. 8 is that the anode electrode 54a of the Schottky barrier diode 27 is formed as a single crystal silicon layer having a low impurity concentration (n ⁺ type). is there. It is possible to obtain the Schottky barrier diode 27 having higher characteristics than the polycrystalline silicon anode electrode. The semiconductor structure shown in FIG. 11 can be obtained by the method shown in FIG. First, as shown in FIG. 12A, the n ⁻ -type epitaxial layer 3 is formed on the n ⁺ -type substrate 38 by epitaxial growth.
9 is formed, a gate insulating layer 44G made of polycrystalline silicon is formed via the gate insulating layer 42. Then, using the double diffusion method, the p-type impurity element such as boron is diffused by self-alignment using the gate insulating layer 44G as a mask, and p ⁺
After forming the type diffusion region 40a and the p-type channel region 40, an n-type impurity element such as phosphorus is further added using a mask (not shown) formed between the gate insulating layers 44G and the gate insulating layer 44G as a mask. By diffusion, an n ⁺ type source region layer 41 is formed. As a result, the polycrystalline silicon layer of the gate insulating layer 44G is of n ⁺ type. Next, FIG.
As shown in (b), a mask 52a is formed to prevent ion implantation in the active region of the power MOSFET 11, and the polycrystalline silicon layer 44 is made to have a high concentration (n ^{+ +} ) by ion implantation of an n-type impurity element. Then, the Schottky barrier diode 2 of the polycrystalline silicon layer 44
After removing the portion 44b where the 7 should be formed, FIG.
As shown in, an n ⁺ type single crystal silicon layer 54a is formed on the removed portion 44b by epitaxial growth.
Next, after removing the mask 52a, as shown in FIG. 12D, an interlayer insulating layer 45 is formed on the polycrystalline silicon layer 44, and the active region of the power MOSFET 11 and the portion of the single crystal silicon layer 54a are formed. The contact holes 45a and 45b are opened. Then, as shown in FIG. 11, an aluminum layer 46 serving as a source electrode wiring is formed on the interlayer insulating layer 45, and is brought into contact with the source region 41 and the single crystal silicon layer 54a. As a result, the cathode electrode 46k of the Schottky barrier diode 27 is formed. In this manufacturing method, a part of the polycrystalline silicon layer 44 is removed and an epitaxial growth step is added. However, since the anode region (electrode) of the Schottky via diode 27 is single crystal silicon, Can be improved.

(Embodiment 6) FIG. 13 shows a structure similar to that of the semiconductor device described above, except that a bias power supply 25 is added downstream of the control unit 20 in addition to the Schottky barrier diode. 27 shows a configuration of a semiconductor device in which the control unit 20 is protected by using the reference numeral 27. Also in the semiconductor device 10 of this example, the discharge current 16
Is bypassed by the PNP transistor 23 in the control unit 20 and discharged via the Schottky barrier diode 27. Therefore, the reverse bias voltage applied to the transistor 23 is greatly reduced, and malfunction or destruction of the transistor 23 can be prevented.

According to the measurement, by installing this Schottky barrier diode 27, the peak value of the reverse bias voltage is reduced from -35V to -17V in the voltage resonance circuit in which -15V is added as the reverse bias power supply. . Of course, in the device of this example as well, it is necessary to employ a diode having the characteristics that satisfy the relation of the above-mentioned formula (1), and the Schottky barrier diode having a fast rise and a low forward voltage drop. Is preferred.

Further, FIG. 14 is an example in which an inverter circuit is configured by the semiconductor device according to the sixth embodiment, and a Schottky barrier diode for protecting the control unit is provided in each of the upper arm portion 45 and the lower arm portion 46 of the inverter circuit. 27a and 27b are installed.

(Embodiment 7) FIG. 15 shows a reverse bias power source 2
5 shows a configuration of a semiconductor device in which a Schottky barrier diode 27 according to the present invention is installed in a device in which a zener diode 26 for constant voltage is connected in parallel.
Schottky barrier diode 2 during bypass
The anode voltage of 7 is fixed to the Zener voltage.

(Embodiment 8) FIG. 16 shows a control unit 20.
A case is shown in which a general rectifying diode is used as the diode 27 for protecting the rectifier. In this case, it is desirable to install the rectifying diode 28 in series with the control resistor 15 in order to secure the operation balance. If a rectifying diode 28 is installed in series with such a control resistor 15,
Since the forward voltage of the path via the parasitic diode of the transistor 23 is twice as much as that of the bias path, it becomes possible to increase the apparent threshold voltage of the switching semiconductor element such as the power MOSFET.
Since the current surely flows to the bypass path via the rectifying diode 27, it is possible to improve the noise immunity.

By the way, there is a parasitic capacitance between the gate and the source of the power MOSFET 11, and the electric charge accumulated therein must be discharged through the transistor 22 when the transistor 22 is on and the transistor 23 is off. However, as described above, when the rectifying diode 28 is inserted in order to make the bypass current flow through the rectifying diode 27 reliably, the discharge of the electric charge of the gate-source parasitic capacitance is impaired. Therefore, in order to improve this, a circuit configuration as shown in FIG. 17 is adopted.

(Embodiment 9) In the circuit configuration of FIG. 17, a diode 282 is added, which has a polarity opposite to that of the rectifier diode 28 and is connected in parallel. As a result, the charge in the gate-source parasitic capacitance 141 is rectified by the rectifier diode 2
Since it is discharged through 82, the operation of the power MOSFET can be normally performed. Since the forward voltage drop of the parasitic diode 231 and the diode 28 is larger than the forward voltage drop of the diode 27, the current flows through the diode 27 before the current flows through the parasitic diode 231. Therefore, malfunction or destruction of the transistor 23 may occur. There is no.

(Embodiment 10) FIG. 18 shows an example in which a resistor 152 is used instead of the diode 28 shown in FIG.

The resistor 152 can also discharge the charge in the gate-source parasitic capacitance 141. However, the sum of the forward voltage drop of the parasitic diode 231 and the voltage drop of the resistor 152 needs to be smaller than the forward voltage drop of the diode 27. In addition, power MOS
The gate resistance of the FET 11 is the sum of the resistance 151 and the resistance 152, and is the same as the value of the resistance 15 shown in FIG.

(Embodiment 11) FIG. 19 shows an improved example of the example shown in FIG. In the circuit configuration shown in FIG. 4, the discharge current is discharged through the diode 27 and the gate resistor 15. If the diode 27 is a Schottky barrier diode, the forward voltage drop is low and therefore discharges through this bypass path. However, if it is a rectifying diode, current may flow even through the parasitic diode 231 of the transistor 23. . Therefore, in this example, a diode 282 that blocks a reverse bias current is provided on the collector side of the transistor 23. As a result, the discharge current can be completely bypassed to the diode 27 side.

(Embodiment 12) FIG. 20 shows another improvement example. This example is different from the example of FIG. 19 in that a diode 282 for blocking a reverse bias current is provided on the emitter side of the transistor 28, and the same effect as the example of FIG. 19 can be obtained.

(Embodiment 13) FIG. 21 shows an embodiment in which the present invention is applied to an H-bridge driver circuit. Note that FIG.
27, the same parts as those shown in FIG. 27 are designated by the same reference numerals, and the description thereof will be omitted. This circuit also has an IGBT (T ₂ ) as a main switching semiconductor element and a semiconductor integrated circuit IC _{2 as a} control circuit, and a Schottky barrier diode 27 of a bypass path is provided between the collector and the emitter of the transistor 23. There is. by this,
Since the current due to the back electromotive force induced in the wiring inductance L ₁₁ can be bypassed, malfunctions and destruction of the transistors 22 and 23 can be prevented, and the power loss due to the through current can be reduced, as in the above example.

[0049]

As described above, the present invention provides the first
In addition, a current bypass path is formed by a Schottky barrier diode having a low rising voltage. Second, a current bypass path is formed by a rectifier diode, and
Since it is characterized by adopting a circuit configuration in which the discharge current is surely flown into the bypass path, the following effects are achieved.

When the bypass path is formed by using the Schottky barrier diode having a low forward-direction rising voltage and a small forward-direction voltage drop, the discharge current generated in the switching semiconductor element can flow through the control unit. It is possible. Therefore, even if the charge of the feedback capacitance when the switching semiconductor element is in the OFF state or the discharge current due to the reverse power due to the wiring inductance occurs, it is possible to prevent the malfunction and the destruction of the switching control semiconductor integrated circuit side.
Further, since it is possible to prevent the delay in the operation of the semiconductor, it is possible to suppress the through current and reduce the consumption current.

Further, even when the bypass path is formed by the rectifying diode, the above effect can be obtained by adding the voltage drop means to the discharge path on the control unit side. This is because, at the time of discharging, the voltage drop of the voltage drop means is superimposed on the voltage drop of the parasitic diode due to the reverse bias, so that the load of the bypass path becomes smaller and the discharge current inevitably flows through the bypass path.

Since the electric charge accumulated in the feedback capacitance of the switching semiconductor element may be normally discharged through the ON element of the switching control semiconductor integrated circuit, the voltage drop means rather disturbs the discharge path in the normal state. However, by providing a diode in parallel with the voltage drop means, the discharge current can be passed without any trouble.

Further, in the case where the diode for blocking the inflow current to the discharge path at the time of reverse bias is provided, the discharge current does not flow into the OFF element in the reverse bias state, and the discharge current is completely supplied only to the bypass path. It will flow.

In the case of adopting the first manufacturing method in which the Schottky barrier diode forming the bypass path is formed on the same substrate as the switching semiconductor element, not on the main surface of the semiconductor substrate but on the control electrode layer of the switching semiconductor element. Since the Schottky barrier diode can be formed, it is possible to realize not only one chip but also a layout having a high degree of freedom. Moreover, since the Schottky barrier diode can be configured by directly using the formation process of the switching semiconductor element, there is an advantage that the number of steps is not increased.

When the second manufacturing method is adopted,
Since the Schottky barrier diode can be formed not on the semiconductor substrate but on the single crystal in the same layer as the control electrode layer, the Schottky barrier diode with good characteristics can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor device according to a first embodiment of the invention.

FIG. 2 is a circuit diagram showing a configuration of a semiconductor device according to a second embodiment of the invention.

FIG. 3 is a circuit diagram showing a configuration of a semiconductor device according to a third embodiment of the present invention, (a) is a circuit diagram in which a resonance capacitor is connected in parallel to a transformer, and (b) is in series with the transformer. It is the circuit diagram connected.

FIG. 4 is a circuit diagram showing a configuration of a semiconductor device according to a fourth exemplary embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a semiconductor device according to a fifth exemplary embodiment of the present invention.

6 is a cross-sectional view showing a cross-sectional structure of the semiconductor device shown in FIG.

7 is a circuit diagram showing an equivalent circuit of the sectional structure shown in FIG.

8 is a cross-sectional view showing a cross-sectional structure of the semiconductor device shown in FIG.

9 is a sectional view showing an equivalent circuit of the sectional structure shown in FIG.

FIG. 10 is a cross-sectional view showing the manufacturing process of the semiconductor structure shown in FIG. 8;

11 is a cross-sectional view showing another cross-sectional structure of the semiconductor device shown in FIG.

FIG. 12 is a cross-sectional view showing the manufacturing process of the semiconductor structure shown in FIG. 11;

FIG. 13 is a circuit diagram showing a configuration of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 14 is a circuit diagram showing an inverter circuit configured using a semiconductor device of Example 6 according to the present invention.

FIG. 15 is a circuit diagram showing a configuration of a semiconductor device according to a seventh embodiment to which a reverse bias power source is added as in FIG.

FIG. 16 is a semiconductor device according to the present invention, in which a rectifier diode is used to form a bypass path.
3 is a circuit diagram showing the configuration of FIG.

FIG. 17 is a semiconductor device according to the present invention, in which a rectifier diode is used to form a bypass path.
3 is a circuit diagram showing the configuration of FIG.

FIG. 18 is a semiconductor device according to a first embodiment of the present invention in which a rectifier diode is used to form a bypass path.
It is a circuit diagram which shows the structure of 0.

FIG. 19 is a semiconductor device according to a first embodiment of the present invention in which a rectifying diode is used to form a bypass path.
It is a circuit diagram which shows the structure of 1.

FIG. 20 is a semiconductor device according to a first embodiment of the present invention in which a rectifier diode is used to form a bypass path.
It is a circuit diagram which shows the structure of 2.

FIG. 21 is a circuit diagram showing Embodiment 13 in which the present invention is applied to an H-type bridge driver circuit.

FIG. 22 is a circuit diagram showing a configuration of a conventional semiconductor device.

FIG. 23 is a power MO in the semiconductor device shown in FIG.
It is a graph which shows the fluctuation | variation of the voltage applied to SFET.

FIG. 24 is a circuit diagram showing a configuration of a conventional semiconductor device including a reverse bias power supply.

25A is a power M of the semiconductor device shown in FIG.
A graph showing the variation of the voltage applied to the OSFET,
(B) is a graph showing the variation of the reverse bias voltage.

FIG. 26 is a circuit diagram showing a conventional H-type bridge driver circuit.

27 is a circuit diagram showing details of a switching control semiconductor integrated circuit of the driver circuit shown in FIG.

[Explanation of symbols]

1 ... Transformer 2 ... Main power supply 3 ... Resonance capacitor 10 ... Semiconductor device 11 ... Power MOSFET 12 ... Power MOSFET control input terminal 13 ... Power MOSFET output terminal 14 ... Power MOSFET Feedback capacitance (between gate and drain) 15 ... Control resistor 16 ... Discharge current 17 ... Overcurrent detection resistor 20 ... Control unit 21 ... Switching control semiconductor integrated circuit output terminal 22 ... NPN transistor 23・ ・ PNP transistor 25 ・ ・ Reverse bias power supply 27 ・ ・ Schottky barrier diode (SBD) 28 ・ ・ Rectifier diode 38 ・ ・ n ⁺ type semiconductor substrate 39 ・ ・ n ⁻ type epitaxial layer 40 ・ ・ p type channel diffusion layer 40a ... p ⁺ -type diffusion layer 41 ... n ⁺ source region 42 ... gate insulating layer 44, Polycrystalline silicon layer 44a ··· low concentration polycrystalline silicon layer (anode electrode) 44G · · gate electrode layer 45 · · interlayer insulating layer 46 · · aluminum layer 46S · · source electrode 46 · · cathode electrode 54a · · low concentration Single-crystal silicon layer (anode electrode) 141 of the power MOSFET feedback capacitance (gate
Between sources 231 ··· Parasitic diode 282 ··· Diode T _{1 to} T ₄ · · IGBT D _{1 to} D ₄ · · Diode for absorbing back electromotive force IC _{1 to} IC ₄ · · Semiconductor integrated circuit for switching control R _{1 to} R ₄ are control resistors L ₁₁ , L ₁₂ , L ₂₁ , L ₂₂ ··· Wiring inductance L · · Inductance load

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI Technical indication location H03K 17/60 17/687 9184-5J H03K 17/60 7436-5J 17/687 B (72) Invention Person Masanori Mitamura 1-1 Tanabe Nitta, Kawasaki-ku, Kawasaki-shi, Kanagawa Fuji Electric Co., Ltd.

Claims (12)

[Claims] 1. A semiconductor device having a switching semiconductor element that conducts and blocks a current according to a control signal, and a switching control semiconductor integrated circuit including a control unit that supplies the control signal to a control input of the switching semiconductor element. The semiconductor device is characterized in that a path for current bypass is formed by a Schottky barrier diode with respect to a discharge path having a reverse bias element generated in the control unit when the switching semiconductor element is opened and closed. 2. The semiconductor device according to claim 1, wherein
The semiconductor device, wherein the bypass path includes a control resistor connected in series with the control input from the control unit. 3. The semiconductor device according to claim 1, wherein
The semiconductor device, wherein the bypass path includes an overcurrent detection resistor of the switching semiconductor element. 4. The semiconductor device according to claim 1, wherein the Schottky barrier diode is formed on the same substrate as the switching semiconductor element. 5. The semiconductor device according to any one of claims 1 to 3, wherein the Schottky barrier diode is formed on the same substrate as the switching control semiconductor integrated circuit. Semiconductor device. 6. A switching control semiconductor integrated circuit including a switching semiconductor element that conducts and blocks a current according to a control signal, a control section that supplies the control signal to a control input of the switching semiconductor element, and the control section. A semiconductor device having a control resistor connected between the control output and the control input, the rectifying diode having a reverse bias element generated in the control unit when the switching semiconductor element is opened and closed. A path for bypassing the current is formed, the bypass path includes the control resistor, and voltage drop means is connected between the output of the control unit and the control resistor. . 7. The semiconductor device according to claim 6,
A semiconductor device, wherein the voltage drop means is a rectifying diode. 8. The semiconductor device according to claim 6,
The semiconductor device, wherein the voltage drop means is a resistor. 9. The semiconductor device according to claim 6,
A semiconductor device comprising: a rectifier diode connected in parallel with the voltage drop unit and having a forward direction in a direction opposite to a voltage applied to the voltage drop unit during the reverse bias. 10. The semiconductor device according to claim 7, further comprising a diode that blocks an inflow current into the discharge path during the reverse bias. 11. The method of manufacturing a semiconductor device according to claim 4, wherein a step of forming an impurity-doped polycrystalline silicon layer of the same layer, a part of which serves as a control electrode layer of the switching semiconductor element, Masking a part of the crystalline silicon layer to further increase the impurity concentration of the polycrystalline silicon layer; and forming an insulating layer on the formed polycrystalline silicon layer having the high impurity concentration, and then forming the insulating layer. Forming a contact hole in the masked portion, and forming a metal layer of the same layer, which is to be an output electrode layer of the switching semiconductor element, on the insulating layer to form a polycrystalline silicon layer in the masked portion. And a step of bringing them into contact with each other. 12. The method of manufacturing a semiconductor device as defined in claim 4, wherein a step of forming a polycrystalline silicon layer having a high impurity concentration in the same layer, a part of which serves as a control electrode layer of the switching semiconductor element, Forming an opening in a part of the polycrystalline silicon layer; forming a single crystal silicon layer having an impurity concentration lower than the surrounding impurity concentration by epitaxial growth in the opening; A step of forming an insulating layer on the crystalline silicon layer and then forming a contact hole at the portion of the single crystal silicon layer having a low impurity concentration, and a part of the metal of the same layer to be the output electrode layer of the switching semiconductor element A step of forming a layer on the insulating layer and contacting with the single crystal silicon layer having a low impurity concentration, the method for manufacturing a semiconductor device.