JP2783191B2 - Semiconductor device protection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor devices.
ge, hereinafter referred to as “ESD”).

[0002]

2. Description of the Related Art Electrostatic discharge (ES) which is likely to occur in a field in which a semiconductor device is handled or in a manufacturing process.
D) The following three phenomena can be considered. (1) The human body handling the semiconductor device becomes an externally charged object, and the static electricity stored in the human body is released to the terminals of the device and causes destruction. (2) When an object such as a metal in the vicinity of the device is charged with static electricity, the terminal of the device comes into contact with the object, resulting in ESD destruction. (3) The device itself (device conductor portion or encapsulated plastic package) is charged with static electricity, and the static electricity is discharged from the terminal of the device to another conductor to cause destruction. Conventionally, various protection circuits for protecting the inside (circuit) of an integrated circuit from such surge due to static electricity have been put to practical use.

FIGS. 3 and 4 show the structure of a conventional protection device.

FIG. 3 shows a protection circuit disclosed in Japanese Patent Publication No. 2-52626, which is a p-channel MOS transistor TP.
The inverter 33 and the n-channel MOS transistor TN34 form an input-stage CMOS inverter I. The common gate of the inverter I is connected to the signal input terminal IN, and the common drain is connected to the next-stage circuit (not shown).
In the figure, a circuit shown in a sectional structure is a protection circuit.
In this protection circuit, at a concentration of about 1 × 10 ¹³ / cm ³ , p
A substrate obtained by growing ap ⁺ -type epitaxial layer 12 containing a p-type impurity is used as a starting substrate 13.
An n-well region 14 having a depth of about 2 μm is selectively formed thereon.

A contact region 15 containing a p-type impurity at a concentration of about 1 × 10 ¹⁹ / cm ³ for contacting the substrate 13 (p-type epitaxial layer 12) is formed on the p-type substrate 13; An n-type semiconductor region 16 containing an n-type impurity at a concentration of 1 × 10 ¹⁹ / cm ³ or more is formed.

On the n-well region 14 located on the opposite side of the regions 15 and 16 across the boundary of the n-well region 14, a p-type impurity containing p-type impurity at a concentration of 1 × 10 ¹⁹ / cm ³ or more is formed. A type semiconductor region 17 and a contact region 18 containing an n-type impurity at a concentration of about 1 × 10 ¹⁹ / cm ³ for making contact with the n-well region 14 are formed.

The p-type contact region 15, the n-type semiconductor region 16, and the p-type substrate 13 are connected to a low potential power supply V _ss , and the p-type semiconductor region 17 and the n-type contact region 18 are connected to the signal input terminal IN. It is connected to the.

In this conventional protection circuit for a complementary MOS semiconductor device, the first semiconductor region 16 is used as an emitter,
And a second semiconductor region 17 having a first polarity as a base and an n-well region 14 as a collector.
, An emitter, an n-well region 14 as a base, and a substrate 13 as a collector, the bipolar transistors of the second polarity are equivalently configured. When a high voltage is applied to the signal input terminal IN or the signal output terminal, the first Latch-up is caused in a circuit composed of bipolar transistors of a polarity and a second polarity to bypass a high-voltage current.

FIG. 4 shows the 1991 EOS / ESD SY
Another conventional example described on pages 88 to 97 of MPOSIUM PROCEEDINGS is shown. FIG.
In FIG. 7, the same regions as those in FIG. 3 are indicated by the same symbols. The difference between this conventional example and the conventional example of FIG. 3 is that the second semiconductor region 17 (emitter) is adjacent to the n-type semiconductor region 41 and the n-type semiconductor region 41 is an n-well (base).
The point is that it is formed over the region 14 and the p-type epitaxial layer 12. The protection circuit of this conventional complementary MOS semiconductor device also has the first protection circuit in the same manner as the protection circuit shown in FIG.
It comprises a bipolar transistor having a polarity and a bipolar transistor having a second polarity, and causes a latch-up to bypass a current caused by a high voltage. In this case, the trigger voltage VT (hereinafter, referred to as “turn-on voltage”) serving as a source of latch-up activation can be reduced in the protection circuit of FIG. 4 as compared with the protection circuit of FIG.

[0010]

In the thyristor type ESD protection circuit shown in FIG. 3, the turn-on voltage VT is n.
Since it is determined by the breakdown voltage of the well, it is usually as high as 50 V, which is not sufficient to protect the internal elements. Generally, the basic concept of protection circuit design is (1)
The ESD charge is absorbed by the protection element below the breakdown voltage and current of the element to be protected, (2) the protection element is not destroyed, and (3) the protection element does not impair the product characteristics within the operating range of the product. However, particularly in (1), the withstand voltage design of the protection element is the key to protection. That is, the withstand voltage BV design of the protection element must satisfy the following relation: maximum rating <BV <withstand voltage and gate breakdown voltage of the protected element. Since the gate breakdown voltage has been reduced to about 15 V with the miniaturization (higher speed) of the transistor, the protected element is not used in the low-voltage design of the conventional example shown in FIG. There is a problem that it cannot be sufficiently protected.

FIG. 4 shows a conventional example in which such a disadvantage is improved. In this case, since the withstand voltage VT is determined by the n-type semiconductor region 41 (n ⁺ ) and the p-type epitaxial layer 12 (p ⁻ ), there is an advantage that the withstand voltage VT can be set as low as ten and several volts.

However, if the protection element having this structure is applied to an actual product, there is no guarantee that the characteristics of the protection element are always stable against fluctuations in manufacturing conditions.
That is, the characteristic that the parasitic bipolar constituting the protection element keeps OFF against noise is called a dv / dt characteristic (critical off-voltage rise rate characteristic). This dv / dt is set to be large enough to prevent the protection element itself from malfunctioning. There must be. In the conventional example shown in FIG. 4, since the parasitic base resistance of the substrate 13 is large, it is difficult to design a stable dv / dt characteristic including reliability, and there is a problem that it is easily affected by fluctuations in manufacturing conditions.

The present invention has been made in view of the above points, and has as its object to provide a protection circuit for protecting a semiconductor device from high-voltage transient development caused by electrostatic discharge which is not easily affected by fluctuations in manufacturing conditions. I do.

[0014]

According to the present invention, there is provided a protection circuit for a semiconductor device having an n-type region formed on a p-type semiconductor substrate, wherein the p-type semiconductor substrate has a low potential. An n-type contact region connected to a power supply is formed, a p-type contact region connected to an input terminal or an output terminal is formed in the n-type region, and a p-type region having a higher concentration than the p-type semiconductor substrate is formed. The protective circuit of the semiconductor device was formed so as to surround the n-type region.

Further, the p-type region is formed between the n-type contact region and the p-type contact region.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1A is a sectional view of an embodiment of a protection circuit according to the present invention, and FIG. 1B is an equivalent circuit diagram thereof.

The embodiment shown in FIG. 1 is one in which the protection circuit according to the present invention is applied particularly to a semiconductor device for protecting a signal input terminal, and includes a p-channel MOS transistor TP33.
The n-channel MOS transistor TN34 forms an input-stage CMOS inverter I. The common gate of the inverter I is connected to a signal input terminal IN, and the common drain is connected to a next-stage circuit (not shown).
In the figure, the same components as those in FIG. 3 are indicated by the same symbols.
In this protection circuit, p is applied at a concentration of about 1 × 10 ¹⁵ / cm ^3.
A p-type substrate 13 containing type impurities is used.
An n-well region 14 having a depth of about 2 μm is selectively formed on 3.

[0019] On the P-type substrate 13, a contact region 15 containing P-type impurity at a concentration of about 1 × 10 ¹⁹ / cm ³ for making contact against the substrate 13, 1 × 1
An n-type semiconductor region 16 containing an n-type impurity at a concentration of 0 ¹⁹ / cm ³ or more is formed.

On the n-well region 14 located on the opposite side of the regions 15 and 16 across the boundary of the n-well region 14, a p-type impurity at a concentration of 1 × 10 ¹⁹ / cm ³ or more is doped. A contact region 18 containing an n-type impurity at a concentration of about 1 × 10 ¹⁹ / cm ³ for making contact with the P-type semiconductor region 17 and the n-well region 14 is formed.

Further, 1 × 1 around the n-well region 14
A p-well region 22 containing a P-type impurity at a concentration of 0 ¹⁷ / cm ³ or more is formed in contact with the n-type semiconductor region 16.

The p-type contact region 15, the n-type semiconductor region 16 and the P-type substrate 13 are connected to a low potential power supply V _ss , and the p-type semiconductor region 17 and the n-type contact region 18 are connected to the signal input terminal IN. It is connected.

FIG. 1B is an equivalent circuit diagram of the protection circuit according to the above embodiment. The pnp bipolar transistor 31 in the figure is formed parasitically with the P-type semiconductor region 17 as the emitter, the n-well region 14 as the base, and the P-type substrate 13 as the collector. On the other hand, an npn-type bipolar transistor 32 has an n-type semiconductor region 16 as an emitter, a p-type substrate 13 and a p-well region 22 as bases,
It is formed parasitically using the n-well region 14 as a collector. The emitter and base of the transistor 31 are both connected to the terminal IN, and the transistor 32
Are connected to the base and the collector of the transistor 31, respectively, and the base and the emitter of the transistor 32 are connected to the low potential power supply V _ss .

This embodiment can be easily manufactured by using ordinary MOS manufacturing technology. First, the p-well region 22 is selectively formed in the protection circuit formation region of the p-type substrate 13. In general, a desired profile is formed by heat treatment after boron ion implantation. Subsequently, the n-well region 14 is selectively formed. Normally, n-well region 14 is formed simultaneously with the n-well region of p-channel MOS transistor TP33. There is no difference from the conventional silicon MOS manufacturing method.
That is, the contact region 15 and the p-type semiconductor region 17
It is formed simultaneously with the source and drain of the channel MOS transistor TP33. The n-type semiconductor region 16 and the contact region 18 are formed simultaneously with the source and drain of the N-channel transistor TN34. Trigger voltage VT
(Turn-on voltage) is determined by the breakdown voltage of the junction between the n-well region 14 and the p ⁺ well region 22.

FIG. 2 shows still another embodiment of the present invention in which means for reducing the chip occupation area of the protection circuit is taken. In the drawing, the same components as those in FIG. 1 are denoted by the same reference numerals, and in this embodiment, the chip occupation area can be set to 0.25 when the conventional one is set to 1.

[0026]

As described above, in the present invention, since the p ⁺ well region 22 is formed around the n well region 14, the turn-on voltage VT of the thyristor type ESD protection element is reduced to the p ⁺ well region 22. Can be set low by adjusting the dose amount of. Therefore, as shown in the DC characteristic diagram of FIG. 1C, the n-well region 14 and the p ⁺
VT determined by the breakdown voltage of the junction of the well region 22 is 1
It can be set to about 5 to 20V.

Further, since the parasitic base resistance can be reduced by the p ⁺ well region 22, a breakdown current flows through the base resistance of the parasitic bipolar transistor, and a malfunction that causes the parasitic bipolar transistor to turn on can be prevented. Therefore, in this embodiment, it is possible to supply a high-performance protection circuit having stable dv / dt characteristics including long-term reliability and having little influence on fluctuations in manufacturing conditions.

By applying the present invention to the protection of the input terminal of a semiconductor device, it is possible to obtain a good withstand voltage of 2 KV or more by the MIL standard and 2 KV or more by the package charging method.

[Brief description of the drawings]

1A is a diagram showing a sectional structure of an embodiment of a protection circuit according to the present invention, FIG. 1B is an equivalent circuit diagram, and FIG. 1C is a DC characteristic diagram of the circuit.

FIG. 2 shows a sectional structure of another embodiment of the protection circuit according to the present invention.

FIG. 3 is a diagram illustrating a cross-sectional structure of an example of a conventional protection circuit.

FIG. 4 is a diagram showing a cross-sectional structure of another example of a conventional protection circuit.

DESCRIPTION OF SYMBOLS 11 p ⁺ -type epitaxial substrate 12 starting substrate 15 p-type contact region 17 p-type semiconductor region 22 p ⁺ well 31 pnp-type bipolar transistor 32 npn-type bipolar transistor 41 n-type semiconductor region 12 p-type epitaxial Layer 14 n-well region 16 n-type semiconductor region 18 n-type contact region 33 p-channel MOS transistor (TP) 34 n-channel MOS transistor (TN)

Claims (2)

(57) [Claims] 1. An n-type region formed on a p-type semiconductor substrate.
In the protection circuit for a semiconductor device having the same, the p-type semiconductor substrate has an n-type capacitor connected to a low potential power supply.
A contact area, and the n-type area has an input terminal.
Or p-type contact region connected to output terminal
The p-type region having a higher concentration than the p-type semiconductor substrate is
A protection circuit for a semiconductor device, wherein the protection circuit is formed so as to surround a mold region . 2. An n-type region formed on a p-type semiconductor substrate.
In the protection circuit for a semiconductor device having the same, the p-type semiconductor substrate has an n-type capacitor connected to a low potential power supply.
A contact area, and the n-type area has an input terminal.
Or p-type contact region connected to output terminal
The p-type region having a higher concentration than the p-type semiconductor substrate is
Formed between the p-type contact region and the p-type contact region
Protection circuit for a semiconductor device, characterized in that the.