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JP3150253B2 - Semiconductor device, its manufacturing method and mounting method - Google Patents

Semiconductor device, its manufacturing method and mounting method

Info

Publication number
JP3150253B2
JP3150253B2 JP17102094A JP17102094A JP3150253B2 JP 3150253 B2 JP3150253 B2 JP 3150253B2 JP 17102094 A JP17102094 A JP 17102094A JP 17102094 A JP17102094 A JP 17102094A JP 3150253 B2 JP3150253 B2 JP 3150253B2
Authority
JP
Japan
Prior art keywords
semiconductor device
conductor layer
semiconductor chip
sealing
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP17102094A
Other languages
Japanese (ja)
Other versions
JPH0837253A (en
Inventor
哲也 上田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP17102094A priority Critical patent/JP3150253B2/en
Priority to DE19526511A priority patent/DE19526511A1/en
Priority to KR1019950022303A priority patent/KR100201168B1/en
Publication of JPH0837253A publication Critical patent/JPH0837253A/en
Application granted granted Critical
Publication of JP3150253B2 publication Critical patent/JP3150253B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09709—Staggered pads, lands or terminals; Parallel conductors in different planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10439—Position of a single component
    • H05K2201/10454—Vertically mounted
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10568—Integral adaptations of a component or an auxiliary PCB for mounting, e.g. integral spacer element
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10659—Different types of terminals for the same component, e.g. solder balls combined with leads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10696—Single-in-line [SIL] package
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/167—Using mechanical means for positioning, alignment or registration, e.g. using rod-in-hole alignment
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H05K3/3426—Leaded components characterised by the leads
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】この発明は、半導体装置およびそ
の製造方法並びに実装方法に関し、特に高密度実装可能
な半導体装置の表面実装型パッケージに関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a method of manufacturing the same, and a method of mounting the same, and more particularly to a surface mounting type package of a semiconductor device capable of high-density mounting.

【０００２】[0002]

【従来の技術】近年、半導体装置の高密度実装化、表面
実装化が進んできており、それに関する技術も多数提案
されている。例えば、表面実装では、これまでのリード
を用いた実装に代わり、半導体チップを直接基板に実装
する際に用いられたバンプと呼ばれる金属突起状電極を
有し、これを再融（リフロー）して実装するという方法
を樹脂封止した半導体装置に適用しようとするものであ
る。2. Description of the Related Art In recent years, high-density mounting and surface mounting of semiconductor devices have been progressing, and a number of related technologies have been proposed. For example, in surface mounting, instead of conventional mounting using leads, there is a metal bump-shaped electrode called a bump used when mounting a semiconductor chip directly on a substrate, and this is re-melted (reflowed). The method of mounting is intended to be applied to a resin-sealed semiconductor device.

【０００３】このような表面実装の一例として、図２８
は例えば特開平１−１７９３３４号公報に記載された従
来の半導体装置の一部断面を示す外観図であり、図２９
は図２８を線ｇ−ｇ′の部分で切断して示す断面図であ
る。図において、１は半導体装置、２は半導体チップ、
３は半導体チップ上に設けられた電極としてのボンディ
ングパッド、４は半導体チップ２に取り付けられた接続
用導体、５は導体４上に設けられた半田チップ、６は半
導体チップ２を周囲環境から守るために封止する封止樹
脂である。FIG. 28 shows an example of such a surface mounting.
FIG. 29 is an external view showing a partial cross section of a conventional semiconductor device described in, for example, JP-A-1-179334.
FIG. 29 is a cross-sectional view of FIG. 28 cut along a line gg ′. In the figure, 1 is a semiconductor device, 2 is a semiconductor chip,
3 is a bonding pad as an electrode provided on the semiconductor chip, 4 is a connection conductor attached to the semiconductor chip 2, 5 is a solder chip provided on the conductor 4, and 6 is a semiconductor chip that protects the semiconductor chip 2 from the surrounding environment. Sealing resin for sealing.

【０００４】この半導体装置１は半導体チップ２の周囲
を封止樹脂６で封止し、半導体チップ２を外界環境から
防御すると共に、封止樹脂６の厚さを極力薄くし、半導
体装置１の体積を小さくして高密度実装化を図るもので
ある。また、半導体装置をバンプを用いて実装するパッ
ケージとしてＢＧＡ（Bump・Grid・Array）と呼ばれるパ
ッケージがあり、現在日本電子機械工業会（ＥＩＡＪ）
で標準化等が進められている。このＢＧＡのパッケージ
として例えば米国テセラ社のものがあり、これは半導体
チップ上にバンプを格子状に配列した回路フイルムを接
着して電気的に接続したパッケージである（Tessera′s
Compliant Chip TM Technology参照）。In the semiconductor device 1, the periphery of the semiconductor chip 2 is sealed with a sealing resin 6 to protect the semiconductor chip 2 from the external environment and reduce the thickness of the sealing resin 6 as much as possible. The purpose is to achieve high-density mounting by reducing the volume. Also, there is a package called BGA (Bump Grid Array) as a package for mounting a semiconductor device using bumps.
Is being standardized. As a package of this BGA, there is, for example, a package of Tessera's U.S.A., which is a package in which a circuit film having bumps arranged in a grid on a semiconductor chip is adhered and electrically connected (Tessera's).
Compliant Chip ™ Technology).

【０００５】さらに、半導体装置、特にメモリＩＣにお
ける高密度実装化の方法として、図３０および図３１に
示すようなＺＩＰ（Zigzag・In-like・Package）と呼ばれ
るパッケージがあり、実装面積当たりの実装密度をあげ
る手法として用いられていた。図３０はＺＩＰの外形
図、図３１はその側面図であり、図において、７はボン
ディングパッド３と電気的に接続されるリードの内、封
止樹脂６より外側の部分にある外部リードである。Further, as a method for achieving high-density mounting in a semiconductor device, particularly in a memory IC, there is a package called ZIP (Zigzag In-like Package) as shown in FIGS. 30 and 31. It was used as a technique to increase the density. FIG. 30 is an external view of the ZIP, and FIG. 31 is a side view thereof. In the drawing, reference numeral 7 denotes an external lead located outside the sealing resin 6 among leads electrically connected to the bonding pad 3. .

【０００６】ところが、ＺＩＰは貫通孔実装タイプ（基
板に穴を開け、半導体装置の外部リードを挿入して実装
するタイプ）であるため、基板の両面への実装が不可能
であり、最近の表面実装化の流れにより使用されなくな
った。そして、このＺＩＰに代わって新しく提案された
のが、図３２〜図３４に示すようなＳＶＰ（Saface・Ver
tical・Package）と呼ばれる直立表面実装型パッケージ
を有する半導体装置である。図３２はＳＶＰの外形図、
図３３は図３２においてｈ方向より見た側面図、図３４
は図３２において線ｊーｊ′の部分を切断して示す断面
図であり、図において、８はＳＶＰを立てるために通常
の外部リード７より長く、かつこの外部リード７と同一
方向および逆方向に曲げられたスタンドリードである。However, since the ZIP is a through-hole mounting type (a type in which holes are formed in a substrate and external leads of a semiconductor device are inserted), mounting on both sides of the substrate is impossible, and the recent surface It is no longer used due to the flow of implementation. A new proposal has been made in place of the ZIP, as shown in FIGS.
This is a semiconductor device having an upright surface-mount package called “tical package”. FIG. 32 is an external view of the SVP,
FIG. 33 is a side view of FIG.
32 is a cross-sectional view taken along a line JJ 'in FIG. 32, in which 8 is longer than a normal external lead 7 for erecting an SVP, and in the same direction as the external lead 7 and in the opposite direction. It is a bent stand lead.

【０００７】また、従来の半導体装置の高密度化の手法
として例えば特開平５−３０９９８３号公報に記載され
た図３５に示すような半導体装置がある。この半導体装
置はメモリカード用の半導体装置であり、ワイアボンデ
ィング法を用いているために、図３５Ｂの上向リード付
き樹脂封止型半導体装置４６の場合、上向リード４７と
樹脂封止部４３による半導体チップ４０の樹脂封止面と
の段差は、半導体チップ４０上のワイヤ４２の高さ約２
００μｍ，ワイヤ４２上の樹脂封止部４３の樹脂の厚さ
最小５０μｍ，パッケージの反り等による余裕度を約５
０μｍと見積もっても、最小３００μｍとなる。As a conventional technique for increasing the density of a semiconductor device, for example, there is a semiconductor device as shown in FIG. 35 described in Japanese Patent Application Laid-Open No. Hei 5-309983. Since this semiconductor device is a semiconductor device for a memory card and uses a wire bonding method, in the case of the resin-encapsulated semiconductor device 46 with upward leads shown in FIG. The height of the wire 42 on the semiconductor chip 40 is about 2
00 μm, the minimum resin thickness of the resin sealing portion 43 on the wire 42 is 50 μm, and the margin due to warpage of the package is about 5 μm.
Even if it is estimated to be 0 μm, the minimum is 300 μm.

【０００８】また、図３５Ａの下向リード付き樹脂封止
型半導体装置４４の場合、ワイヤ４２と半導体チップ４
０の端部の短絡を防ぐため、下向リード４５はダイパッ
ド４１より約２００μｍ半導体チップ４０の能動面（上
面）にシフトさせる必要がある。さらに、ダイパッド４
１の下部の樹脂封止部４３の樹脂の厚さが２００μｍ必
要であることから、下向リード４５と樹脂封止部４３に
よる半導体チップ４０の樹脂封止面との段差は約４００
μｍとなり、図３５Ｂの上向リード４７の場合より大き
くなる。In the case of a resin-sealed semiconductor device 44 with downward leads in FIG.
In order to prevent a short circuit at the end of 0, the downward lead 45 needs to be shifted from the die pad 41 to the active surface (upper surface) of the semiconductor chip 40 by about 200 μm. Furthermore, die pad 4
1 requires a resin thickness of 200 μm, the step between the downward lead 45 and the resin sealing surface of the semiconductor chip 40 by the resin sealing portion 43 is about 400 μm.
μm, which is larger than in the case of the upward lead 47 in FIG. 35B.

【０００９】[0009]

【発明が解決しようとする課題】従来の半導体装置は以
上のように構成されているので、以下のような問題点が
あった。すなわち、まず、特開平１−１７９３３号公報
に示された半導体装置の場合（図２８，図２９）、半田
バンプ５と半導体チップ２上の電極であるボンディング
パッド３との距離が短く、また、封止樹脂６と半田バン
プ５，接続用導体４等の金属との接着性が悪いため、封
止樹脂６と半田バンプ５，接続用導体４との界面を通し
て水が侵入し、ボンディングパッド３を腐食し、半導体
装置１が不良になるという問題点があった。Since the conventional semiconductor device is configured as described above, there are the following problems. That is, first, in the case of the semiconductor device disclosed in JP-A-1-179933 (FIGS. 28 and 29), the distance between the solder bump 5 and the bonding pad 3 as an electrode on the semiconductor chip 2 is short. Since the adhesiveness between the sealing resin 6 and the metal such as the solder bumps 5 and the connection conductors 4 is poor, water penetrates through the interface between the sealing resin 6 and the solder bumps 5 and the connection conductors 4 to cause the bonding pads 3 There is a problem that the semiconductor device 1 is corroded and becomes defective.

【００１０】また、半田バンプ５とボンディングパッド
３とが１対１で対応するため、半田バンプ５を形成する
ための半田ボール（図示せず）の数がボンディングパッ
ド３の数だけ必要となり、例えば電源供給電極や接地電
極を共有したり、半導体装置１内での回路を形成するこ
とが不可能であるという問題点があった。さらに、基板
上の外部接続用リードパターン上に半導体素子上の電極
を接合させる場合、半導体素子とベース基板に挟まれた
リードパターンと半導体素子上の電極の位置合わせが困
難であるとういう問題点があった。Further, since the solder bumps 5 and the bonding pads 3 correspond one-to-one, the number of solder balls (not shown) for forming the solder bumps 5 is required by the number of the bonding pads 3. There is a problem that it is impossible to share a power supply electrode and a ground electrode, and to form a circuit in the semiconductor device 1. Furthermore, when the electrodes on the semiconductor element are bonded to the external connection lead patterns on the substrate, it is difficult to align the electrodes on the semiconductor element with the lead patterns sandwiched between the semiconductor element and the base substrate. was there.

【００１１】また、半導体チップ上にバンプを格子状に
配列した回路フイルムを接着して電気的に接続したＢＧ
Ａのパッケージの場合、半導体チップ上は回路フィルタ
を介して外界環境に接しており、封止樹脂で被膜されて
いないため、回路フィルタの材料、特に図示せずもエラ
ストマ（弾性体）と回路を構成する金属導体，ＰＩ（ポ
リイミド）フィルムとを接着する接着剤の純度を上げ、
ボンディングパッドを腐食させるような不純物（クロル
イオン等）を排除する必要がある。また、エラストマ，
ＰＩフィルムは吸湿しやすいためこれらの材料の吸水率
を極力下げないと、半導体装置の実装時半田バンプをリ
フローする際に、エラストマ，ＰＩフィルム中の水分が
爆発的に気化し、エラストマ層やＰＩフィルムに亀裂等
を生じたり、場合によっては、導体の断線も引き起こす
可能性もある等の問題点があった。Also, a BG in which a circuit film in which bumps are arranged in a grid on a semiconductor chip is adhered and electrically connected.
In the case of the package A, since the semiconductor chip is in contact with the external environment via a circuit filter and is not coated with a sealing resin, the material of the circuit filter, particularly, an elastomer (elastic body) and a circuit (not shown) are used. Increase the purity of the adhesive that bonds the metal conductor and PI (polyimide) film
It is necessary to eliminate impurities (such as chlorine ions) that corrode the bonding pad. Also, elastomers,
Since the PI film easily absorbs moisture, if the water absorption of these materials is not reduced as much as possible, when reflowing the solder bumps when mounting the semiconductor device, the moisture in the elastomer and the PI film explosively evaporates, and the elastomer layer and the PI There have been problems such as cracks and the like in the film, and in some cases, disconnection of the conductor.

【００１２】また、ＳＶＰを有する半導体装置の場合
（図３２〜図３４）、外部リード７により基板（図示せ
ず）に接続されるが、外部リード７の強度を必要とする
点から、そのリード厚さとして0.125ｍｍ、リード幅0.2
5ｍｍが必要となり、その結果、リードピッチは0.5ｍｍ
以上が必要となり、特に多ピンパッケージ（多リードパ
ッケージ）の場合には半導体装置の外部リード７が外部
に出ている辺の長さは、そのリードの長さの制限を受け
て、半導体装置のサイズが大きくなる等の問題点があっ
た。また、ＳＶＰの外部リード７はパッケージ下面でＬ
字型に曲がっており、曲がった部分（図３４のｋ部分）
の長さが0.65〜1.20ｍｍとなっている。従って、この外
部リード７の長さがかなり長いので、半導体装置１がそ
の縦構造の偏心等により反った場合には、見かけ上リー
ド幅が増え、外部リード７のリードピッチを広くするこ
とが困難になる等の問題点があった。In the case of a semiconductor device having an SVP (FIGS. 32 to 34), the semiconductor device is connected to a substrate (not shown) by an external lead 7, but the external lead 7 requires strength. 0.125mm thickness, 0.2 lead width
5mm required, resulting in 0.5mm lead pitch
The above is necessary. Particularly, in the case of a multi-pin package (multi-lead package), the length of the side where the external lead 7 of the semiconductor device is exposed to the outside is limited by the length of the lead. There were problems such as an increase in size. The external lead 7 of the SVP is L
It is bent in the shape of a letter, and is bent (k in FIG. 34)
Has a length of 0.65 to 1.20 mm. Therefore, since the length of the external lead 7 is considerably long, when the semiconductor device 1 is warped due to the eccentricity of the vertical structure, the apparent lead width increases, and it is difficult to widen the lead pitch of the external lead 7. And other problems.

【００１３】また、通常表面実装型半導体装置を基板上
に実装する際には、スクリーン印刷法により半田ペース
トを印刷し、その半田ペーストと実装する表面実装型半
導体装置のリードとを粘着させた後リフローにより半田
ペースト内の半田を熔融させて接続するが、この場合に
は半田ペーストの厚みの最大値は、スクリーンマスクの
厚さにほぼ等しくなり、現在使用されているスクリーン
マスクが厚さ２００μｍである。従って、上述した特開
平５ー３０９９８３号公報に示された半導体装置の場合
（図３５）は、実装時に基板とリードとの段差（最小３
００μｍ）が半田ペーストの厚さ（２００μｍ）よりも
大きいため、リードと半田の接合が不可能になる、つま
り、単体での表面実装は不可能になるという問題点があ
った。Usually, when mounting a surface-mounted semiconductor device on a substrate, a solder paste is printed by a screen printing method, and the solder paste is adhered to a lead of the surface-mounted semiconductor device to be mounted. The solder in the solder paste is melted and connected by reflow. In this case, the maximum value of the thickness of the solder paste is substantially equal to the thickness of the screen mask, and the currently used screen mask has a thickness of 200 μm. is there. Therefore, in the case of the semiconductor device disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 5-309983 (FIG. 35), the step between the substrate and the lead (minimum 3
(.Mu.m) is larger than the thickness of the solder paste (200 .mu.m), so that there is a problem that joining of the lead and the solder becomes impossible, that is, surface mounting alone becomes impossible.

【００１４】この対策として、スクリーンマスクの厚さ
を３００μｍ以上とすることが考えられるが、この場
合、半田の厚さが厚くなり、また、半田印刷幅も広くな
るため、つまり、スクリーンマスクの開口幅は最小でも
スクリーンマスクの厚さは必要であるため、リードピッ
チの小さい多ピンＱＦＰ（Quad・Flat・Package）と呼ば
れるケースの四辺の方向からリードの出ているパッケー
ジ等で用いられている0.5ｍｍリードピッチの半導体装
置および狭ピッチＴＳＯＰ（Thin・Small・Outline・Packa
ge）と呼ばれるケースの二辺の方向からリードの出てい
るパッケージおよびＱＦＰのような0.65ｍｍリードピッ
チの半導体装置には半田量が多すぎてリード間の半田ブ
リッジが発生し、短絡不良となるため、汎用性がなくな
る等の問題点があった。As a countermeasure, it is conceivable that the thickness of the screen mask is 300 μm or more. In this case, however, the thickness of the solder is increased and the solder printing width is also increased. Since the thickness of the screen mask is necessary even if the width is the minimum, a multi-pin QFP (Quad / Flat / Package) having a small lead pitch is used in a package or the like in which leads come out from four sides of a case called a 0.5-pin QFP. mm lead pitch semiconductor device and narrow pitch TSOP (Thin / Small / Outline / Packa)
ge) A package having leads coming out from two sides of a case and a semiconductor device having a lead pitch of 0.65 mm such as QFP have too much solder to generate a solder bridge between the leads, resulting in a short circuit failure. Therefore, there is a problem that the versatility is lost.

【００１５】この発明はこのような問題点を解決するた
めになされたもので、耐湿性等信頼性が高くかつ高密度
の実装が可能な汎用性の優れた半導体装置およびその製
造方法並びに実装方法を得ることを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has high versatility, high reliability such as moisture resistance, and excellent versatility, and a method of manufacturing and mounting the same. The purpose is to obtain.

【００１６】[0016]

【課題を解決するための手段】請求項１の発明に係る半
導体装置は、半導体チップ上に設けられ、導体層を有す
る接着部材と、半導体チップ上に設けられた電極と導体
層とを電気的に接続する接続部材と、導体層上に設けら
れた金属突起と、半導体チップ、導体層、接着部材、接
続部材および金属突起を樹脂封止しかつ金属突起を一部
外部に露出させる封止部材と、外部に露出した金属突起
と接続された外部電極とを備えたものである。According to a first aspect of the present invention, there is provided a semiconductor device comprising: an adhesive member provided on a semiconductor chip and having a conductive layer; and an electrode and a conductive layer provided on the semiconductor chip. , A metal projection provided on the conductor layer, a sealing member for resin-sealing the semiconductor chip, the conductor layer, the adhesive member, the connection member and the metal projection, and partially exposing the metal projection to the outside And an external electrode connected to the metal projection exposed to the outside.

【００１７】請求項２の発明に係る半導体装置は、請求
項１の発明において、接着部材は、半導体チップ上に設
けられた電極と接続される櫛形導体層を有するものであ
る。According to a second aspect of the present invention, in the semiconductor device of the first aspect, the adhesive member has a comb-shaped conductor layer connected to an electrode provided on the semiconductor chip.

【００１８】請求項３の発明に係る半導体装置は、請求
項１の発明において、金属突起が露出している封止部材
の部分の周囲に凹部を設け、該凹部に上記外部電極の一
部を食い込ませたものである。According to a third aspect of the present invention, in the semiconductor device according to the first aspect of the present invention, a recess is provided around a portion of the sealing member where the metal protrusion is exposed, and a part of the external electrode is provided in the recess. It is a bite.

【００１９】請求項４の発明に係る半導体装置は、請求
項２の発明において、櫛形導体層は、電源供給または接
地電位用配線として使用されるものである。According to a fourth aspect of the present invention, in the semiconductor device of the second aspect, the comb-shaped conductor layer is used as a power supply or a ground potential wiring.

【００２０】請求項５の発明に係る半導体装置は、半導
体チップの一側に設けられた、導体層を有する接着部材
と、半導体チップの上記一側以外の部分に設けられた電
極と導体層とを電気的に接続する接続部材と、半導体チ
ップ、導体層、接着部材および接続部材を樹脂封止しか
つ導体層の一側を、封止樹脂の一側の端面の上部を半導
体チップの他側方向に後退させることにより外部に露出
させる封止部材とを備えたものである。According to a fifth aspect of the present invention, there is provided a semiconductor device comprising: an adhesive member having a conductor layer provided on one side of a semiconductor chip; and an electrode and a conductor layer provided on a portion other than the one side of the semiconductor chip. And a semiconductor chip, a conductive layer, an adhesive member, and a connecting member, which are electrically connected to each other, and one side of the conductive layer is sealed with one end of the sealing resin on the other side of the semiconductor chip. And a sealing member that is exposed to the outside by being retracted in the direction.

【００２１】請求項６の発明に係る半導体装置は、請求
項５の発明において、封止部材上に半導体チップの能動
面と垂直な方向に突出して設けられた支持部材を備えた
ものである。A semiconductor device according to a sixth aspect of the present invention is the semiconductor device according to the fifth aspect of the present invention, further comprising a support member provided on the sealing member so as to protrude in a direction perpendicular to the active surface of the semiconductor chip.

【００２２】請求項７の発明に係る半導体装置は、半導
体チップと離隔して設けられた導電性の基本部材と、こ
の基本部材上に設けられ、導体層を有する接着部材と、
半導体チップに設けられた第１および第２の電極と導体
層および基本部材とをそれぞれ電気的に接続する接続部
材と、半導体チップ、基本部材、導体層、接着部材およ
び接続部材を樹脂封止しかつ少なくとも基本部材と導体
層の一側を外部に露出させる封止部材とを備えたもので
ある。According to a seventh aspect of the present invention, there is provided a semiconductor device, comprising: a conductive basic member provided apart from a semiconductor chip; an adhesive member provided on the basic member and having a conductor layer;
A connection member for electrically connecting the first and second electrodes provided on the semiconductor chip to the conductor layer and the basic member; and a resin sealing of the semiconductor chip, the basic member, the conductor layer, the adhesive member, and the connection member. Further, at least a basic member and a sealing member for exposing one side of the conductor layer to the outside are provided.

【００２３】請求項８の発明に係る半導体装置は、半導
体チップと離隔して設けられた導電性の基本部材と、半
導体チップと離隔しかつ基本部材の周囲に設けられた導
電性の環状部材と、基本部材上に設けられ、導体層を有
する接着部材と、半導体チップに設けられた第１、第２
および第３の電極と導体層、基本部材および環状部材と
をそれぞれ電気的に接続する接続部材と、半導体チッ
プ、基本部材、環状部材、導体層、接着部材および接続
部材を樹脂封止しかつ少なくとも基本部材、環状部材お
よび導体層の一側を外部に露出させる封止部材とを備え
たものである。The semiconductor device according to an eighth aspect of the present invention is a semiconductor device, comprising: a conductive basic member provided apart from the semiconductor chip; and a conductive annular member provided apart from the semiconductor chip and provided around the basic member. An adhesive member provided on the basic member and having a conductor layer; and first and second adhesive members provided on the semiconductor chip.
And a connection member for electrically connecting the third electrode and the conductor layer, the basic member and the annular member respectively, and at least resin sealing the semiconductor chip, the basic member, the annular member, the conductor layer, the adhesive member and the connection member, and And a sealing member for exposing one side of the conductor layer to the outside.

【００２４】請求項９の発明に係る半導体装置は、請求
項７または８の発明において、封止部材より露出した基
本部材は支持用として使用されるものである。According to a ninth aspect of the present invention, in the semiconductor device of the seventh or eighth aspect, the basic member exposed from the sealing member is used for supporting.

【００２５】請求項１０の発明に係る半導体装置は、請
求項７〜９の発明において、導体層は上記封止部材より
0.2〜1.0mm程度露出されるものである。According to a tenth aspect of the present invention, in the semiconductor device according to the seventh to ninth aspects, the conductor layer is made of a material other than the sealing member.
It is exposed about 0.2 to 1.0 mm.

【００２６】請求項１１の発明に係る半導体装置は、請
求項７〜１０の発明において、封止部材より露出した導
体層は実装時基板上の配線と接続する際のヒンジとして
使用されるものである。In a semiconductor device according to an eleventh aspect of the present invention, in the invention according to the seventh to tenth aspects, the conductor layer exposed from the sealing member is used as a hinge when connecting to the wiring on the board at the time of mounting. is there.

【００２７】請求項１２の発明に係る半導体装置は、請
求項７〜１１の発明において、基本部材は接地電位用と
して使用されるものである。According to a twelfth aspect of the present invention, in the semiconductor device according to the seventh to eleventh aspects, the basic member is used for ground potential.

【００２８】請求項１３の発明に係る半導体装置は、請
求項７〜１２の発明において、基本部材は上記電極側の
表面を露出され、該露出部がワイヤボンディング可能と
されているものである。A semiconductor device according to a thirteenth aspect of the present invention is the semiconductor device according to the seventh to twelfth aspects, wherein the surface of the basic member on the electrode side is exposed, and the exposed portion can be wire-bonded.

【００２９】請求項１４の発明に係る半導体装置は、請
求項７〜１３の発明において、封止部材の上記基本部材
が露出している部分に溝部を設けたものである。A semiconductor device according to a fourteenth aspect of the present invention is the semiconductor device according to the seventh to thirteenth aspects, wherein a groove is provided in a portion of the sealing member where the basic member is exposed.

【００３０】請求項１５の発明に係る半導体装置は、請
求項８〜１４の発明において、基本部材と環状部材は電
極を挟んで相互に対向した位置に配置されるものであ
る。A semiconductor device according to a fifteenth aspect of the present invention is the semiconductor device according to the eighth to fourteenth aspects, wherein the basic member and the annular member are arranged at positions facing each other with the electrode interposed therebetween.

【００３１】請求項１６の発明に係る半導体装置は、請
求項８〜１５の発明において、基本部材と環状部材は、
電源供給または接地電位用配線として使用されるもので
ある。According to a sixteenth aspect of the present invention, in the semiconductor device according to the eighth to fifteenth aspects, the basic member and the annular member are
It is used as power supply or ground potential wiring.

【００３２】請求項１７の発明に係る半導体装置は、請
求項７〜１６の発明において、基本部材の一側は、接着
部材および導体層に対向する部分以外は削除されて櫛形
をなすものである。A semiconductor device according to a seventeenth aspect of the present invention is the semiconductor device according to the seventh to sixteenth aspects, wherein one side of the basic member has a comb shape except for a portion opposing the adhesive member and the conductor layer. .

【００３３】請求項１８の発明に係る半導体装置は、半
導体チップ上に設けられた接着部材と、この接着部材よ
り延在して半導体チップ上に設けられた電極と電気的に
接続される薄膜状の配線部材と、半導体チップ、接着部
材および配線部材を樹脂封止しかつ配線部材の一側を所
定の段差を持って外部に露出させる封止部材とを備えた
ものである。The semiconductor device according to the eighteenth aspect of the present invention is a thin-film semiconductor device provided with an adhesive member provided on the semiconductor chip and an electrode extending from the adhesive member and electrically connected to an electrode provided on the semiconductor chip. And a sealing member for sealing the semiconductor chip, the adhesive member and the wiring member with a resin, and exposing one side of the wiring member to the outside with a predetermined level difference.

【００３４】請求項１９の発明に係る半導体装置は、請
求項１８の発明において、封止部材は実装時基板と対接
する部分に該基板の配線と嵌合する位置決め凹部を有す
るものである。A semiconductor device according to a nineteenth aspect of the present invention is the semiconductor device according to the eighteenth aspect , wherein the sealing member has a positioning concave portion for fitting with the wiring of the substrate at a portion facing the substrate at the time of mounting.

【００３５】請求項２０の発明に係る半導体装置は、請
求項１８または１９の発明において、封止部材は実装時
基板と対接する部分に基板上のスルーホール等との干渉
を防ぐための逃げ凹部を有するものである。According to a twentieth aspect of the present invention, in the semiconductor device according to the eighteenth or nineteenth aspect , the sealing member has an escape recess at a portion that is in contact with the substrate during mounting to prevent interference with a through hole or the like on the substrate. It has.

【００３６】請求項２１の発明に係る半導体装置の製造
方法は、半導体チップ上に導体層を有する接着部材を貼
着す工程と、半導体チップ上に電極を形成する工程と、
電極と上記導体層とを電気的に接続する工程と、半導体
チップ、導体層、接着部材を樹脂封止する工程と、この
封止樹脂に上記導体層に達する開口部を形成する工程
と、開口部に半田を充填して外部電極を形成する工程と
を含み、開口部を樹脂封止する際の金型に設けられた突
起を導体層に所定の深さだけ押し込むように半導体チッ
プと接着部材を金型内に設置し、樹脂封止するものであ
る。According to a twenty-first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: attaching an adhesive member having a conductor layer on a semiconductor chip; and forming an electrode on the semiconductor chip.
A step of electrically connecting the electrode to the conductor layer, a step of resin sealing the semiconductor chip, the conductor layer, and the adhesive member; a step of forming an opening reaching the conductor layer in the sealing resin; Forming an external electrode by filling the portion with solder, and bonding the semiconductor chip and the adhesive member so that the projection provided on the mold when the opening is sealed with a resin is pushed into the conductor layer by a predetermined depth. Is set in a mold and sealed with a resin.

【００３７】請求項２２の発明に係る半導体装置の製造
方法は、請求項２１の発明において、半導体チップと接
着部材を金型内に設置する位置を保持するのに、接着部
材の架橋部を金型で挟むようにしたものである。According to a twenty-second aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the twenty-first aspect of the present invention, wherein a cross-link portion of the adhesive member is formed by a metal to maintain a position where the semiconductor chip and the adhesive member are set in the mold. It is designed to be sandwiched between molds.

【００３８】請求項２３の発明に係る半導体装置の製造
方法は、請求項２１または２２の発明において、開口部
に半田ボールを乗せ、リフローにより外部電極を形成す
るものである。According to a twenty- third aspect of the present invention, in the method of manufacturing a semiconductor device according to the twenty-first or twenty-second aspect , a solder ball is placed on an opening and an external electrode is formed by reflow.

【００３９】請求項２４の発明に係る半導体装置の製造
方法は、半導体チップ上に導体層を有する接着部材を貼
着する工程と、半導体チップ上に電極を形成する工程
と、電極と導体層とを電気的に接続する工程と、導体層
上にワイヤボンディング法により金属突起を形成する工
程と、半導体チップ、導体層、接着部材および金属突起
を樹脂封止しかつ金属突起を一部外部に露出させる工程
と、外部に露出した金属突起と接続される外部電極を形
成する工程とを含むものである。According to a twenty-fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: adhering an adhesive member having a conductor layer on a semiconductor chip; forming an electrode on the semiconductor chip; Electrically connecting the semiconductor chip, forming a metal protrusion on the conductor layer by a wire bonding method, sealing the semiconductor chip, the conductor layer, the adhesive member and the metal protrusion with a resin, and partially exposing the metal protrusion to the outside. And forming an external electrode connected to the metal projection exposed to the outside.

【００４０】請求項２５の発明に係る半導体装置の製造
方法は、請求項２４の発明において、金属突起を一部外
部に露出させる工程において、金属突起の高さを、該金
属突起の切り残し量を調整し、該調整された金属突起を
樹脂封止の際に樹脂封止金型に押し付けるように樹脂封
止して金属突起の一部を露出させるものである。According to a twenty-fifth aspect of the present invention, in the method for manufacturing a semiconductor device according to the twenty-fourth aspect , in the step of partially exposing the metal projection to the outside, the height of the metal projection is reduced by the uncut amount of the metal projection. Is adjusted, and the adjusted metal projection is sealed with a resin so as to be pressed against a resin sealing mold at the time of resin sealing to expose a part of the metal projection.

【００４１】請求項２６の発明に係る半導体装置の製造
方法は、半導体チップと離隔して導電性の基本部材を配
置する工程と、基本部材上に導体層を有する接着部材を
貼着する工程と、半導体チップに第１および第２の電極
を形成する工程と、第１および第２の電極とと導体層お
よび基本部材とをそれぞれ電気的に接続する工程と、半
導体チップ、基本部材、導体層および接着部材を樹脂封
止しかつ少なくとも上記基本部材と上記導体層の一側を
外部に露出させる工程とを含むものである。According to a twenty-sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: disposing a conductive basic member apart from a semiconductor chip; and adhering an adhesive member having a conductor layer on the basic member. Forming a first and a second electrode on a semiconductor chip, electrically connecting the first and second electrodes to a conductor layer and a basic member, respectively, And sealing the adhesive member with a resin and exposing at least one side of the basic member and the conductor layer to the outside.

【００４２】請求項２７の発明に係る半導体装置の製造
方法は、半導体チップと離隔して導電性の基本部材を配
置する工程と、半導体チップと離隔しかつ基本部材の周
囲に導電性の環状部材を配置する工程と、基本部材上に
導体層を有する接着部材を貼着する工程と、半導体チッ
プに第１、第２および第３の電極を形成する工程と、第
１、第２および第３の電極と導体層、基本部材および環
状部材とをそれぞれ電気的に接続する工程と、半導体チ
ップ、基本部材、環状部材、導体層および接着部材を樹
脂封止しかつ少なくとも上記基本部材、環状部材および
上記導体層の一側を外部に露出させる工程とを含むもの
である。According to a twenty-seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: disposing a conductive basic member at a distance from the semiconductor chip; and providing a conductive annular member at a distance from the semiconductor chip and around the basic member. Disposing, bonding an adhesive member having a conductor layer on a basic member, forming first, second, and third electrodes on a semiconductor chip; and forming first, second, and third electrodes on the semiconductor chip. Electrically connecting the electrode and the conductor layer, the basic member and the annular member, respectively, and sealing the semiconductor chip, the basic member, the annular member, the conductor layer and the adhesive member with resin, and at least the basic member, the annular member and Exposing one side of the conductor layer to the outside.

【００４３】請求項２８の発明に係る半導体装置の実装
方法は、請求項６，８または９記載の半導体装置を基板
に対して垂直に配置し、半導体装置内の半導体チップの
一側に貼着された接着部材上の導体層を基板の配線と電
気的に接続するようにしたものである。According to a twenty-eighth aspect of the present invention, in the semiconductor device mounting method, the semiconductor device according to the sixth, eighth, or ninth aspect is disposed vertically with respect to the substrate and attached to one side of a semiconductor chip in the semiconductor device. The conductive layer on the adhesive member is electrically connected to the wiring on the substrate.

【００４４】請求項２９の発明に係る半導体装置の実装
方法は、請求項１５記載の半導体装置の樹脂封止部分に
設けられた溝部の内、基本部材を曲げるために設けられ
ていない溝部に、隣接する他の半導体装置の支持部材を
潜り込ませて実装するようにしたものである。According to a twenty- ninth aspect of the present invention, there is provided a semiconductor device mounting method according to the fifteenth aspect, wherein, among the grooves provided in the resin-sealed portion of the semiconductor device, the grooves not provided for bending the basic member are provided. In this case, a supporting member of another adjacent semiconductor device is sunk and mounted.

【００４５】請求項３０の発明に係る半導体装置の実装
方法は、半導体装置の半導体チップ表面側の樹脂表面に
薄膜状の配線部材の貼着された接着部材を露出させるよ
うに樹脂封止し、接着部材上の配線部材と半導体装置の
樹脂表面との段差を所定値に抑え、接着部材上の配線部
材を基板に対向するように実装し、接着部材上の配線部
材を基板の配線と電気的に接続するようにしたものであ
る。In a semiconductor device mounting method according to a thirtieth aspect of the present invention, the semiconductor device is sealed with a resin so as to expose an adhesive member having a thin-film wiring member attached to a resin surface on a semiconductor chip surface side of the semiconductor device. The step between the wiring member on the adhesive member and the resin surface of the semiconductor device is suppressed to a predetermined value, the wiring member on the adhesive member is mounted so as to face the substrate, and the wiring member on the adhesive member is electrically connected to the wiring on the substrate. It is intended to be connected to.

【００４６】[0046]

【作用】請求項１の発明においては、半導体チップおよ
びその上の接着部材の周囲が封止されて耐湿性がよくな
り、また、外部電極と半導体チップ上の電極の長くして
封止樹脂と内蔵される接着部材、その上の導体層、接続
部材等との界面を伝わって侵入する水分の進行が抑えら
れ、さらに、耐湿性が向上される。また、実装密度の向
上と小型化が可能となる。According to the first aspect of the present invention, the periphery of the semiconductor chip and the adhesive member on the semiconductor chip are sealed to improve the moisture resistance. The progress of moisture that enters and penetrates the interface with the built-in adhesive member, the conductor layer thereon, the connection member, and the like is suppressed, and the moisture resistance is further improved. Further, the mounting density can be improved and the size can be reduced.

【００４７】請求項２の発明においては、接着部材が櫛
形導体層を有するので、外部電極よりの信号を半導体チ
ップ上の種々の電極へ伝達することが可能となる。According to the second aspect of the present invention, since the bonding member has the comb-shaped conductor layer, it is possible to transmit signals from the external electrodes to various electrodes on the semiconductor chip.

【００４８】請求項３の発明においては、金属突起が露
出している封止部材の部分に凹部を設けたので、外部電
極形成時に半田が凹部に流れ込み、封止樹脂と半田が機
械的にかみあい、半田と封止樹脂さらには外部電極と金
属突起との結合を強固にできる。According to the third aspect of the present invention, since the concave portion is provided in the portion of the sealing member where the metal projection is exposed, the solder flows into the concave portion when the external electrode is formed, and the sealing resin and the solder are mechanically engaged. In addition, the bonding between the solder and the sealing resin, as well as the external electrode and the metal projection can be strengthened.

【００４９】請求項４の発明においては、櫛形導体層を
電源供給用と接地用として使用できるので、半導体チッ
プ内での配線の引き回しが不要になり、配線によりイン
ダクタンスの増加が抑制されて半導体装置の動作の高速
化が可能となる。According to the fourth aspect of the present invention, since the comb-shaped conductor layer can be used for power supply and grounding, it is not necessary to route wiring in the semiconductor chip, and an increase in inductance is suppressed by the wiring. Operation can be speeded up.

【００５０】請求項５の発明においては、垂直実装によ
る実装密度の向上を図ることができる。According to the fifth aspect of the present invention, the mounting density can be improved by the vertical mounting.

【００５１】請求項６の発明においては、支持部材によ
り半導体装置を基板に対して垂直に立てることができる
ので、実装が容易となり、実装性、自立性の向上を図る
ことができる。According to the sixth aspect of the present invention, since the semiconductor device can be set upright with respect to the substrate by the support member, mounting is facilitated, and mountability and autonomy can be improved.

【００５２】請求項７の発明においては、半導体チップ
の周囲は比較的接着力が強く、吸水率の低い封止樹脂で
覆われているため、実装時の熱により実装までに吸湿し
た水の爆発による界面剥離やそれに伴う接続部材の破断
が起こりにくくなり、製品の信頼性が向上する。According to the seventh aspect of the present invention, since the periphery of the semiconductor chip is covered with a sealing resin having a relatively high adhesive strength and a low water absorption, the explosion of water absorbed by the mounting due to heat at the time of mounting. This makes it less likely that the interface will peel off and that the connecting member will break, thereby improving the reliability of the product.

【００５３】請求項８の発明においては、半導体チップ
内での配線の引き回しが不要になり、配線によりインダ
クタンスの増加が抑制されて半導体装置の動作の高速化
が可能となり、電気特性が向上する。According to the eighth aspect of the present invention, it is not necessary to route the wiring in the semiconductor chip, the increase in inductance is suppressed by the wiring, the operation speed of the semiconductor device can be increased, and the electric characteristics are improved.

【００５４】請求項９の発明においては、基本部材を支
持用として使用するため、半導体装置の自立性を向上す
ることができる。According to the ninth aspect of the present invention, since the basic member is used for supporting, the self-sustainability of the semiconductor device can be improved.

【００５５】請求項１０の発明においては、導体層が封
止部材より露出しているので、導体層と基板の配線を容
易に接続することができ、半田付けによるオープン不良
が防止される。According to the tenth aspect of the present invention, since the conductor layer is exposed from the sealing member, the conductor layer and the wiring of the substrate can be easily connected, and an open defect due to soldering is prevented.

【００５６】請求項１１の発明においては、導体層をヒ
ンジとして使用できるので、実装性、信頼性の向上を図
ることができる。According to the eleventh aspect of the present invention, since the conductor layer can be used as a hinge, the mountability and reliability can be improved.

【００５７】請求項１２の発明においては、基本部材を
接地電位用として使用できるので、半導体チップ内での
配線の引き回しが不要になり、配線によりインダクタン
スの増加が抑制されて半導体装置の動作の高速化が可能
となる。According to the twelfth aspect of the present invention, since the basic member can be used for the ground potential, it is not necessary to route the wiring in the semiconductor chip, the increase in inductance is suppressed by the wiring, and the operation speed of the semiconductor device is increased. Is possible.

【００５８】請求項１３の発明においては、基本部材の
露出部をワイヤボンディングできるので、半導体チップ
内での配線の引き回しが不要になり、配線によりインダ
クタンスの増加が抑制されて半導体装置の動作の高速化
が可能となり、また、電気特性の向上、製法の簡易化を
図ることができる。According to the thirteenth aspect of the present invention, since the exposed portion of the basic member can be wire-bonded, it is not necessary to route the wiring in the semiconductor chip, the increase in inductance is suppressed by the wiring, and the operation speed of the semiconductor device is increased. It is possible to improve the electrical characteristics and simplify the manufacturing method.

【００５９】請求項１４の発明においては、封止部材の
基本部材の露出している所に溝部を設けたので、半導体
装置の実装ピッチが小さくなり、高密度実装が可能とな
り、また、実装性を向上できる。According to the fourteenth aspect of the present invention, since the groove is provided at a position where the basic member of the sealing member is exposed, the mounting pitch of the semiconductor device is reduced, and high-density mounting is possible. Can be improved.

【００６０】請求項１５の発明においては、電極を挟ん
で基本部材と環状部材を配置したので、半導体チップ内
での配線が短くなって、半導体チップ内での信号の遅延
が減少し、また、配線によりインダクタンス量が減少し
て半導体装置の動作の高速化が可能となり、電気特性の
向上を図ることができる。According to the fifteenth aspect of the present invention, since the basic member and the annular member are arranged with the electrodes interposed therebetween, the wiring in the semiconductor chip is shortened, and the signal delay in the semiconductor chip is reduced. The amount of inductance is reduced by the wiring, the operation of the semiconductor device can be performed at high speed, and the electrical characteristics can be improved.

【００６１】請求項１６の発明においては、基本部材と
環状部材を電源供給用と接地用に使用できるので、半導
体チップ内での配線が短くなって、半導体チップ内での
信号の遅延が減少し、また、配線によりインダクタンス
量が減少して半導体装置の動作の高速化が可能となり、
電気特性の向上を図ることができる。According to the sixteenth aspect of the present invention, since the basic member and the annular member can be used for power supply and grounding, the wiring in the semiconductor chip is shortened, and the signal delay in the semiconductor chip is reduced. In addition, the amount of inductance is reduced by the wiring, and the operation of the semiconductor device can be performed at high speed.
The electrical characteristics can be improved.

【００６２】請求項１７の発明においては、基本部材の
一側を櫛形としたので、封止樹脂と基本部材の密着性が
向上し、水分の侵入を抑制し、耐湿性の劣化を防ぐこと
ができる。According to the seventeenth aspect of the present invention, since one side of the basic member is formed in a comb shape, the adhesion between the sealing resin and the basic member is improved, the penetration of moisture is suppressed, and the deterioration of moisture resistance is prevented. it can.

【００６３】請求項１８の発明においては、半導体装置
の小型化、実装密度の向上、信頼性の向上を図ることが
できる。According to the eighteenth aspect , it is possible to reduce the size, increase the mounting density, and improve the reliability of the semiconductor device.

【００６４】請求項１９の発明においては、封止部材に
位置決め凹部を設けたので、配線処理が容易となり実装
性が向上する。According to the nineteenth aspect of the present invention, since the positioning recess is provided in the sealing member, the wiring process is facilitated and the mountability is improved.

【００６５】請求項２０の発明においては、封止部材に
逃げ凹部を設けたので、位置決め凹部で概略位置合わせ
された場所から適正な実装位置へ動く、セルフアライメ
ントが可能になる。According to the twentieth aspect of the present invention, since the escape recess is provided in the sealing member, self-alignment, which is possible to move from a position roughly aligned by the positioning recess to an appropriate mounting position, is possible.

【００６６】請求項２１の発明においては、製造工程の
簡略化を図ることができ、しかも、導体層上の封止樹脂
ばりが発生して導体層と外部電極との導電性を損なうこ
とが防止される。According to the twenty-first aspect of the present invention, the manufacturing process can be simplified, and furthermore, it is possible to prevent the occurrence of sealing resin burrs on the conductor layer and to impair the conductivity between the conductor layer and the external electrodes. Is done.

【００６７】請求項２２の発明においては、半導体チッ
プと接着部材の位置決めの際に、接着部材の架橋部を金
型で挟むので、製造が容易となる。According to the twenty-second aspect of the present invention, when positioning the semiconductor chip and the adhesive member, the bridge portion of the adhesive member is sandwiched by the mold, so that the manufacturing is facilitated.

【００６８】請求項２３の発明においては、外部電極の
形成を、開口部に半田ボールを乗せて行うので、製造工
程の簡略化を図ることができる。According to the twenty- third aspect of the present invention, since the external electrodes are formed by placing the solder balls on the openings, the manufacturing process can be simplified.

【００６９】請求項２４の発明においては、簡単な製造
工程で半導体装置の小型化を図ることができる。According to the twenty-fourth aspect , the size of the semiconductor device can be reduced by a simple manufacturing process.

【００７０】請求項２５の発明においては、金属突起の
高さを調整して一部露出できるので、製造工程が簡略化
される。According to the twenty-fifth aspect of the present invention, since the height of the metal projection can be adjusted and partially exposed, the manufacturing process is simplified.

【００７１】請求項２６の発明においては、簡単な製造
工程で信頼性の高い半導体装置を得ることができる。According to the twenty-sixth aspect , a highly reliable semiconductor device can be obtained by a simple manufacturing process.

【００７２】請求項２７の発明においては、簡単な製造
工程で電気特性の優れた半導体装置を得ることができ
る。According to the twenty-seventh aspect , a semiconductor device having excellent electric characteristics can be obtained by a simple manufacturing process.

【００７３】請求項２８の発明においては、実装密度の
向上を図ることができる。According to the twenty-eighth aspect , the mounting density can be improved.

【００７４】請求項２９の発明においては、高密度実装
が可能になる。According to the twenty- ninth aspect, high-density mounting becomes possible.

【００７５】請求項３０の発明においては、高密度実装
が可能になる。According to the invention of claim 30 , high-density mounting is possible.

【００７６】[0076]

【実施例】以下、この発明の一実施例を図を参照して説
明する。 実施例１． 図１〜図４はこの発明の第１実施例を示すもので、図１
はこの発明に係る半導体装置の一部断面を示す外観図、
図２は図１の線ａ−ａ′の部分で切断して示す断面図、
図３はこの発明に係る半導体装置の製造段階における半
田バンプ作成前の断面図、図４はこの発明に係る半導体
装置の製造方法を説明するための一部断面を示す外観図
であり、各図において、図２８〜図２９と対応する部分
には同一符号を付し、その詳細説明は省略する。図にお
いて、１Ａは本実施例による半導体装置、９は半導体チ
ップ２に接着された接着部材としてのテープ、１０はテ
ープ９の上に形成された導体層、１１はワイヤボンディ
ングするための接続部材としての金属細線、１２は樹脂
封止時に樹脂封止金型（図示せず）で形成されたテープ
９上の導体層１０へ達する封止部材としての封止樹脂６
の開口部、１３はテープ９の一部をなす架橋部である。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. Embodiment 1 FIG. 1 to 4 show a first embodiment of the present invention.
Is an external view showing a partial cross section of the semiconductor device according to the present invention,
FIG. 2 is a sectional view taken along a line aa ′ in FIG.
FIG. 3 is a cross-sectional view of a semiconductor device according to the present invention before the production of solder bumps in a manufacturing stage thereof, and FIG. 4 is an external view showing a partial cross-section for explaining a method of manufacturing the semiconductor device according to the present invention. In FIG. 28, portions corresponding to those in FIGS. 28 to 29 are denoted by the same reference numerals, and detailed description thereof will be omitted. In the figure, 1A is a semiconductor device according to the present embodiment, 9 is a tape as an adhesive member adhered to the semiconductor chip 2, 10 is a conductor layer formed on the tape 9, and 11 is a connecting member for wire bonding. Is a sealing resin 6 as a sealing member that reaches the conductor layer 10 on the tape 9 formed by a resin sealing mold (not shown) during resin sealing.
The opening 13 is a bridge portion forming a part of the tape 9.

【００７７】図１および図２に示すように、半導体装置
１Ａは半導体チップ２に接着されたテープ９を有し、こ
のテープ９上に形成された導体層１０と半導体チップ２
上の電極としてのボンディングパッド３を金属細線１１
でワイヤボンディングし、導体層１０の一表面の一部を
露出するために封止樹脂６に図３に示すように開口部１
２を設ける。この開口部１２は半導体装置１Ａの製造工
程の途中の工程である樹脂封止工程で用いる樹脂封止金
型の樹脂封止部分の該当部分に設けた突起をテープ９上
の導体層１０に押し当てて形成する。そして、この開口
部１２に外部電極としての半田バンプ５を形成する。As shown in FIGS. 1 and 2, the semiconductor device 1A has a tape 9 adhered to the semiconductor chip 2, and the conductor layer 10 formed on the tape 9 and the semiconductor chip 2
The bonding pad 3 serving as the upper electrode is
In order to expose a part of one surface of the conductor layer 10, the opening 1 is formed as shown in FIG.
2 is provided. The opening 12 pushes a protrusion provided on a corresponding portion of the resin-sealed portion of the resin-sealing mold used in the resin-sealing process, which is a process in the middle of the manufacturing process of the semiconductor device 1A, against the conductor layer 10 on the tape 9. Apply to form. Then, solder bumps 5 as external electrodes are formed in the openings 12.

【００７８】樹脂封止金型の突起は、樹脂封止金型内で
テープ９上の導体層１０を例えば５〜１００μｍ程度好
ましくは数１０μｍ押し込むように設計されることによ
り、導電層１０上に封止樹脂６のばりが発生し、導電層
１０と半田バンプ５との導電性を損なうことのないよう
に工夫されている。従って、樹脂封止金型の突起が導電
層１０を押し込むことによるストレスは、テープ９の弾
性により吸収されるため、半導体チップ２ヘの損傷はな
い。The protrusion of the resin-sealing mold is designed so that the conductor layer 10 on the tape 9 is pressed into the resin-sealing mold by, for example, about 5 to 100 μm, preferably several tens μm. It is designed so as not to cause burrs of the sealing resin 6 and impair the conductivity between the conductive layer 10 and the solder bumps 5. Therefore, the stress caused by the protrusion of the resin sealing mold pressing the conductive layer 10 is absorbed by the elasticity of the tape 9, so that the semiconductor chip 2 is not damaged.

【００７９】また、図３の半導体装置１Ａの実質的に中
間製造物に半田バンプ５を形成するときには、半田ボー
ル（図示せず）を開口部１２に配置しリフローすること
により、同じ樹脂封止金型で形成する外形との位置精度
を数μｍの精度で半田バンプ５が精度よく形成できる。
また、図４に示すように、テープ９の一部を半導体装置
１Ａの予定外形部分より突出させて架橋部１３を設け、
半導体装置１Ａを樹脂封止する際に樹脂封止金型で挟
み、半導体チップ２およびテープ９の樹脂封止金型内で
の位置を固定するようにし、樹脂封止金型に設けたテー
プ９上の導体層１０と接触させ、半田バンプ５とのコン
タクトを得るために設けられた樹脂封止部６の開口部１
２を形成する。これにより、樹脂封止金型に設けた突起
と、テープ９上の導体層１０との接触を確実なものと
し、テープ９上の導体層１０と樹脂封止金型に設けた突
起の間の樹脂のにじみ出しによる封止樹脂ばりの発生が
抑えられる。When the solder bumps 5 are formed substantially on an intermediate product of the semiconductor device 1A shown in FIG. 3, solder balls (not shown) are disposed in the openings 12 and reflowed to form the same resin sealing. The solder bumps 5 can be formed with high accuracy with a positional accuracy of several μm with respect to the outer shape formed by the mold.
As shown in FIG. 4, a part of the tape 9 is protruded from the planned outer shape of the semiconductor device 1 </ b> A to provide a bridge portion 13.
When the semiconductor device 1A is sealed with a resin, the semiconductor chip 2 and the tape 9 are sandwiched by the resin sealing mold so that the positions of the semiconductor chip 2 and the tape 9 in the resin sealing mold are fixed. Opening 1 of resin sealing portion 6 provided to make contact with upper conductor layer 10 and obtain contact with solder bump 5
Form 2 Thereby, the contact between the protrusion provided on the resin sealing mold and the conductor layer 10 on the tape 9 is ensured, and the contact between the conductor layer 10 on the tape 9 and the protrusion provided on the resin sealing mold is ensured. The occurrence of sealing resin burrs due to oozing of the resin is suppressed.

【００８０】実施例２． 図５〜図８はこの発明の第２実施例を示すもので、図５
はこの発明に係る半導体装置の一部断面を示す外観図、
図６は図５の線ｋーｋ′の部分で切断して示す断面図、
図７はこの発明に係る半導体装置の製造段階における樹
脂封止前の状態を示す断面図、図８はこの発明に係る半
導体装置の製造方法を説明するための一部断面図であ
り、各図において、図１〜図４と対応する部分には同一
符号を付し、その詳細説明は省略する。図において、１
Ｂは本実施例による半導体装置、１４はワイヤボンディ
ング技術を用いて半導体チップ１０上に形成された金属
突起、１５はテープ９上に形成された櫛形導体層であっ
て、この櫛形導体層１５はテープ９上の導体層の一部を
なすもので、櫛形状をしており、テープ９上の複数の導
体層の部分よりワイヤボンディングを行うものである。
１６は半田バンプ５と金属突起１４との接合性を向上す
るため、封止樹脂部６に設けられた凹部と嵌合する半田
バンプ５の凸部である。Embodiment 2 FIG. 5 to 8 show a second embodiment of the present invention.
Is an external view showing a partial cross section of the semiconductor device according to the present invention,
FIG. 6 is a sectional view taken along a line kk ′ of FIG. 5,
FIG. 7 is a cross-sectional view showing a state before resin sealing in a manufacturing stage of the semiconductor device according to the present invention, and FIG. 8 is a partial cross-sectional view for explaining a method of manufacturing the semiconductor device according to the present invention. In the figure, the same reference numerals are given to portions corresponding to FIGS. 1 to 4 and the detailed description thereof is omitted. In the figure, 1
B is a semiconductor device according to the present embodiment, 14 is a metal projection formed on the semiconductor chip 10 using a wire bonding technique, 15 is a comb-shaped conductor layer formed on the tape 9, and this comb-shaped conductor layer 15 It forms a part of the conductor layer on the tape 9 and has a comb shape, and performs wire bonding from a plurality of conductor layers on the tape 9.
Reference numeral 16 denotes a convex portion of the solder bump 5 that fits into a concave portion provided in the sealing resin portion 6 in order to improve the bonding property between the solder bump 5 and the metal protrusion 14.

【００８１】従来よりワイヤボンディング技術による金
属突起の形成は、半導体チップ２上のボンディングパッ
ド３にバンプを形成し、ＴＡＢ（Tape・Automated・Bondi
ng）テープと接合する場合に用いられるが、本実施例で
は、テープ９上の導体層１０に上述のワイヤボンデイン
グ技術により金属突起１４を形成する。これにより、上
述した特開平１−１７９３３４号公報に示されているよ
うな複雑な工程の方法を取る必要がなくなり、また、後
述の基板１８（図１１）のようなベース基板に半導体素
子をフェイスダウンボンディング（後述の図２７のよう
に能動素子等の半導体素子を下方に向けテボンディング
する方法）する際の位置決めの困難さがなくなる。Conventionally, a metal projection is formed by a wire bonding technique by forming a bump on a bonding pad 3 on a semiconductor chip 2 and forming a TAB (Tape Automated Bondi).
In this embodiment, the metal projections 14 are formed on the conductor layer 10 on the tape 9 by the above-described wire bonding technique. As a result, it is not necessary to adopt a complicated process as shown in the above-mentioned Japanese Patent Application Laid-Open No. 1-179334, and the semiconductor element is mounted on a base substrate such as a substrate 18 (FIG. 11) described later. This eliminates the difficulty of positioning during down bonding (a method in which a semiconductor element such as an active element is downwardly te-bonded as shown in FIG. 27 described later).

【００８２】なお、上述したワイヤボンデイング技術を
用いた金属突起の形成時の材料として半田ワイヤを用い
るとリフロー時に半田バンプ５と融着し、高い強度が得
られる。また、導電層１０を有するテープ９上に櫛形導
電層１５を備えているので、テープ９上の複数の部分よ
り半導体チップ２との接続が可能となる。これにより、
例えば、半導体装置１Ｂの１つの半田バンプ５からの信
号を半導体チップ２内の種々のボンディングパッド３へ
伝達することが可能となる。さらに、櫛形導電層１５を
電源供給用配線または接地配線とし、半導体チップ２内
の複数の位置への電源供給、接地を行うようにしてもよ
い。これにより、半導体チップ２内でのアルミ配線によ
る引き回しが不要となり、配線によるインダクタンスの
増加を抑え、半導体装置の高速化が可能となる。When a solder wire is used as a material when forming the metal projections using the above-described wire bonding technique, the solder bump is fused to the solder bump 5 during reflow, and high strength is obtained. Further, since the comb-shaped conductive layer 15 is provided on the tape 9 having the conductive layer 10, the connection with the semiconductor chip 2 can be made from a plurality of portions on the tape 9. This allows
For example, a signal from one solder bump 5 of the semiconductor device 1B can be transmitted to various bonding pads 3 in the semiconductor chip 2. Furthermore, the comb-shaped conductive layer 15 may be used as a power supply wiring or a ground wiring to supply and ground power to a plurality of positions in the semiconductor chip 2. This eliminates the need for wiring with aluminum wiring in the semiconductor chip 2, suppresses an increase in inductance due to wiring, and enables a high-speed semiconductor device.

【００８３】図７において、点線部分は樹脂封止される
部分の予想線である。図７に示すように、ワイヤボンデ
イング技術により形成された金属突起１４は、樹脂封止
される予想線より突出しており、樹脂封止金型内で金属
突起１４が金型内部に押し当てられ、樹脂封止後には金
属突起１４が封止樹脂面より露出するようになされてい
る。つまり、ワイヤボンデイング技術により形成される
金属突起１４の高さは、金属突起１４自体の切り残し量
を制御することにより調整し、樹脂封止工程の段階で金
属突起１４を樹脂封止金型に押し付けるように樹脂封止
し、金属突起１４の一部を露出させる。これにより、製
造が容易となる。In FIG. 7, a dotted line is a predicted line of a portion to be sealed with resin. As shown in FIG. 7, the metal protrusion 14 formed by the wire bonding technique protrudes from a predicted line to be resin-sealed, and the metal protrusion 14 is pressed against the inside of the resin-sealing mold, After the resin sealing, the metal projections 14 are exposed from the sealing resin surface. That is, the height of the metal projection 14 formed by the wire bonding technique is adjusted by controlling the uncut amount of the metal projection 14 itself. Resin sealing is performed so as to be pressed, and a part of the metal protrusion 14 is exposed. This facilitates manufacture.

【００８４】図８において、半田バンプ５を形成する部
分に嵌合するように封止樹脂６に凹部を設ける。する
と、半田バンプ５の形成時にこの凹部に半田が流れ込
み、封止樹脂６と半田が機械的にかみ合い、半田バンプ
５と封止樹脂６、さらには、半田バンプ５と金属突起１
４との接合が強固になる。なお、櫛形導体層１５は実施
例１の半導体装置にも適用してもよい。In FIG. 8, a concave portion is provided in the sealing resin 6 so as to fit into a portion where the solder bump 5 is formed. Then, when the solder bumps 5 are formed, the solder flows into the concave portions, and the sealing resin 6 and the solder are mechanically engaged with each other, so that the solder bumps 5 and the sealing resin 6, and further, the solder bumps 5 and the metal protrusions 1 are formed.
4 becomes stronger. Note that the comb-shaped conductor layer 15 may be applied to the semiconductor device of the first embodiment.

【００８５】実施例３． 図９〜図１２はこの発明の第３実施例を示すもので、図
９はこの発明に係る半導体装置の一部を示す外観図、図
１０はこの発明に係る半導体装置の一部断面を示す外観
図、図１１はこの発明に係る半導体装置の実装時の一部
を示す外観図、図１２は図１１の線ｂーｂ′の部分で切
断して示す断面図であり、各図において、図１〜図４と
対応する部分には同一符号を付し、その詳細説明は省略
する。図において、１Ｃは本実施例による半導体装置、
１７は半導体装置１Ｃを後述の基板に対して立てるため
のスタンドロック、１８は半導体装置１Ｃを実装するた
めの基板、１９は基板１８に設けられた配線、２０は配
線１９と導電層１０とを接続するための半田である。Embodiment 3 FIG. 9 to 12 show a third embodiment of the present invention. FIG. 9 is an external view showing a part of a semiconductor device according to the present invention, and FIG. 10 is a partial cross section of the semiconductor device according to the present invention. FIG. 11 is an external view showing a part of the semiconductor device according to the present invention at the time of mounting, and FIG. 12 is a cross-sectional view taken along a line bb 'in FIG. 1 to 4 are denoted by the same reference numerals, and detailed description thereof will be omitted. In the figure, 1C is a semiconductor device according to the present embodiment,
Reference numeral 17 denotes a stand lock for standing the semiconductor device 1C with respect to a substrate described later, reference numeral 18 denotes a substrate for mounting the semiconductor device 1C, reference numeral 19 denotes a wiring provided on the substrate 18, and reference numeral 20 denotes a connection between the wiring 19 and the conductive layer 10. Solder for connection.

【００８６】図９において、半導体装置１Ｃは導電層１
０を有するテープ９を半導体チップ２の一辺に貼り付
け、テープ９およびテープ９上の導電層１０を含む平面
の一部を帯状に封止樹脂６より露出させる。そして、図
１０に示すように、テープ９上に形成された導体層１０
と半導体チップ２上のボンディングパッド３を金属細線
１１でワイヤボンディングする。また、図１１におい
て、基板１８に半導体装置１Ｃを、その内部の半導体チ
ップ２が基板１８に対して垂直となるように実装すると
共に、基板１８上に配線１９と半導体装置１Ｃの露出さ
れたテープ９上の導体層１０とを垂直に交差するように
半田付けして実装する。In FIG. 9, the semiconductor device 1C has a conductive layer 1
A tape 9 having a zero is adhered to one side of the semiconductor chip 2, and a part of a plane including the tape 9 and the conductive layer 10 on the tape 9 is exposed in a band shape from the sealing resin 6. Then, as shown in FIG. 10, the conductor layer 10 formed on the tape 9 is formed.
And the bonding pads 3 on the semiconductor chip 2 are wire-bonded with the fine metal wires 11. In FIG. 11, the semiconductor device 1C is mounted on the substrate 18 so that the semiconductor chip 2 therein is perpendicular to the substrate 18, and the wiring 19 and the exposed tape of the semiconductor device 1C are mounted on the substrate 18. 9 and the conductor layer 10 is mounted by soldering so as to vertically intersect.

【００８７】また、半導体装置１Ｃには、半導体チップ
２の素子面と垂直な方向に延在するスタンドブロック１
７を樹脂封止工程で形成し、半導体装置１Ｃの一側面お
よびスタンドブロック１７の一面で上記一側面と同一面
を水平にするようになされる。これにより、半導体装置
１Ｃを基板１８に対して図１１および図１２に示すよう
に垂直に実装することができる。なお、ここでは、半導
体チップ２はテープ９により保持された状態で樹脂封止
されるが、慣用の半導体装置のように、半導体チップ２
をダイパッドと呼ばれるリードフレームの一部に接着
し、保持するようにしてもよい。The semiconductor device 1 C includes a stand block 1 extending in a direction perpendicular to the element surface of the semiconductor chip 2.
7 are formed in a resin sealing step, and one side surface of the semiconductor device 1C and one side surface of the stand block 17 are made to be horizontal with the one side surface. As a result, the semiconductor device 1C can be mounted vertically on the substrate 18 as shown in FIGS. Here, the semiconductor chip 2 is sealed with a resin while being held by the tape 9. However, as in a conventional semiconductor device, the semiconductor chip 2
May be adhered to a part of a lead frame called a die pad and held.

【００８８】実施例４． 図１３〜図１９はこの発明の第４実施例を示すもので、
図１３はこの発明に係る半導体装置の一部を示す外観
図、図１４はこの発明に係る半導体装置の一部断面を示
す外観図、図１５はこの発明に係る半導体装置の実装時
の一部を示す外観図、図１６は図１５の線ｃーｃ′の部
分で切断して示す断面図、図１７はこの発明に係る半導
体装置の実装時の状態を示す平面図、図１８はこの発明
に係る半導体装置を複数個実装時の状態を示す平面図、
同じく図１９はこの発明に係る半導体装置を複数個実装
時の状態を示す平面図であり、各図において、図１〜図
４および図１１，図１２と対応する部分には同一符号を
付し、その詳細説明は省略する。図において、１Ｄは本
実施例による半導体装置、２１は半導体チップ２を接着
し、保持するためのリードフレームの一部であるダイパ
ッド、２２は導体層１０を有するテープ９を接着して保
持し、半導体チップ２より浮かせるリードフレームの一
部である基本部材としてのベースリードであって、この
ベースリード２２によりスタンドリード８が形成され
る。２３はスタンドリード８の屈曲部を収納する封止樹
脂６の溝部である。Embodiment 4 FIG. 13 to 19 show a fourth embodiment of the present invention.
13 is an external view showing a part of the semiconductor device according to the present invention, FIG. 14 is an external view showing a partial cross section of the semiconductor device according to the present invention, and FIG. 15 is a part of the semiconductor device according to the present invention when mounted. FIG. 16 is a cross-sectional view taken along a line cc 'of FIG. 15, FIG. 17 is a plan view showing a state of mounting the semiconductor device according to the present invention, and FIG. Plan view showing a state when mounting a plurality of semiconductor devices according to the
Similarly, FIG. 19 is a plan view showing a state in which a plurality of semiconductor devices according to the present invention are mounted. In each figure, the same reference numerals are given to parts corresponding to FIGS. 1 to 4 and FIGS. , And a detailed description thereof will be omitted. In the figure, 1D is a semiconductor device according to the present embodiment, 21 is a die pad which is a part of a lead frame for bonding and holding the semiconductor chip 2, 22 is bonding and holding a tape 9 having a conductor layer 10, The base lead 22 is a base lead as a basic member which is a part of a lead frame floating above the semiconductor chip 2, and the base lead 22 forms the stand lead 8. Reference numeral 23 denotes a groove of the sealing resin 6 that accommodates the bent portion of the stand lead 8.

【００８９】本実施例では、導体層１０を有するテープ
９は、半導体チップ２上の一辺上にこれと離れて配置さ
れたベースリード２２上に接着される。なお、図１４で
は、ベースリード２２はリードフレーム枠部（図示せ
ず）から切り取り、曲げる前の状態を示している。一
方、半導体チップ２はリードフレームの一部であるダイ
パッド２１上に接着され固定される。これにより、テー
プ９を直接半導体チップ２上に貼り付けた上述の実施例
１の半導体装置１Ａの場合と異なり、半導体チップ２の
周囲は比較的接着力が強く、吸水率の低い封止樹脂６で
覆われているため、半導体チップ２とテープ９の界面の
接着層に比べて実装時の熱により実装までに吸湿した水
の爆発による界面剥離およびそれに伴う金属細線１１の
破断が起こりにくくなり、製品の信頼性が向上する。In this embodiment, the tape 9 having the conductor layer 10 is adhered to the base lead 22 disposed on one side of the semiconductor chip 2 and apart from the side. Note that FIG. 14 shows a state before the base lead 22 is cut off from a lead frame frame (not shown) and bent. On the other hand, the semiconductor chip 2 is bonded and fixed on a die pad 21 which is a part of a lead frame. Thus, unlike the case of the semiconductor device 1A of the above-described first embodiment in which the tape 9 is directly attached to the semiconductor chip 2, the sealing resin 6 having a relatively strong adhesive force around the semiconductor chip 2 and having a low water absorption rate. As a result, compared to the adhesive layer at the interface between the semiconductor chip 2 and the tape 9, the interface peeling due to the explosion of water absorbed before the mounting due to the heat at the time of mounting and the accompanying breakage of the thin metal wires 11 are less likely to occur, Product reliability is improved.

【００９０】また、本実施例では、図１３からも分かる
ように、テープ９上の導体層１０を封止樹脂６の部分よ
り所定の長さ例えば0.2〜１ｍｍ程度突出させ、この導
体層１０を図１６に示すようにヒンジ（同図において導
体層１０がＬ字状に曲がっている部分）のように基板１
８上の配線１９と位置合わせして半田２０により半田付
けを行う。これにより、上述の実施例３の半導体装置１
Ｃの場合よりテープ９上の導体層１０と基板１８上の配
線１９との半田付けによる接続不良（オープン不良）が
低減される。Further, in this embodiment, as can be seen from FIG. 13, the conductor layer 10 on the tape 9 is protruded from the portion of the sealing resin 6 by a predetermined length, for example, about 0.2 to 1 mm. As shown in FIG. 16, the substrate 1 is a hinge (a portion where the conductor layer 10 is bent in an L-shape in FIG. 16).
The soldering is performed with the solder 20 in alignment with the wiring 19 on the wiring 8. Thereby, the semiconductor device 1 of the third embodiment described above
The connection failure (open failure) due to soldering between the conductor layer 10 on the tape 9 and the wiring 19 on the substrate 18 is reduced as compared with the case C.

【００９１】また、本実施例では、ベースリード２２を
接地電位とし、このベースリード２２がテープ９上の導
体層１０より低インピーダンスとなるように設計する。
これにより、半導体装置１Ｄの高速動作が可能になる。
さらに、図１４に示すように、テープ９をベースリード
２２の一部に接着し、ベースリード２２の半導体チップ
２の内側（ボンディングパッド３が配置されている所）
に近い部分を帯状に露出させる。これにより、接地電位
にあるベースリード２２の任意の部分から半導体チップ
２上の任意の接地電位を必要とするボンディングパッド
３と接続することが可能となり、半導体チップ２内のア
ルミ配線の引き回しが短くなり、それだけ信号の遅延量
も少なくなって半導体装置１Ｄの高速動作が可能にな
る。ちなみに、図１４では、８本の金属細線１１の内、
図面に向かって左より第１番目，第５番目および第７番
目の金属細線１１が接地電位用として半導体チップ２上
のボンディングパッド３とそれぞれ接続されている。In the present embodiment, the base lead 22 is set to the ground potential, and the base lead 22 is designed to have a lower impedance than the conductor layer 10 on the tape 9.
Thereby, high-speed operation of the semiconductor device 1D becomes possible.
Further, as shown in FIG. 14, the tape 9 is adhered to a part of the base lead 22, and the inside of the semiconductor chip 2 of the base lead 22 (where the bonding pad 3 is disposed).
Is exposed in a strip shape. This makes it possible to connect any portion of the base lead 22 at the ground potential to the bonding pad 3 requiring an arbitrary ground potential on the semiconductor chip 2, thereby shortening the routing of the aluminum wiring in the semiconductor chip 2. As a result, the amount of signal delay is reduced accordingly, and the semiconductor device 1D can operate at high speed. By the way, in FIG. 14, among the eight metal wires 11,
The first, fifth, and seventh metal wires 11 from the left in the drawing are connected to the bonding pads 3 on the semiconductor chip 2 for ground potential.

【００９２】図１７は半導体装置１Ｄのベースリード２
２に連なる外部リードとしてのスタンドリード８の曲げ
方向を示しており、この図１７のように、２本の外部リ
ードを互いに異なる方向に曲げることにより、図３２に
示したＳＶＰのように４本の外部リードを用いることな
く同様の自立性を得ることができる。ことにより、同一
の外形のパッケージの場合、ＳＶＰに比べて２本の外部
リードを余分にテープ９上の導体層１０を設けることが
できる。FIG. 17 shows a base lead 2 of the semiconductor device 1D.
FIG. 17 shows the bending direction of the stand lead 8 as an external lead connected to the second external lead 2. By bending the two external leads in different directions from each other, as shown in FIG. 17, four stand leads 8 as in the SVP shown in FIG. The same independence can be obtained without using external leads. Thus, in the case of a package having the same outer shape, the conductor layer 10 on the tape 9 can be provided with two extra external leads as compared with the SVP.

【００９３】図１８は半導体装置１Ｄを並列に実装した
場合を示しており、半導体装置１ＤがメモリＩＣの場合
に予想される実装方法のうち、スタンドリード８の屈曲
部を収納する封止樹脂６の溝部２３内に隣接する半導体
装置１Ｄのスタンドリード８を入れずに実装した場合で
ある。また、図１９は図１８と同様に半導体装置１Ｄを
並列に実装した場合であるが、図１９ではスタンドリー
ド８の屈曲部を収納する封止樹脂６の溝部２３内に隣接
する半導体装置１Ｄのスタンドリード８を潜り込ませて
実装した場合である。このように、スタンドリード８の
屈曲部を収納する封止樹脂６の溝部２３内に隣接する半
導体装置１Ｄのスタンドリード８を潜り込ませることに
より、半導体装置１Ｄの実装ピッチが小さくなり、高密
度実装が可能となる。なお、テープ９上の導体層１０を
封止樹脂６の部分より所定の長さ例えば0.2〜１ｍｍ程
度突出させ、この導体層１０をヒンジのように基板１８
上の配線１９と位置合わせして半田２０により半田付け
を行うことは、他のＳＶＰの半導体装置にも適用しても
よい。FIG. 18 shows a case where the semiconductor devices 1D are mounted in parallel. Among the mounting methods expected when the semiconductor device 1D is a memory IC, the sealing resin 6 for accommodating the bent portion of the stand lead 8 is shown. In this case, the semiconductor device 1D is mounted without inserting the stand leads 8 of the adjacent semiconductor device 1D into the groove 23 of FIG. FIG. 19 shows a case where the semiconductor devices 1D are mounted in parallel as in FIG. 18, but in FIG. 19, the semiconductor device 1D adjacent to the groove 23 of the sealing resin 6 accommodating the bent portion of the stand lead 8 is shown. This is a case where the stand lead 8 is mounted so as to be sunk. As described above, by allowing the stand leads 8 of the adjacent semiconductor device 1D to sink into the groove portions 23 of the sealing resin 6 accommodating the bent portions of the stand leads 8, the mounting pitch of the semiconductor devices 1D is reduced, and high-density mounting is achieved. Becomes possible. The conductor layer 10 on the tape 9 is protruded from the portion of the sealing resin 6 by a predetermined length, for example, about 0.2 to 1 mm.
Performing the soldering with the solder 20 in alignment with the upper wiring 19 may be applied to other SVP semiconductor devices.

【００９４】実施例５． 図２０〜図２３はこの発明の第５実施例を示すもので、
図２０はこの発明に係る半導体装置の製造段階における
リード加工工程前の一部断面を示す外観図、図２１はこ
の発明に係る半導体装置の実装時の一部を示す外観図、
図２２は図２１の矢印ｄの方向から見た側面図、図２３
はこの発明に係る半導体装置のベースリード、テープ、
リングリード等の構成要素の一部を示す外観図であり、
各図において、図１〜図４および図１１，図１２，図１
５と対応する部分には同一符号を付し、その詳細説明は
省略する。図において、１Ｅは本実施例による半導体装
置、２４はベースリード２２の外側にベースリード２２
を囲むように配置された環状部材としてのリングリー
ド、２５はベースリード２２の一部をなし、ベースリー
ド２２とテープ９および封止樹脂６の接着性を向上させ
るために設けられたベースリードの櫛歯部である。Embodiment 5 FIG. 20 to 23 show a fifth embodiment of the present invention.
FIG. 20 is an external view showing a partial cross section before a lead processing step in a manufacturing stage of the semiconductor device according to the present invention, FIG. 21 is an external view showing a part of the semiconductor device according to the present invention at the time of mounting,
FIG. 22 is a side view as seen from the direction of arrow d in FIG.
Is a semiconductor device according to the present invention base lead, tape,
It is an external view showing a part of components such as a ring lead,
In each figure, FIGS. 1 to 4 and FIGS.
The same reference numerals are given to the portions corresponding to 5 and their detailed description is omitted. In the figure, 1E is the semiconductor device according to the present embodiment, and 24 is the base lead 22 outside the base lead 22.
The ring lead 25 as an annular member disposed so as to surround the base lead 22 forms a part of the base lead 22 and is formed of a base lead provided to improve the adhesion between the base lead 22 and the tape 9 and the sealing resin 6. Comb part.

【００９５】図２０において、半導体チップ２上の一列
に並んだボンディングパッド３を挟んでベースリード２
２と反対側を通るようにかつベースリード２２の周囲に
リングリード２３を設け、ベースリード２２とリングリ
ード２３を各々電源供給電位または接地電位とする。こ
れにより、半導体チップ２内の任意のボンディングパッ
ド３に電源供給を行い、または、接地を行うことがで
き、半導体チップ２内のアルミ配線を短くし、半導体チ
ップ２内の信号の遅延を減少させると共に、電源供給お
よび接地に関与するリードのインダクタンス量を減少さ
せるため、上述した実施例４の半導体装置１Ｄの場合よ
りさらに動作を高速化することができる。In FIG. 20, the base leads 2 are sandwiched between the bonding pads 3 arranged in a row on the semiconductor chip 2.
A ring lead 23 is provided so as to pass through the side opposite to the side 2 and around the base lead 22, and the base lead 22 and the ring lead 23 are set to a power supply potential or a ground potential, respectively. Thus, power can be supplied to any bonding pad 3 in the semiconductor chip 2 or grounding can be performed, thereby shortening the aluminum wiring in the semiconductor chip 2 and reducing signal delay in the semiconductor chip 2. At the same time, since the inductance of the leads involved in power supply and grounding is reduced, the operation can be performed at a higher speed than in the case of the semiconductor device 1D of the fourth embodiment.

【００９６】図２１において、ベースリード２２、リン
グリード２４の一部封止樹脂６より出た部分をスタンド
リード８として用いる。ここでは、両端の２本ずつ合計
４本のスタンドリード８は、各々片端の２本が上述した
ＳＶＰのように異なる方向に曲げられる。図２２におい
て、一部スタンドリード８と、このスタンドリード８の
屈曲部を収納する封止樹脂６の溝部２３を点線で表して
いる。図２３において、ベースリード２２の一部、テー
プ９の下部、テープ９上の導体層１０の下部以外のとこ
ろを削除し、櫛歯状にした場合のベースリード２２、導
体層１０を有するテープ９、およびリングリード２３を
示しており、テープ９をベースリード２２から離した状
態である。In FIG. 21, the portions of the base lead 22 and the ring lead 24 that have come out of the sealing resin 6 are used as stand leads 8. Here, a total of four stand leads 8, two at each end, are bent in different directions like the above-mentioned SVP with two at each end. In FIG. 22, a part of the stand lead 8 and the groove 23 of the sealing resin 6 that accommodates the bent portion of the stand lead 8 are indicated by dotted lines. In FIG. 23, a part of the base lead 22, the lower part of the tape 9, and the part other than the lower part of the conductor layer 10 on the tape 9 are deleted to form a comb-shaped base lead 22 and a tape 9 having the conductor layer 10. , And a ring lead 23 in a state where the tape 9 is separated from the base lead 22.

【００９７】図２３に示すように、ベースリード２２の
一部、テープ９上の導体層１０の下部以外の所を削除し
たことにより、半導体装置１Ｅの製造工程で、半導体チ
ップ２上のボンディングパッド３とテープ９上の導体層
１０とを金属細線１１で接合する場合に、テープ９上の
導体層１０への金属細線１１のワイヤボンディング性を
損なうことがない。これは、ワイヤボンディンするテー
プ９上の導体層１０の下部にはベースリード２２が存在
するため、ワイヤボンディング時の荷重を有効に使い得
るからで、下地が軟らかいとボンディング荷重が減少す
るためボンディング剥がれが生じる。また、封止後封止
樹脂６とベースリード２２の密着性を向上するために、
封止樹脂６とベースリード２２の界面を通して水分の侵
入を抑え、耐湿性の劣化を抑制できる。ベースリード２
２とテープ９および封止樹脂６の接着性を向上させるた
めに設けられたベースリードの櫛歯部２５は、他の実施
例におけるベースリード２２にも同様に適用してもよ
い。As shown in FIG. 23, by removing a part of the base lead 22 and a portion other than the lower part of the conductor layer 10 on the tape 9, the bonding pad on the semiconductor chip 2 is manufactured in the manufacturing process of the semiconductor device 1E. When the metal wire 3 and the conductor layer 10 on the tape 9 are joined by the thin metal wire 11, the wire bonding property of the thin metal wire 11 to the conductor layer 10 on the tape 9 is not impaired. This is because the base lead 22 exists under the conductor layer 10 on the tape 9 to be wire-bonded, so that the load at the time of wire bonding can be used effectively. Peeling occurs. In order to improve the adhesion between the sealing resin 6 and the base lead 22 after the sealing,
Intrusion of moisture through the interface between the sealing resin 6 and the base lead 22 can be suppressed, and deterioration of moisture resistance can be suppressed. Base lead 2
The comb teeth 25 of the base lead provided for improving the adhesiveness between the tape 2 and the tape 9 and the sealing resin 6 may be similarly applied to the base lead 22 in another embodiment.

【００９８】実施例６． 図２４および図２５はこの発明の第６実施例を示すもの
で、図２４はこの発明に係る半導体装置の一部断面を示
す外観図、図２５は図２４の線ｅーｅ′の部分で切断し
て示す断面図であり、各図において、図１〜図４と対応
する部分には同一符号を付し、その詳細説明は省略す
る。図において、１Ｆは本実施例による半導体装置、２
６は半導体チップ２上に設けられた接着部材としてのＴ
ＡＢテープ、２７はＴＡＢテープ２６上の外部電極とし
ての配線、２８はＴＡＢテープ２６の内部リード、２９
はＴＡＢテープ２６上の櫛形配線、３０はＴＡＢテープ
２６の架橋部、３１はボンディングパッド３上に設けら
れたバンプである。Embodiment 6 FIG. 24 and 25 show a sixth embodiment of the present invention. FIG. 24 is an external view showing a partial cross section of a semiconductor device according to the present invention, and FIG. 25 is a portion taken along line ee 'in FIG. FIG. 5 is a cross-sectional view cut away. In each drawing, the same reference numerals are given to portions corresponding to FIGS. In the figure, 1F is the semiconductor device according to the present embodiment,
Reference numeral 6 denotes T as an adhesive member provided on the semiconductor chip 2.
AB tape; 27, wiring as external electrodes on the TAB tape 26; 28, internal leads of the TAB tape 26;
Is a comb-shaped wiring on the TAB tape 26, 30 is a bridge portion of the TAB tape 26, and 31 is a bump provided on the bonding pad 3.

【００９９】図２４において、ＴＡＢ技術を用い、ＴＡ
Ｂテープ２６の内部リード２８の先端部と半導体チップ
２のボンディングパッド３とをバンプ３１と呼ばれる金
属突起電極を介して接続する。ＴＡＢテープ２６の樹脂
封止部分より外側の破線で示すＴＡＢテープの架橋部３
０は実施例１における架橋部１３（図４）と同様、封止
金型内での半導体チップ２の位置固定、半田バンプ５を
形成するために、封止樹脂６に設けた凹部を形成するた
めの封止金型の突起をＴＡＢテープ２６上に圧接させる
ことを可能にする。その後このＴＡＢテープの架橋部３
０はその役目が終わると切断される。In FIG. 24, using TAB technology, TA
The tips of the internal leads 28 of the B tape 26 and the bonding pads 3 of the semiconductor chip 2 are connected via metal bump electrodes called bumps 31. Bridge portion 3 of TAB tape indicated by a broken line outside the resin sealing portion of TAB tape 26
Reference numeral 0 denotes a recess provided in the sealing resin 6 for fixing the position of the semiconductor chip 2 in the sealing mold and forming the solder bumps 5 as in the case of the bridging portion 13 (FIG. 4) in the first embodiment. To press the projection of the sealing die for pressing on the TAB tape 26. Then, the bridging part 3 of this TAB tape
0 is cut off when its role is over.

【０１００】また、ＴＡＢ技術を用いる場合は、実施例
１の半導体装置１Ａの場合と異なり、ＴＡＢテープ２６
の内部リード２８がＴＡＢテープ２６の位置より上に存
在せずとも半導体チップ２との接続が可能となる。つま
り、ＴＡＢテープ２６上の封止樹脂６の厚さを抑え、半
導体装置１Ｆを小型化することができる。なお、バンプ
３１はボンディングパッド３の上に設けてもよいし、あ
るいは、ＴＡＢテープ２６の内部リード２８側に設けて
もよい。また、本実施例では、ＴＡＢテープ２６と半導
体チップ２とが接着した状態で示されているが、半導体
チップ２はＴＡＢテープ９より出ている内部リード２８
で吊り下げることも可能であり、必ずしも接着の必要性
はない。When the TAB technique is used, unlike the semiconductor device 1A of the first embodiment, the TAB tape 26
Can be connected to the semiconductor chip 2 even if the internal lead 28 does not exist above the position of the TAB tape 26. That is, the thickness of the sealing resin 6 on the TAB tape 26 can be suppressed, and the semiconductor device 1F can be downsized. The bump 31 may be provided on the bonding pad 3 or may be provided on the internal lead 28 side of the TAB tape 26. In this embodiment, the TAB tape 26 and the semiconductor chip 2 are shown in a bonded state, but the semiconductor chip 2 has internal leads 28 protruding from the TAB tape 9.
It is also possible to hang it, and it is not always necessary to bond it.

【０１０１】実施例７． 図２６および図２７はこの発明の第７実施例を示すもの
で、図２６はこの発明に係る半導体装置の一部断面を示
す外観図、図２７は図２６の線ｆーｆ′の部分で切断し
て示す断面図であり、各図において、図１〜図４および
図１１，図１２，図１５，図２４と対応する部分には同
一符号を付し、その詳細説明は省略する。図において、
１Ｇは本実施例による半導体装置、３２は半導体装置１
Ｇの表面に金型を用いて形成され、基板１８の配線２７
と嵌合する位置決め凹部、３３は基板１８に形成された
スルーホール、３４は基板１８のスルーホール３３等と
の干渉を防ぐために半導体装置１Ｇの表面に金型を用い
て形成された逃げ凹部である。Embodiment 7 FIG. 26 and 27 show a seventh embodiment of the present invention. FIG. 26 is an external view showing a partial cross section of a semiconductor device according to the present invention. FIG. 27 is a portion taken along line ff 'of FIG. FIG. 4 is a cross-sectional view cut away, and in each figure, the same reference numerals are given to parts corresponding to FIGS. 1 to 4 and FIGS. 11, 12, 15, and 24, and the detailed description thereof is omitted. In the figure,
1G is the semiconductor device according to the present embodiment, 32 is the semiconductor device 1
The wiring 27 of the substrate 18 is formed on the surface of G using a mold.
33 is a through hole formed in the substrate 18, and 34 is an escape concave formed using a mold on the surface of the semiconductor device 1 </ b> G to prevent interference with the through hole 33 of the substrate 18. is there.

【０１０２】本実施例では、半導体チップ２上に配線２
７を有するＴＡＢテープ２６を設け、配線２７と半導体
チップ２とを電気的に接続すると共に、ＴＡＢテープ２
６上の配線２７が帯状に露出するように樹脂封止し、樹
脂封止面とＴＡＢテープ２６上の配線２７の段差を２０
０μｍ以下に抑え、半導体装置１ＧのＴＡＢテープ２６
上の配線２７を下にして、かつ配線２７と基板１８上の
配線１９とを位置決めした後半田付けが可能なパッケー
ジとする。このように、封止樹脂面と配線２７との段差
を２００μｍ以下に抑えたので、例えばスクリーン印刷
による半田塗布時の半田とＴＡＢテープ２６上の配線２
７が接触してリフロー後のオープン不良が発生すること
がなくなる。また、半導体装置１Ｇは封止樹脂より側面
に突出するリードフレームが存在しないので、実装時に
必要な面積が小さくなり、高密度実装が可能となる。In this embodiment, the wiring 2 is provided on the semiconductor chip 2.
7 is provided, the wiring 27 is electrically connected to the semiconductor chip 2, and the TAB tape 2 is electrically connected to the semiconductor chip 2.
6 is sealed with resin so that the wiring 27 on the tape 6 is exposed in a strip shape, and the step between the resin sealing surface and the wiring 27 on the TAB tape 26 is set to 20 degrees.
0 μm or less, TAB tape 26 of semiconductor device 1G
A package that can be soldered after the upper wiring 27 is positioned down and the wiring 27 and the wiring 19 on the substrate 18 are positioned. As described above, since the step between the sealing resin surface and the wiring 27 is suppressed to 200 μm or less, for example, when the solder is applied by screen printing and the wiring 2 on the TAB tape 26 is formed.
7 does not come into contact and an open defect after reflow does not occur. Further, since the semiconductor device 1G does not have a lead frame projecting to the side surface from the sealing resin, the area required for mounting is reduced, and high-density mounting is possible.

【０１０３】また、本実施例では、基板１８上の配線１
９と嵌合する位置決め凹部３２を半導体装置１Ｇと基板
１８上の配線１９との位置決めを概略行うようにしてい
る。これにより、実装が容易となり、実装性が向上す
る。また、本実施例では、半導体装置１Ｇの表面に金型
を用いて逃げ凹部３４を形成する。これにより、基板１
８上の配線１９以外の例えばスルーホール３３等の部分
と半導体装置１Ｇとの干渉を防ぎ、位置決め凹部３２の
効果を充分なものとすると共に、半導体装置１Ｇと基板
１８との接触面積を少なくして、半田リフロー時の半導
体装置１Ｇが微少に動き、位置決め凹部３２によって概
略位置合わせされた場所から適正な実装位置へ動くいわ
ゆるセルフアライメントが可能になる。In this embodiment, the wiring 1 on the substrate 18
The positioning recess 32 that fits with the semiconductor device 9 is designed to roughly position the semiconductor device 1 </ b> G and the wiring 19 on the substrate 18. This facilitates mounting and improves mountability. In this embodiment, the escape recess 34 is formed on the surface of the semiconductor device 1G using a mold. Thereby, the substrate 1
In addition to preventing interference between the semiconductor device 1G and a portion such as the through hole 33 other than the wiring 19 on the wiring 8, the effect of the positioning recess 32 is made sufficient, and the contact area between the semiconductor device 1G and the substrate 18 is reduced. Therefore, the so-called self-alignment in which the semiconductor device 1 </ b> G at the time of solder reflow slightly moves and moves from a position roughly aligned by the positioning recess 32 to an appropriate mounting position.

【０１０４】また、図２６に示すように、半導体装置１
Ｇの表面、半導体チップ２の表面と同じ側に半導体装置
１Ｇの表面より最大２００μｍへこんだ部分にある電極
面と基板１８上の配線１９とを半田ペーストを介して接
着した後リフローする。図中、符号ｍは半導体装置１Ｇ
の表面と電極面すなわち配線２７との段差を表し、最大
２００μｍであり、符号ｎは半田ペーストの厚さで、通
常最大２００μｍである。なお、ここでは、ＴＡＢテー
プ２６上の配線２７と半導体チップ２との電気的な接続
にＴＡＢ法を用いているため、図中、ｍの樹脂厚さは内
部リード２８が封止樹脂６の通して見え、不良となる限
界概ね５０μｍまで薄くすることができる。Also, as shown in FIG.
The electrode surface on the same side as the surface of the semiconductor device 1G on the same side as the surface of the semiconductor chip 2 and the wiring 19 on the substrate 18 is bonded via a solder paste, and then reflowed. In the figure, the symbol m indicates the semiconductor device 1G
And the step between the electrode surface, that is, the wiring 27, is a maximum of 200 μm, and the symbol n is the thickness of the solder paste, which is usually a maximum of 200 μm. In this case, since the TAB method is used for electrical connection between the wiring 27 on the TAB tape 26 and the semiconductor chip 2, in FIG. It can be thinned down to a limit of about 50 μm at which it becomes defective.

【０１０５】[0105]

【発明の効果】以上のように請求項１の発明によれば、
半導体チップ上に設けられ、導体層を有する接着部材
と、半導体チップ上に設けられた電極と導体層とを電気
的に接続する接続部材と、導体層上に設けられた金属突
起と、半導体チップ、導体層、接着部材、接続部材およ
び金属突起を樹脂封止しかつ金属突起を一部外部に露出
させる封止部材と、外部に露出した金属突起と接続され
た外部電極とを備えたので、耐湿性がよくなって信頼性
を向上でき、また、電気特性、実装密度および汎用性の
向上を図ることができつと共に、小型化が可能となると
いう効果がある。As described above, according to the first aspect of the present invention,
An adhesive member provided on the semiconductor chip and having a conductor layer, a connection member for electrically connecting an electrode provided on the semiconductor chip to the conductor layer, a metal protrusion provided on the conductor layer, and the semiconductor chip Since the conductor layer, the adhesive member, the connection member and the metal protrusion are resin-sealed and the sealing member for partially exposing the metal protrusion to the outside, and the external electrode connected to the metal protrusion exposed to the outside, The moisture resistance is improved, reliability can be improved, and electrical characteristics, mounting density, and versatility can be improved, and downsizing can be achieved.

【０１０６】請求項２の発明によれば、請求項１の発明
において、接着部材は、半導体チップ上に設けられた電
極と接続される櫛形導体層を有するので、請求項１また
は２の発明の効果に加えて、外部電極よりの信号を半導
体チップ上の種々の電極へ伝達することが可能となると
いう効果がある。According to the second aspect of the present invention, in the first aspect of the present invention, the bonding member has a comb-shaped conductor layer connected to an electrode provided on the semiconductor chip. In addition to the effect, there is an effect that signals from external electrodes can be transmitted to various electrodes on the semiconductor chip.

【０１０７】請求項３の発明によれば、請求項１の発明
において、金属突起が露出している封止部材の部分の周
囲に凹部を設け、該凹部に上記外部電極の一部を食い込
ませたので、請求項２の発明の効果に加えて、外部電極
形成時に半田が凹部に流れ込み、封止樹脂と半田が機械
的にかみあい、半田と封止樹脂さらには外部電極と金属
突起との結合を強固にできるという効果がある。According to the third aspect of the present invention, in the first aspect of the present invention, a concave portion is provided around a portion of the sealing member where the metal projection is exposed, and a part of the external electrode is made to bite into the concave portion. Therefore, in addition to the effect of the invention of claim 2, when the external electrode is formed, the solder flows into the concave portion, the sealing resin and the solder are mechanically engaged, and the solder and the sealing resin, and furthermore, the bonding between the external electrode and the metal projection. There is an effect that can be strengthened.

【０１０８】請求項４の発明によれば、請求項２の発明
において、櫛形導体層は、電源供給または接地電位用配
線として使用されるので、請求項３の発明の効果に加え
て、半導体チップ内での配線の引き回しが不要になり、
配線によりインダクタンスの増加が抑制されて半導体装
置の動作の高速化が可能となるという効果がある。According to a fourth aspect of the present invention, in the second aspect of the present invention, the comb-shaped conductor layer is used as a power supply or a ground potential wiring. It is not necessary to route the wiring inside
There is an effect that the increase in inductance is suppressed by the wiring and the operation of the semiconductor device can be performed at high speed.

【０１０９】請求項５の発明によれば、半導体チップの
一側に設けられた、導体層を有する接着部材と、半導体
チップの上記一側以外の部分に設けられた電極と導体層
とを電気的に接続する接続部材と、半導体チップ、導体
層、接着部材および接続部材を樹脂封止しかつ導体層の
一側を、封止樹脂の一側の端面の上部を半導体チップの
他側方向に後退させることにより外部に露出させる封止
部材とを備えたので、垂直実装による実装密度の向上と
信頼性および汎用性の向上を図ることができるという効
果がある。According to the fifth aspect of the present invention, the adhesive member having a conductor layer provided on one side of the semiconductor chip, and the electrode and the conductor layer provided on a portion other than the one side of the semiconductor chip are electrically connected. The connection member, the semiconductor chip, the conductor layer, the adhesive member and the connection member, which are to be electrically connected, are resin-sealed, and one side of the conductor layer is moved toward the other side of the semiconductor chip with the upper end of one side of the sealing resin. Since a sealing member that is exposed to the outside by being retracted is provided, there is an effect that the mounting density and reliability and versatility can be improved by vertical mounting.

【０１１０】請求項６の発明によれば、請求項５の発明
において、封止部材上に半導体チップの能動面と垂直な
方向に突出して設けられた支持部材を備えたので、請求
項６の発明の効果に加えて、実装が容易となり、実装
性、自立性の向上を図ることができるという効果があ
る。According to the invention of claim 6, according to the invention of claim 5, the supporting member is provided on the sealing member so as to protrude in a direction perpendicular to the active surface of the semiconductor chip. In addition to the effects of the invention, there is an effect that mounting is facilitated, and mountability and autonomy can be improved.

【０１１１】請求項７の発明によれば、半導体チップと
離隔して設けられた導電性の基本部材と、この基本部材
上に設けられ、導体層を有する接着部材と、半導体チッ
プに設けられた第１および第２の電極と導体層および基
本部材とをそれぞれ電気的に接続する接続部材と、半導
体チップ、基本部材、導体層、接着部材および接続部材
を樹脂封止しかつ少なくとも基本部材と導体層の一側を
外部に露出させる封止部材とを備えたので、実装時の熱
により実装までに吸湿した水の爆発による界面剥離やそ
れに伴う接続部材の破断が起こりにくくなり、製品の信
頼性を向上でき、また、実装密度、電気特性および汎用
性の向上を図ることができるという効果がある。According to the seventh aspect of the present invention, a conductive basic member provided separately from the semiconductor chip, an adhesive member provided on the basic member and having a conductive layer, and provided on the semiconductor chip. A connection member for electrically connecting the first and second electrodes to the conductor layer and the basic member, and a resin sealing of the semiconductor chip, the basic member, the conductor layer, the adhesive member and the connection member, and at least the basic member and the conductor With a sealing member that exposes one side of the layer to the outside, interface peeling due to the explosion of water absorbed before mounting due to heat during mounting and the resulting breakage of the connecting member are less likely to occur, and product reliability is reduced. In addition, there is an effect that mounting density, electric characteristics and versatility can be improved.

【０１１２】請求項８の発明によれば、半導体チップと
離隔して設けられた導電性の基本部材と、半導体チップ
と離隔しかつ基本部材の周囲に設けられた導電性の環状
部材と、基本部材上に設けられ、導体層を有する接着部
材と、半導体チップに設けられた第１、第２および第３
の電極と導体層、基本部材および環状部材とをそれぞれ
電気的に接続する接続部材と、半導体チップ、基本部
材、環状部材、導体層、接着部材および接続部材を樹脂
封止しかつ少なくとも基本部材、環状部材および導体層
の一側を外部に露出させる封止部材とを備えたので、半
導体チップ内での配線の引き回しが不要になり、配線に
よりインダクタンスの増加が抑制されて半導体装置の動
作の高速化が可能となり、電気特性を向上でき、また、
実装密度、信頼性および汎用性の向上を図ることができ
るという効果がある。According to the eighth aspect of the present invention, a conductive basic member provided apart from the semiconductor chip, a conductive annular member provided around the basic member and separated from the semiconductor chip, An adhesive member provided on the member and having a conductor layer, and first, second and third members provided on the semiconductor chip;
A connection member for electrically connecting the electrode and the conductor layer, the basic member and the annular member, respectively, and a semiconductor chip, the basic member, the annular member, the conductor layer, the adhesive member and the connection member resin-sealed and at least the basic member, The provision of the annular member and the sealing member for exposing one side of the conductive layer to the outside eliminates the need for wiring in the semiconductor chip, and suppresses an increase in inductance due to the wiring, thereby increasing the speed of operation of the semiconductor device. And electrical characteristics can be improved.
There is an effect that mounting density, reliability, and versatility can be improved.

【０１１３】請求項９の発明によれば、請求項７または
８の発明において、封止部材より露出した基本部材は支
持用として使用されるので、請求項８または９の発明の
効果に加えて、半導体装置の自立性を向上することがで
きるという効果がある。According to the ninth aspect of the present invention, in the seventh or eighth aspect, the basic member exposed from the sealing member is used for supporting. In addition, there is an effect that the independence of the semiconductor device can be improved.

【０１１４】請求項１０の発明によれば、請求項７〜９
の発明において、導体層は上記封止部材より0.2〜1.0mm
程度露出されるので、請求項７〜９の発明の効果に加え
て、導体層と基板の配線を容易に接続することができ、
半田付けによるオープン不良が防止されるという効果が
ある。According to the tenth aspect, the seventh to ninth aspects are described.
In the invention, the conductor layer is 0.2 to 1.0 mm from the sealing member
To the extent that the conductor layer and the wiring of the substrate can be easily connected in addition to the effects of the inventions of claims 7 to 9.
This has the effect of preventing open defects due to soldering.

【０１１５】請求項１１の発明によれば、請求項７〜１
０の発明において、封止部材より露出した導体層は実装
時基板上の配線と接続する際のヒンジとして使用される
ので、導体層をヒンジとして使用できるので、請求項７
〜１０の発明の効果に加えて、実装性、信頼性の向上を
図ることができるという効果がある。According to the eleventh aspect of the present invention, 7-1 to 7-1
According to the present invention, since the conductor layer exposed from the sealing member is used as a hinge when connecting to the wiring on the board at the time of mounting, the conductor layer can be used as a hinge.
In addition to the effects of the present invention, there is an effect that the mountability and the reliability can be improved.

【０１１６】請求項１２の発明によれば、請求項７〜１
１の発明において、基本部材は接地電位用として使用さ
れるので、請求項７〜１１の発明の効果に加えて、半導
体チップ内での配線の引き回しが不要になり、配線によ
りインダクタンスの増加が抑制されて半導体装置の動作
の高速化が可能となるという効果がある。According to the twelfth aspect of the present invention, the seventh to first aspects are provided.
In the first aspect of the present invention, since the basic member is used for the ground potential, in addition to the effects of the seventh to eleventh aspects, the wiring in the semiconductor chip becomes unnecessary, and the increase in inductance by the wiring is suppressed. Thus, there is an effect that the operation speed of the semiconductor device can be increased.

【０１１７】請求項１３の発明によれば、請求項７〜１
２の発明において、基本部材は上記電極側の表面を露出
され、該露出部がワイヤボンディング可能とされている
ので、請求項７〜１２の発明の効果に加えて、半導体チ
ップ内での配線の引き回しが不要になり、配線によりイ
ンダクタンスの増加が抑制されて半導体装置の動作の高
速化が可能となり、また、電気特性の向上、製法の簡易
化を図ることができるという効果がある。According to the thirteenth aspect, the seventh to first aspects are described.
According to the second aspect of the present invention, since the surface of the basic member on the electrode side is exposed, and the exposed portion can be wire-bonded. Wiring is not required, and an increase in inductance is suppressed by wiring, so that operation of the semiconductor device can be performed at high speed. Further, there is an effect that electric characteristics can be improved and a manufacturing method can be simplified.

【０１１８】請求項１４の発明によれば、請求項７〜１
３の発明において、封止部材の上記基本部材が露出して
いる部分に溝部を設けたので、請求項７〜１３の発明の
効果に加えて、半導体装置の実装ピッチが小さくなり、
高密度実装が可能となり、また、実装性を向上できると
いう効果がある。According to the fourteenth aspect, claims 7-1
According to the third aspect of the present invention, since the groove is provided in a portion of the sealing member where the basic member is exposed, in addition to the effects of the seventh to thirteenth aspects, the mounting pitch of the semiconductor device is reduced,
This has the effect of enabling high-density mounting and improving mountability.

【０１１９】請求項１５の発明によれば、請求項８〜１
４の発明において、基本部材と環状部材は電極を挟んで
相互に対向した位置に配置されるので、請求項８〜１４
の発明の効果に加えて、半導体チップ内での配線が短く
なって、半導体チップ内での信号の遅延が減少し、ま
た、配線によりインダクタンス量が減少して半導体装置
の動作の高速化が可能となり、電気特性の向上を図るこ
とができるという効果がある。According to the fifteenth aspect, claims 8 to 1 are provided.
In the invention according to the fourth aspect, the basic member and the annular member are arranged at positions facing each other with the electrode interposed therebetween.
In addition to the effect of the invention, the wiring in the semiconductor chip is shortened, the signal delay in the semiconductor chip is reduced, and the inductance is reduced by the wiring, so that the operation of the semiconductor device can be speeded up. Thus, there is an effect that the electrical characteristics can be improved.

【０１２０】請求項１６の発明によれば、請求項８〜１
５の発明において、基本部材と環状部材は、電源供給ま
たは接地電位用配線として使用されるので、請求項８〜
１５の発明の効果に加えて、半導体チップ内での配線が
短くなって、半導体チップ内での信号の遅延が減少し、
また、配線によりインダクタンス量が減少して半導体装
置の動作の高速化が可能となり、電気特性の向上を図る
ことができるという効果がある。According to the sixteenth aspect, claims 8 to 1 are provided.
In the invention of claim 5, the basic member and the annular member are used as power supply or ground potential wiring.
In addition to the effects of the fifteenth aspect, the wiring in the semiconductor chip is shortened, the signal delay in the semiconductor chip is reduced,
Further, there is an effect that the amount of inductance is reduced by the wiring, the operation of the semiconductor device can be performed at high speed, and the electrical characteristics can be improved.

【０１２１】請求項１７の発明によれば、請求項７〜１
６の発明において、基本部材の一側は、接着部材および
導体層に対向する部分以外は削除されて櫛形をなすの
で、請求項７〜１６の発明の効果に加えて、封止樹脂と
基本部材の密着性が向上し、水分の侵入を抑制し、耐湿
性の劣化を防ぐことができるという効果がある。According to the seventeenth aspect, claims 7-1
According to the sixth aspect of the present invention, one side of the basic member is comb-shaped by removing portions other than the portion facing the adhesive member and the conductor layer. Therefore, in addition to the effects of the inventions of claims 7 to 16, the sealing resin and the basic member are provided. Has the effect of improving the adhesion of water, suppressing the intrusion of moisture, and preventing the deterioration of moisture resistance.

【０１２２】請求項１８の発明によれば、半導体チップ
上に設けられた接着部材と、この接着部材より延在して
半導体チップ上に設けられた電極と電気的に接続される
薄膜状の配線部材と、半導体チップ、接着部材および配
線部材を樹脂封止しかつ配線部材の一側を所定の段差を
持って外部に露出させる封止部材とを備えたので、半導
体装置の小型化、実装密度、汎用性、信頼性および電気
特性の向上を図ることができるという効果がある。According to the eighteenth aspect of the present invention, the adhesive member provided on the semiconductor chip and the thin-film wiring extending from the adhesive member and electrically connected to the electrode provided on the semiconductor chip. Since the semiconductor device includes a member and a sealing member for sealing the semiconductor chip, the adhesive member and the wiring member with resin and exposing one side of the wiring member to the outside with a predetermined step, the semiconductor device can be reduced in size and mounting density. There is an effect that versatility, reliability and electrical characteristics can be improved.

【０１２３】請求項１９の発明によれば、請求項１８の
発明において、封止部材は実装時基板と対接する部分に
該基板の配線と嵌合する位置決め凹部を有するので、請
求項１８の発明の効果に加えて、配線処理が容易となり
実装性が向上するという効果がある。[0123] According to the invention of claim 19, in the invention of claim 18, since the sealing member has a positioning recess for wiring and fitting of the substrate to the mounting when the substrate and the paired contact portions, the invention of claim 18 In addition to the effects described above, there is an effect that wiring processing is facilitated and mountability is improved.

【０１２４】請求項２０の発明に係る半導体装置は、請
求項１８または１９の発明において、封止部材は実装時
基板と対接する部分に基板上のスルーホール等との干渉
を防ぐための逃げ凹部を有するので、請求項１８または
１９の発明の効果に加えて、位置決め凹部で概略位置合
わせされた場所から適正な実装位置へ動く、セルフアラ
イメントが可能になるという効果がある。According to a twentieth aspect of the present invention, in the semiconductor device according to the eighteenth or nineteenth aspect , the sealing member has an escape recess for preventing interference with a through-hole or the like on the substrate at a portion in contact with the substrate during mounting. Claim 18 or
In addition to the effects of the nineteenth invention, there is an effect that the self-alignment is enabled, moving from a position roughly aligned by the positioning recess to an appropriate mounting position.

【０１２５】請求項２１の発明によれば、半導体チップ
上に導体層を有する接着部材を貼着す工程と、半導体チ
ップ上に電極を形成する工程と、電極と上記導体層とを
電気的に接続する工程と、半導体チップ、導体層、接着
部材を樹脂封止する工程と、この封止樹脂に上記導体層
に達する開口部を形成する工程と、開口部に半田を充填
して外部電極を形成する工程とを含み、開口部を樹脂封
止する際の金型に設けられた突起を導体層に所定の深さ
だけ押し込むように半導体チップと接着部材を金型内に
設置し、樹脂封止するので、簡単な製造工程で半導体装
置の小型化、実装密度の向上を図ることができると共
に、導体層上の封止樹脂ばりが発生して導体層と外部電
極との導電性を損なうことが防止されるという効果があ
る。According to the twenty-first aspect, a step of attaching an adhesive member having a conductor layer on a semiconductor chip, a step of forming an electrode on the semiconductor chip, and electrically connecting the electrode and the conductor layer are performed. Connecting, resin sealing the semiconductor chip, the conductor layer, and the adhesive member; forming an opening reaching the conductor layer in the sealing resin; filling the opening with solder to form an external electrode; Forming the semiconductor chip and the adhesive member in the mold so that the protrusion provided on the mold when the opening is sealed with a resin is pushed into the conductor layer by a predetermined depth. Since it is possible to reduce the size of the semiconductor device and improve the packaging density with a simple manufacturing process, the sealing resin burrs on the conductor layer are generated and the conductivity between the conductor layer and the external electrodes is impaired. This has the effect of preventing

【０１２６】請求項２２の発明によれば、請求項２１の
発明において、半導体チップと接着部材を金型内に設置
する位置を保持するのに、接着部材の架橋部を金型で挟
むようにしたので、製造が容易となり、生産効率を向上
できるという効果がある。[0126] According to the present invention 22, in the invention of claim 21, the semiconductor chip and the adhesive member to hold the position to be installed in the mold, the bridge portion of the adhesive member so as to sandwich the mold Therefore, there is an effect that the production becomes easy and the production efficiency can be improved.

【０１２７】請求項２３の発明によれば、請求項２１ま
たは２２の発明において、開口部に半田ボールを乗せ、
リフローにより外部電極を形成するので、請求項２１ま
たは２２の発明の効果に加えて、製造工程の簡略化を図
ることができるという効果がある。[0127] According to the present invention 23, in the invention of claim 21 or <br/> other 22, placing the solder ball into the opening,
Since the external electrodes are formed by reflow, there is an effect that the manufacturing process can be simplified in addition to the effects of the invention according to claim 21 or 22 .

【０１２８】請求項２４の発明によれば、半導体チップ
上に導体層を有する接着部材を貼着する工程と、半導体
チップ上に電極を形成する工程と、電極と導体層とを電
気的に接続する工程と、導体層上にワイヤボンディング
法により金属突起を形成する工程と、半導体チップ、導
体層、接着部材および金属突起を樹脂封止しかつ金属突
起を一部外部に露出させる工程と、外部に露出した金属
突起と接続される外部電極を形成する工程とを含むの
で、簡単な製造工程で半導体装置の小型化を図ることが
できるという効果がある。According to the twenty-fourth aspect , a step of attaching an adhesive member having a conductor layer on a semiconductor chip, a step of forming an electrode on the semiconductor chip, and electrically connecting the electrode and the conductor layer Forming a metal protrusion on the conductor layer by a wire bonding method; sealing the semiconductor chip, the conductor layer, the adhesive member and the metal protrusion with a resin, and partially exposing the metal protrusion to the outside; Forming the external electrodes connected to the metal projections exposed to the semiconductor device, so that the size of the semiconductor device can be reduced by a simple manufacturing process.

【０１２９】請求項２５の発明によれば、請求項２４の
発明において、金属突起を一部外部に露出させる工程に
おいて、金属突起の高さを、該金属突起の切り残し量を
調整し、該調整された金属突起を樹脂封止の際に樹脂封
止金型に押し付けるように樹脂封止して金属突起の一部
を露出させるので、請求項２４の発明の効果に加えて、
さらに、製造工程が簡略化されるという効果がある。According to the twenty-fifth aspect, in the invention of the twenty-fourth aspect , in the step of partially exposing the metal projection, the height of the metal projection is adjusted by adjusting the uncut amount of the metal projection. Since the adjusted metal protrusions are resin-sealed so as to be pressed against a resin-sealing mold during resin-sealing and a part of the metal protrusions are exposed, in addition to the effects of the invention of claim 24 ,
Further, there is an effect that the manufacturing process is simplified.

【０１３０】請求項２６の発明によれば、半導体チップ
と離隔して導電性の基本部材を配置する工程と、基本部
材上に導体層を有する接着部材を貼着する工程と、半導
体チップに第１および第２の電極を形成する工程と、第
１および第２の電極とと導体層および基本部材とをそれ
ぞれ電気的に接続する工程と、半導体チップ、基本部
材、導体層および接着部材を樹脂封止しかつ少なくとも
上記基本部材と上記導体層の一側を外部に露出させる工
程とを含むので、簡単な製造工程で信頼性の高い半導体
装置を得ることができるという効果がある。According to the twenty-sixth aspect of the present invention, a step of disposing a conductive basic member at a distance from the semiconductor chip, a step of attaching an adhesive member having a conductor layer on the basic member, Forming the first and second electrodes, electrically connecting the first and second electrodes to the conductive layer and the basic member, respectively, Since the method includes a step of sealing and exposing at least one side of the basic member and the conductor layer to the outside, there is an effect that a highly reliable semiconductor device can be obtained by a simple manufacturing process.

【０１３１】請求項２７の発明によれば、半導体チップ
と離隔して導電性の基本部材を配置する工程と、半導体
チップと離隔しかつ基本部材の周囲に導電性の環状部材
を配置する工程と、基本部材上に導体層を有する接着部
材を貼着する工程と、半導体チップに第１、第２および
第３の電極を形成する工程と、第１、第２および第３の
電極と導体層、基本部材および環状部材とをそれぞれ電
気的に接続する工程と、半導体チップ、基本部材、環状
部材、導体層および接着部材を樹脂封止しかつ少なくと
も上記基本部材、環状部材および上記導体層の一側を外
部に露出させる工程とを含むので、簡単な製造工程で電
気特性の優れた半導体装置を得ることができるという効
果がある。According to the twenty-seventh aspect , a step of arranging a conductive basic member at a distance from the semiconductor chip and a step of arranging a conductive annular member at a distance from the semiconductor chip and around the basic member. Bonding an adhesive member having a conductor layer on a basic member, forming first, second, and third electrodes on a semiconductor chip; and attaching the first, second, and third electrodes to the conductor layer. Electrically connecting the basic member and the annular member to each other; sealing the semiconductor chip, the basic member, the annular member, the conductor layer and the adhesive member with a resin, and forming at least one of the basic member, the annular member and the conductor layer. And a step of exposing the side to the outside, so that a semiconductor device having excellent electrical characteristics can be obtained by a simple manufacturing process.

【０１３２】請求項２８の発明によれば、請求項６、８
または９記載の半導体装置を基板に対して垂直に配置
し、半導体装置内の半導体チップの一側に貼着された接
着部材上の導体層を基板の配線と電気的に接続するよう
にしたので、実装密度の向上を図ることができるという
効果がある。According to the twenty-eighth aspect , the sixth and eighth aspects are described.
Alternatively, the semiconductor device described in 9 is vertically arranged with respect to the substrate, and the conductor layer on the adhesive member attached to one side of the semiconductor chip in the semiconductor device is electrically connected to the wiring of the substrate. This has the effect that the mounting density can be improved.

【０１３３】請求項２９の発明によれば、請求項１５記
載の半導体装置の樹脂封止部分に設けられた溝部の内、
基本部材を曲げるために設けられていない溝部に、隣接
する他の半導体装置の支持部材を潜り込ませて実装する
ようにしたので、高密度実装が可能になるという効果が
ある。According to the twenty- ninth aspect of the present invention, the semiconductor device according to the fifteenth aspect has the following features:
Since the supporting member of another adjacent semiconductor device is sunk into the groove not provided for bending the basic member and mounted, there is an effect that high-density mounting becomes possible.

【０１３４】請求項３０の発明によれば、半導体装置の
半導体チップ表面側の樹脂表面に薄膜状の配線部材の貼
着された接着部材を露出させるように樹脂封止し、接着
部材上の配線部材と半導体装置の樹脂表面との段差を所
定値に抑え、接着部材上の配線部材を基板に対向するよ
うに実装し、接着部材上の配線部材を基板の配線と電気
的に接続するようにしたので、高密度実装が可能になる
という効果がある。According to the thirtieth aspect of the present invention, the semiconductor device is sealed with resin so that the adhesive member having the thin-film wiring member attached to the resin surface on the semiconductor chip surface side of the semiconductor device is exposed. The step between the member and the resin surface of the semiconductor device is suppressed to a predetermined value, the wiring member on the adhesive member is mounted so as to face the substrate, and the wiring member on the adhesive member is electrically connected to the wiring on the substrate. Therefore, there is an effect that high-density mounting becomes possible.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 この発明に係る半導体装置の第１実施例の一
部断面を示す外観図である。FIG. 1 is an external view showing a partial cross section of a first embodiment of a semiconductor device according to the present invention.

【図２】 図１の線ａ−ａ′の部分で切断して示す断面
図である。FIG. 2 is a cross-sectional view taken along a line aa 'of FIG.

【図３】 この発明に係る半導体装置の第１実施例の製
造段階における半田バンプ作成前の断面図である。FIG. 3 is a sectional view of a semiconductor device according to a first embodiment of the present invention before a solder bump is formed in a manufacturing stage.

【図４】 この発明に係る半導体装置の第１実施例の製
造工程を説明するための一部断面を示す外観図である。FIG. 4 is an external view showing a partial cross section for describing a manufacturing process of the first embodiment of the semiconductor device according to the present invention.

【図５】 この発明に係る半導体装置の第２実施例の一
部断面を示す外観図である。FIG. 5 is an external view showing a partial cross section of a second embodiment of the semiconductor device according to the present invention.

【図６】 図５の線ｋ−ｋ′の部分で切断して示す断面
図である。FIG. 6 is a cross-sectional view cut along a line kk ′ of FIG. 5;

【図７】 この発明に係る半導体装置の第２実施例の製
造段階における樹脂封止前の状態を示す断面図である。FIG. 7 is a sectional view showing a state before resin sealing in a manufacturing stage of a second embodiment of the semiconductor device according to the present invention.

【図８】 この発明に係る半導体装置の第２実施例の製
造工程を説明するための一部断面図である。FIG. 8 is a partial cross-sectional view for explaining a manufacturing step of the second embodiment of the semiconductor device according to the present invention.

【図９】 この発明に係る半導体装置の第３実施例の一
部を示す外観図である。FIG. 9 is an external view showing a part of a third embodiment of the semiconductor device according to the present invention.

【図１０】 この発明に係る半導体装置の第３実施例の
一部断面を示す外観図である。FIG. 10 is an external view showing a partial cross section of a third embodiment of the semiconductor device according to the present invention.

【図１１】 この発明に係る半導体装置の第３実施例の
実装時の一部を示す外観図である。FIG. 11 is an external view showing a part of a semiconductor device according to a third embodiment of the present invention when it is mounted.

【図１２】 図１１の線ｂ−ｂ′の部分で切断して示す
断面図である。FIG. 12 is a cross-sectional view cut along a line bb ′ of FIG. 11;

【図１３】 この発明に係る半導体装置の第４実施例の
一部を示す外観図である。FIG. 13 is an external view showing a part of a fourth embodiment of the semiconductor device according to the present invention.

【図１４】 この発明に係る半導体装置の第４実施例の
一部断面を示す外観図である。FIG. 14 is an external view showing a partial cross section of a fourth embodiment of the semiconductor device according to the present invention.

【図１５】 この発明に係る半導体装置の第４実施例の
実装時の一部を示す外観図である。FIG. 15 is an external view showing a part of a semiconductor device according to a fourth embodiment of the present invention when it is mounted.

【図１６】 図１５の線ｃ−ｃ′の部分で切断して示す
断面図である。16 is a cross-sectional view cut along a line cc 'in FIG.

【図１７】 この発明に係る半導体装置の第４実施例の
実装時の状態を示す平面図である。FIG. 17 is a plan view showing a state when a semiconductor device according to a fourth embodiment of the present invention is mounted.

【図１８】 この発明の第４実施例の半導体装置を複数
個実装した状態を示す平面図である。FIG. 18 is a plan view showing a state where a plurality of semiconductor devices according to a fourth embodiment of the present invention are mounted.

【図１９】 この発明の第４実施例の半導体装置を複数
個実装した状態を示す平面図である。FIG. 19 is a plan view showing a state in which a plurality of semiconductor devices according to a fourth embodiment of the present invention are mounted.

【図２０】 この発明に係る半導体装置の第５実施例の
製造段階におけるリード加工工程前の一部断面を示す外
観図である。FIG. 20 is an external view showing a partial cross section before a lead processing step in a manufacturing stage of a fifth embodiment of the semiconductor device according to the present invention.

【図２１】 この発明に係る半導体装置の第５実施例の
実装時の一部を示す外観図である。FIG. 21 is an external view showing a part of a semiconductor device according to a fifth embodiment of the present invention when it is mounted.

【図２２】 図２１の矢印ｄの方向から見た側面図であ
る。FIG. 22 is a side view as seen from the direction of arrow d in FIG. 21.

【図２３】 この発明に係る半導体装置の第５実施例の
ベースリード、テープ、リングリード等の構成要素の一
部を示す外観図である。FIG. 23 is an external view showing a part of components such as a base lead, a tape, and a ring lead of a fifth embodiment of the semiconductor device according to the present invention.

【図２４】 この発明に係る半導体装置の第６実施例の
一部断面を示す外観図である。FIG. 24 is an external view showing a partial cross section of a sixth embodiment of the semiconductor device according to the present invention.

【図２５】 図２４の線ｅ−ｅ′の部分で切断して示す
断面図である。FIG. 25 is a sectional view taken along a line ee ′ in FIG. 24;

【図２６】この発明に係る半導体装置の第７実施例の一
部断面を示す外観図である。FIG. 26 is an external view showing a partial cross section of a seventh embodiment of the semiconductor device according to the present invention.

【図２７】 図２６の線ｆ−ｆ′の部分で切断して示す
断面図である。FIG. 27 is a cross-sectional view taken along a line ff ′ of FIG. 26;

【図２８】 従来の半導体装置の一部断面を示す外観図
である。FIG. 28 is an external view showing a partial cross section of a conventional semiconductor device.

【図２９】 図２８の線ｇ−ｇ′の部分で切断して示す
断面図である。FIG. 29 is a cross-sectional view cut along a line gg ′ in FIG. 28;

【図３０】 従来の半導体装置のＺＩＰを示す外観図で
ある。FIG. 30 is an external view showing a ZIP of a conventional semiconductor device.

【図３１】 従来の半導体装置のＺＩＰを示す側面図で
ある。FIG. 31 is a side view showing a ZIP of a conventional semiconductor device.

【図３２】 従来の半導体装置のＳＶＰを示す外観図で
ある。FIG. 32 is an external view showing an SVP of a conventional semiconductor device.

【図３３】 従来の半導体装置のＳＶＰをｈ方向から見
た側面図である。FIG. 33 is a side view of an SVP of a conventional semiconductor device viewed from a direction h.

【図３４】 図３２の線ｊ−ｊ′の部分で切断して示す
断面図である。FIG. 34 is a sectional view taken along line JJ ′ of FIG. 32;

【図３５】 従来の半導体装置を示す断面図である。FIG. 35 is a cross-sectional view showing a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１Ａ〜１Ｇ 半導体装置、２ 半導体チップ、３ ボン
ディングパッド、５半田バンプ、６ 封止樹脂、９ テ
ープ、１０ 導体層、１１ 金属細線、１２開口部、１
３，３０ 架橋部、１４ 金属突起、１５ 櫛形導体
層、１６ 凸部、１７ スタンドロック、１８ 基板、
１９，２７ 配線、２０ 半田、２２ベースリード、２
３ 溝部、２４ リングリード、２５ 櫛形部、２６
ＴＡＢテープ、２８ 内部リード、２９ 櫛形配線、３
２ 位置決め凹部、３３ スルーホール、３４ 逃げ凹
部。1A to 1G semiconductor device, 2 semiconductor chip, 3 bonding pad, 5 solder bump, 6 sealing resin, 9 tape, 10 conductor layer, 11 thin metal wire, 12 opening, 1
3, 30 bridging part, 14 metal protrusion, 15 comb-shaped conductor layer, 16 convex part, 17 stand lock, 18 substrate,
19, 27 wiring, 20 solder, 22 base lead, 2
3 groove, 24 ring lead, 25 comb, 26
TAB tape, 28 internal leads, 29 comb wiring, 3
2 positioning recess, 33 through hole, 34 escape recess.

Claims (30)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 半導体チップ上に設けられ、導体層を有
する接着部材と、 上記半導体チップ上に設けられた電極と上記導体層とを
電気的に接続する接続部材と、 上記導体層上に設けられた金属突起と、 上記半導体チップ、上記導体層、上記接着部材、上記接
続部材および上記金属突起を樹脂封止しかつ上記金属突
起を一部外部に露出させる封止部材と、 上記外部に露出した金属突起と接続された外部電極とを
備えたことを特徴とする半導体装置。1. An adhesive member provided on a semiconductor chip and having a conductor layer, a connection member electrically connecting an electrode provided on the semiconductor chip and the conductor layer, and provided on the conductor layer And a sealing member that seals the semiconductor chip, the conductor layer, the adhesive member, the connecting member, and the metal protrusion with resin and partially exposes the metal protrusion, and that is exposed to the outside. A semiconductor device comprising: a metal projection formed as described above; and an external electrode connected to the metal projection. 【請求項２】 上記接着部材は、上記半導体チップ上に
設けられた電極と接続される櫛形導体層を有する請求項
１記載の半導体装置。2. The semiconductor device according to claim 1, wherein said adhesive member has a comb-shaped conductor layer connected to an electrode provided on said semiconductor chip. 【請求項３】 上記金属突起が露出している封止部材の
部分の周囲に凹部を設け、該凹部に上記外部電極の一部
を食い込ませた請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein a recess is provided around a portion of the sealing member where the metal projection is exposed, and a part of the external electrode is made to bite into the recess. 【請求項４】 上記櫛形導体層は、電源供給または接地
電位用配線として使用される請求項２記載の半導体装
置。4. The semiconductor device according to claim 2, wherein said comb-shaped conductor layer is used as a power supply or ground potential wiring. 【請求項５】 半導体チップの一側に設けられた、導体
層を有する接着部材と、 上記半導体チップの上記一側以外の部分に設けられた電
極と上記導体層とを電気的に接続する接続部材と、 上記半導体チップ、上記導体層、上記接着部材および上
記接続部材を樹脂封止しかつ上記導体層の一側を、封止
樹脂の上記一側の端面の上部を上記半導体チップの他側
方向に後退させることにより外部に露出させる封止部材
とを備えたことを特徴とする半導体装置。5. An adhesive member having a conductor layer provided on one side of a semiconductor chip, and a connection for electrically connecting an electrode provided on a portion other than the one side of the semiconductor chip and the conductor layer. The member, the semiconductor chip, the conductor layer, the adhesive member, and the connection member are resin-sealed, and one side of the conductor layer is placed on an end surface of the one side of the sealing resin and the other side of the semiconductor chip. A sealing member that is exposed to the outside by being retracted in a direction. 【請求項６】 上記封止部材上に上記半導体チップの能
動面と垂直な方向に突出して設けられた支持部材を備え
た請求項５記載の半導体装置。6. The semiconductor device according to claim 5, further comprising a support member provided on said sealing member so as to protrude in a direction perpendicular to an active surface of said semiconductor chip. 【請求項７】 半導体チップと離隔して設けられた導電
性の基本部材と、 この基本部材上に設けられ、導体層を有する接着部材
と、 上記半導体チップに設けられた第１および第２の電極と
上記導体層および上記基本部材とをそれぞれ電気的に接
続する接続部材と、 上記半導体チップ、上記基本部材、上記導体層、上記接
着部材および上記接続部材を樹脂封止しかつ少なくとも
上記基本部材と上記導体層の一側を外部に露出させる封
止部材とを備えたことを特徴とする半導体装置。7. A conductive basic member provided apart from the semiconductor chip, an adhesive member provided on the basic member and having a conductor layer, and a first and a second member provided on the semiconductor chip. A connection member for electrically connecting the electrode, the conductor layer, and the basic member, respectively; and a resin sealing of the semiconductor chip, the basic member, the conductor layer, the adhesive member, and the connection member, and at least the basic member. And a sealing member for exposing one side of the conductor layer to the outside. 【請求項８】 半導体チップと離隔して設けられた導電
性の基本部材と、 上記半導体チップと離隔しかつ上記基本部材の周囲に設
けられた導電性の環状部材と、 上記基本部材上に設けられ、導体層を有する接着部材
と、 上記半導体チップに設けられた第１、第２および第３の
電極と上記導体層、上記基本部材および上記環状部材と
をそれぞれ電気的に接続する接続部材と、 上記半導体チップ、上記基本部材、上記環状部材、上記
導体層、上記接着部材および上記接続部材を樹脂封止し
かつ少なくとも上記基本部材、上記環状部材および上記
導体層の一側を外部に露出させる封止部材とを備えたこ
とを特徴とする半導体装置。8. A conductive basic member provided separately from the semiconductor chip, a conductive annular member provided apart from the semiconductor chip and provided around the basic member, and provided on the basic member. An adhesive member having a conductor layer; and a connection member for electrically connecting the first, second, and third electrodes provided on the semiconductor chip to the conductor layer, the basic member, and the annular member, respectively. The semiconductor chip, the basic member, the annular member, the conductor layer, the adhesive member and the connection member are resin-sealed, and at least one side of the basic member, the annular member and the conductor layer is exposed to the outside. A semiconductor device comprising a sealing member. 【請求項９】 上記封止部材より露出した上記基本部材
は支持用として使用される請求項７または８記載の半導
体装置。9. The semiconductor device according to claim 7, wherein the basic member exposed from the sealing member is used for support. 【請求項１０】 上記導体層は上記封止部材より0.2〜
1.0mm程度露出される請求項７〜９のいずれかに記載の
半導体装置。10. The conductive layer may be 0.2 to 0.2% smaller than the sealing member.
10. The semiconductor device according to claim 7, which is exposed by about 1.0 mm. 【請求項１１】 上記封止部材より露出した上記導体層
は実装時基板上の配線と接続する際のヒンジとして使用
される請求項７〜１０のいずれかに記載の半導体装置。11. The semiconductor device according to claim 7, wherein said conductor layer exposed from said sealing member is used as a hinge when connecting to a wiring on a board at the time of mounting. 【請求項１２】 上記基本部材は接地電位用として使用
される請求項７〜１１のいずれかに記載の半導体装置。12. The semiconductor device according to claim 7, wherein said basic member is used for ground potential. 【請求項１３】 上記基本部材は上記電極側の表面を露
出され、該露出部がワイヤボンディング可能とされてい
る請求項７〜１２のいずれかに記載の半導体装置。13. The semiconductor device according to claim 7, wherein the surface of the basic member on the electrode side is exposed, and the exposed portion is capable of being wire-bonded. 【請求項１４】 上記封止部材の上記基本部材が露出し
ている部分に溝部を設けた請求項７〜１３のいずれかに
記載の半導体装置。14. The semiconductor device according to claim 7, wherein a groove is provided in a portion of the sealing member where the basic member is exposed. 【請求項１５】 上記基本部材と上記環状部材は上記電
極を挟んで相互に対向した位置に配置される請求項８〜
１４のいずれかに記載の半導体装置。15. The basic member and the annular member are arranged at positions facing each other with the electrode interposed therebetween.
15. The semiconductor device according to any one of 14. 【請求項１６】 上記基本部材と上記環状部材は、電源
供給または接地電位用配線として使用される請求項８〜
１５のいずれかに記載の半導体装置。16. The power supply or ground potential wiring according to claim 8, wherein said basic member and said annular member are used.
16. The semiconductor device according to any one of 15. 【請求項１７】 上記基本部材の一側は、上記接着部材
および上記導体層に対向する部分以外は削除されて櫛形
をなす請求項７〜１６のいずれかに記載の半導体装置。17. The semiconductor device according to claim 7, wherein one side of the basic member is comb-shaped by removing portions other than a portion facing the adhesive member and the conductor layer. 【請求項１８】 半導体チップ上に設けられた接着部材
と、 この接着部材より延在して上記半導体チップ上に設けら
れた電極と電気的に接続される薄膜状の配線部材と、 上記半導体チップ、上記接着部材および上記配線部材を
樹脂封止しかつ上記配線部材の一側を所定の段差を持っ
て外部に露出させる封止部材とを備えたことを特徴とす
る半導体装置。18. An adhesive member provided on a semiconductor chip, a thin-film wiring member extending from the adhesive member and electrically connected to an electrode provided on the semiconductor chip, and the semiconductor chip And a sealing member for sealing the adhesive member and the wiring member with a resin and exposing one side of the wiring member to the outside with a predetermined level difference. 【請求項１９】 上記封止部材は実装時基板と対接する
部分に該基板の配線と嵌合する位置決め凹部を有する請
求項１８記載の半導体装置。19. The semiconductor device according to claim 18 , wherein said sealing member has a positioning concave portion at a portion which is in contact with the substrate at the time of mounting, and which is fitted with a wiring of said substrate. 【請求項２０】 上記封止部材は実装時基板と対接する
部分に基板上のスルーホール等との干渉を防ぐための逃
げ凹部を有する請求項１８または１９記載の半導体装
置。20. The semiconductor device according to claim 18 , wherein said sealing member has an escape recess at a portion which is in contact with the board at the time of mounting to prevent interference with a through hole or the like on the board. 【請求項２１】 半導体チップ上に導体層を有する接着
部材を貼着す工程と、 上記半導体チップ上に電極を形成する工程と、 上記電極と上記導体層とを電気的に接続する工程と、 上記半導体チップ、上記導体層、上記接着部材を樹脂封
止する工程と、 この封止樹脂に上記導体層に達する開口部を形成する工
程と、 上記開口部に半田を充填して外部電極を形成する工程と
を含み、上記開口部を樹脂封止する際の金型に設けられ
た突起を上記導体層に所定の深さだけ押し込むように上
記半導体チップと上記接着部材を上記金型内に設置し、
樹脂封止することを特徴とする半導体装置の製造方法。21. A step of attaching an adhesive member having a conductor layer on a semiconductor chip; a step of forming an electrode on the semiconductor chip; and a step of electrically connecting the electrode and the conductor layer; A step of resin sealing the semiconductor chip, the conductor layer, and the adhesive member; a step of forming an opening reaching the conductor layer in the sealing resin; and filling the opening with solder to form an external electrode. And mounting the semiconductor chip and the adhesive member in the mold so that the protrusion provided on the mold for sealing the opening with resin is pressed into the conductor layer by a predetermined depth. And
A method for manufacturing a semiconductor device, which comprises resin sealing. 【請求項２２】 上記半導体チップと上記接着部材を上
記金型内に設置する位置を保持するのに、上記接着部材
の架橋部を上記金型で挟むようにした請求項２１記載の
半導体装置の製造方法。22. The semiconductor device according to claim 21 , wherein a bridge portion of said adhesive member is sandwiched by said mold to hold a position where said semiconductor chip and said adhesive member are set in said mold. Production method. 【請求項２３】 上記開口部に半田ボールを乗せ、リフ
ローにより上記外部電極を形成する請求項２１または２
２記載の半導体装置の製造方法。23. Place the solder balls to the opening, according to claim 21 or 2 to form the external electrodes by reflow
3. The method for manufacturing a semiconductor device according to item 2 . 【請求項２４】 半導体チップ上に導体層を有する接着
部材を貼着する工程と、 上記半導体チップ上に電極を形成する工程と、 上記電極と上記導体層とを電気的に接続する工程と、 上記導体層上にワイヤボンディング法により金属突起を
形成する工程と、 上記半導体チップ、上記導体層、上記接着部材および上
記金属突起を樹脂封止しかつ上記金属突起を一部外部に
露出させる工程と、 上記外部に露出した金属突起と接続される外部電極を形
成する工程とを含むことを特徴とする半導体装置の製造
方法。24. A step of attaching an adhesive member having a conductor layer on a semiconductor chip, a step of forming an electrode on the semiconductor chip, and a step of electrically connecting the electrode and the conductor layer. Forming a metal projection on the conductor layer by a wire bonding method; and sealing the semiconductor chip, the conductor layer, the adhesive member and the metal projection with a resin, and partially exposing the metal projection to the outside. Forming an external electrode connected to the metal projection exposed to the outside. 【請求項２５】 上記金属突起を一部外部に露出させる
工程において、上記金属突起の高さを、該金属突起の切
り残し量を調整し、該調整された金属突起を樹脂封止の
際に樹脂封止金型に押し付けるように樹脂封止して上記
金属突起の一部を露出させる請求項２４記載の半導体装
置の製造方法。25. In the step of partially exposing the metal projection to the outside, the height of the metal projection is adjusted by adjusting the uncut amount of the metal projection, and the adjusted metal projection is sealed with a resin. 25. The method of manufacturing a semiconductor device according to claim 24 , wherein a portion of the metal protrusion is exposed by resin sealing so as to be pressed against a resin sealing mold. 【請求項２６】 半導体チップと離隔して導電性の基本
部材を配置する工程と、 上記基本部材上に導体層を有する接着部材を貼着する工
程と、 上記半導体チップに第１および第２の電極を形成する工
程と、 上記第１および第２の電極とと上記導体層および上記基
本部材とをそれぞれ電気的に接続する工程と、 上記半導体チップ、上記基本部材、上記導体層および上
記接着部材を樹脂封止しかつ少なくとも上記基本部材と
上記導体層の一側を外部に露出させる工程とを含むこと
を特徴とする半導体装置の製造方法。26. A step of disposing a conductive basic member at a distance from a semiconductor chip; a step of attaching an adhesive member having a conductor layer on the basic member; A step of forming electrodes; a step of electrically connecting the first and second electrodes to the conductor layer and the basic member, respectively; and the semiconductor chip, the basic member, the conductor layer, and the adhesive member. A resin device, and exposing at least one side of the basic member and the conductor layer to the outside. 【請求項２７】 半導体チップと離隔して導電性の基本
部材を配置する工程と、 上記半導体チップと離隔しかつ上記基本部材の周囲に導
電性の環状部材を配置する工程と、 上記基本部材上に導体層を有する接着部材を貼着する工
程と、 上記半導体チップに第１、第２および第３の電極を形成
する工程と、 上記第１、第２および第３の電極と上記導体層、上記基
本部材および上記環状部材とをそれぞれ電気的に接続す
る工程と、 上記半導体チップ、上記基本部材、上記環状部材、上記
導体層および上記接着部材を樹脂封止しかつ少なくとも
上記基本部材、上記環状部材および上記導体層の一側を
外部に露出させる工程とを含むことを特徴とする半導体
装置の製造方法。27. A step of arranging a conductive basic member at a distance from the semiconductor chip; a step of arranging a conductive ring member at a distance from the semiconductor chip and around the basic member; Adhering an adhesive member having a conductor layer to the semiconductor chip, forming first, second, and third electrodes on the semiconductor chip; the first, second, and third electrodes and the conductor layer; A step of electrically connecting the basic member and the annular member respectively; and a step of resin-sealing the semiconductor chip, the basic member, the annular member, the conductor layer and the adhesive member, and at least the basic member and the annular member. Exposing one side of the member and the conductor layer to the outside. 【請求項２８】 請求項３、６、８または９のいずれか
に記載の半導体装置を基板に対して垂直に配置し、 上記半導体装置内の半導体チップの一側に貼着された接
着部材上の導体層を上記基板の配線と電気的に接続する
ようにしたことを特徴とする半導体装置の実装方法。28. The semiconductor device according to claim 3, 6, 8 or 9 , wherein the semiconductor device is arranged perpendicular to a substrate, and on a bonding member attached to one side of a semiconductor chip in the semiconductor device. Wherein the conductive layer is electrically connected to the wiring of the substrate. 【請求項２９】 請求項１５記載の半導体装置の樹脂封
止部分に設けられた溝部の内、基本部材を曲げるために
設けられていない溝部に、隣接する他の半導体装置の支
持部材を潜り込ませて実装するようにしたことを特徴と
する半導体装置の実装方法。29. A support member of another adjacent semiconductor device is sunk into a groove not provided for bending a basic member, among grooves provided in a resin sealing portion of the semiconductor device according to claim 15. A method of mounting a semiconductor device, characterized in that the semiconductor device is mounted by mounting. 【請求項３０】 半導体装置の半導体チップ表面側の樹
脂表面に薄膜状の配線部材の貼着された接着部材を露出
させるように樹脂封止し、上記接着部材上の配線部材と
半導体装置の樹脂表面との段差を所定値に抑え、上記接
着部材上の配線部材を基板に対向するように実装し、上
記接着部材上の配線部材を上記基板の配線と電気的に接
続するようにしたことを特徴とする半導体装置の実装方
法。30. A semiconductor device, which is resin-sealed so as to expose an adhesive member having a thin film-shaped wiring member adhered to a resin surface on a semiconductor chip surface side of a semiconductor device. The step with the surface is suppressed to a predetermined value, the wiring member on the adhesive member is mounted so as to face the substrate, and the wiring member on the adhesive member is electrically connected to the wiring on the substrate. A method for mounting a semiconductor device.
JP17102094A 1994-07-22 1994-07-22 Semiconductor device, its manufacturing method and mounting method Expired - Fee Related JP3150253B2 (en)

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DE19526511A DE19526511A1 (en) 1994-07-22 1995-07-20 PCB mounting applications of an encapsulated semiconductor package
KR1019950022303A KR100201168B1 (en) 1994-07-22 1995-07-22 Semiconductor device, manufacture thereof and its mounting method

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JPH0837253A (en) 1996-02-06

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