JP3017223B2 - Microcomputer communication method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer communication method, and more particularly, to a communication method for transmitting and receiving data between microcomputers at synchronous timing by a clock pulse.

[Prior Art] Conventionally, as a data communication method, JP-A-63-250759 discloses a method of performing data communication at a timing based on a clock pulse (Example 1). That is, a data signal is transmitted and received at regular intervals by a clock pulse. At this time, the start of data transmission is determined using the chip select signal. That is, the chip select signal is used as the start signal.

Alternatively, a start bit and a stop bit are used before and after the communication data (Example 2).

[Problems to be Solved by the Invention] However, if the method of Example 1 is adopted for microcomputer communication, there is no chip select signal in communication between microcomputers, a start signal is required separately, and a port for that needs to be prepared. Was. Further, when the method of Example 2 is adopted, it is necessary to transmit and receive data (for example, 10 bits) longer than actual communication data (for example, 8 bits), and there is a disadvantage that the communication speed is reduced.

An object of the present invention is to provide a microcomputer communication method capable of easily and quickly performing data communication between microcomputers without using a start signal transmission port.

Means for Solving the Problems According to the present invention, a receiving microcomputer detects a start of transmission of a plurality of bits of data by a start pulse from a transmitting microcomputer, and performs synchronization using an edge of a clock pulse train from the transmitting microcomputer. In the microcomputer communication method for performing data communication between microcomputers at a timing, in the clock pulse train, a pulse having an edge interval shorter than the edge interval of the clock pulse train is created by using an edge at which the transmitting microcomputer transmits the first bit data. The gist of the present invention is a microcomputer communication method using the pulse as the start pulse.

[Operation] In the clock pulse train transmitted from the sending microcomputer to the receiving microcomputer, a pulse having an edge interval shorter than the edge interval of the clock pulse train is created using the edge at which the transmitting microcomputer transmits the first bit data, The pulse is transmitted to the receiving microcomputer as a start pulse. The receiving microcomputer detects the start of data transmission of a plurality of bits based on the start pulse.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

 FIG. 1 shows two microcomputers 1 and 2 for performing communication.

The main microcomputer 1 includes a central processing unit (hereinafter referred to as a CP).
U), a free-run timer 4, a ROM 7, a RAM 8, and an input / output port 9. The CPU 3 executes various operations according to a control program stored in the ROM 7. The free-run timer 4 generates a periodic interrupt signal every predetermined time tb and outputs it to the CPU 3. RAM 8 is used for temporary storage of data, etc.
The RAM 8 includes a transmission / reception storage area 8a and a transmission / reception buffer area 8b. The RAM 8 is provided with a communication counter C1, and the counter C1 counts the number of interrupt processes. Further, the microcomputer 1 is operated by an oscillator 10.

The sub microcomputer 2 has a central processing unit (hereinafter referred to as a CPU).
11, free-run timer 12, ROM 13, RAM 14, input / output port 15, interrupt generator 16, rising time latch circuit 17,
A falling time latch circuit 18 is provided. The CPU 11 executes various processes according to a control program stored in the ROM 13.
The RAM 14 is used for temporary storage of data and the like. The RAM 14 includes a transmission / reception storage area 14a and a transmission / reception buffer area 14b. The RAM 14 has a communication counter C2.
Is prepared, and the number of interrupt processes is counted by the counter C2.

Data signal lines 20 and 21 are provided between the input / output port 9 of the microcomputer 1 and the input / output port 15 of the microcomputer 2. A communication timing reference cook signal line (hereinafter referred to as a clock signal line) 22 is provided between the input / output port 9 of the microcomputer 1 and the interrupt generator 16 of the microcomputer 2. Reference numeral 22 is connected to the rise / fall time latch circuits 17 and 18 in the microcomputer 2.
Further, the microcomputer 2 is operated by an external oscillator 19.

In the microcomputer 1, the free-run timer 4
As a result, an interrupt is generated in the CPU 3 at regular time intervals tb, and the clock pulse level via the clock signal line 22 is inverted and transmitted to the microcomputer 2 at regular time intervals tb. At the same time, the microcomputer 1 transmits and receives data signals via the data signal lines 20 and 21. At the time of data transmission / reception, a start pulse is combined with a clock signal serving as a transmission / reception reference to notify the start of data transmission / reception.

The interrupt generator 16 of the microcomputer 2 captures a change in the clock pulse from the microcomputer 1 input through the clock signal line 22, and outputs an interrupt signal to the CPU 11 in synchronization with its rising and falling edges. The rising time latch circuit 17 captures a change in the clock pulse from the microcomputer 1 input through the clock signal line 22, reads the time when the rising edge is input from the free-run timer 12, latches the time, and outputs the time to the CPU 11. . Fall time latch circuit 18
Reads and latches the time at which the falling edge of the clock pulse was input from the free-run timer 12, and
Output to CPU11.

Next, a communication method of the microcomputers 1 and 2 configured as described above will be described with reference to a time chart shown in FIG.
The data length for communication is 8 bits.

In FIG. 3 showing the processing of the microcomputer 1, in step 100, the CPU 3 sets the value of the counter C1 to a value of "8" or more, for example, 16
A two-digit number "FF" of a base number is set, and in step 101, the signal output of the clock pulse is set to the "H" state. Thereafter, the CPU 3 executes a main routine process in step 102.

In the low interrupt processing routine for each tb time of the microcomputer 1 shown in FIG.
To receive data from. The CPU 3 initially reads the transmission data from the transmission / reception storage area 8a to the microcomputer 2 in step 203 after step 201 and step 202 because the value of the counter C1 is "8" or more in step 100, and the transmission / reception buffer area 8b Update the stored contents of. CP
U3 sets the value of the counter C1 to a 2-digit hexadecimal number "FF" in step 204, and increments the value of the counter C1 by "1" in step 205 to set the count value to "0".

The CPU 3 transmits data to the microcomputer 2 in step 206, and inverts the signal output of the clock pulse in step 207 ("H" → "L" at time t1 in FIG. 2). At step 208, the CPU 3 determines whether or not the value of the counter C1 is "0". At this time, since the value is "0", the clock pulse at step 210 is inverted after a predetermined time ta has elapsed to transmit a start pulse at step 209 ( In FIG. 2, "L" at t2 →
"H"). The predetermined time ta may be set so that ta≪tb, and may be counted by the number of execution steps of the program, or may be counted by a timer circuit (not shown). The CPU 3 permits the interrupt in step 211 and ends the interrupt processing.

In the next routine processing of FIG. 4, the value of the counter C1 is "0", so that the CPU 3 determines in step 201 that the value of the counter C1 is "6" or less.
Increments the value of counter C1 by "1"
Data is transmitted to the microcomputer 2 at 206, and the signal output of the clock pulse is inverted at step 207 ("H" → "L" at time t3 in FIG. 2). CPU3 is counter C at step 208
It is determined whether or not the value of 1 is "0". At this time, since it is "1", the interrupt is permitted in step 211 and the interrupt processing is terminated.

Hereinafter, the same processing is performed (in FIG. 2, the times tt4 to t9).
In the display). In step 200, the received data is stored in RAM8
Is stored in the transmission / reception buffer area 8b of step 206.
In the transmission processing in, the transmission data is output as the transmission data stored in the transmission / reception buffer area 8b of the RAM 8.

At the interrupt timing of t10 in FIG. 2, the CPU 3 determines that the 8-bit data has been normally received only when the value of the counter C1 is "7". Rewrite the data from the transmission / reception buffer area 8b of the RAM 8 to the transmission / reception storage area 8a, and
At 203, the new transmission data to the microcomputer 2 is read from the transmission / reception storage area 8a, and the storage contents of the transmission / reception buffer area 8b are updated. Then, in step 204, the CPU 3 sets the value of the counter C1 to a 2-digit hexadecimal number “FF”. or,
When the value of the counter C1 is "8" or more, the CPU 3 determines that communication has not been normally performed due to disturbance or the like, and prohibits rewriting of reception data from the microcomputer 2 to the transmission / reception storage area 8a of the RAM 8.

On the other hand, in FIG.
In step 300, the value of the counter C2 is set to a value of "8" or more, for example, a 2-digit hexadecimal number "80" in step 300, and step 301
Sets the falling edge of the clock pulse as the interrupt timing. Thereafter, the CPU 11 executes a main routine process in step 302.

The interrupt generator 16 of the microcomputer 2 receives the clock pulse from the microcomputer 1 and outputs an interrupt signal to the CPU 11 at the rising or falling edge of the signal. In the interrupt processing routine of the microcomputer 2 shown in FIG.
1 determines whether the interrupt edge of the clock pulse is rising or falling.

In FIG. 2, at time t1, the CPU 11 determines at step 401 that the interrupt edge has fallen, and waits for a time ta to determine whether or not it is a start pulse at step 400a. After the lapse of time ta (time t2 in FIG. 2), step 402
It is determined that the level of the clock pulse is "H".
Then, the CPU 11 determines in step 403 that the rising time latch circuit 17
And the time tp (= t2−t1) between the falling edge time and the time of the falling time latch circuit 18 which is the edge at the time of interruption. When the time difference tp obtained in step 404, that is, the time of the pulse width is shorter than a predetermined value, for example, (2/3) · ta, the CPU 11 determines that noise has been input and does not perform the communication processing, and proceeds to step 405. After interrupt permission is given by, the interrupt processing is terminated.

In other words, since the start pulse is transmitted but an interrupt may occur due to noise or the like, the pulse width after a predetermined time ta has elapsed from the interrupt edge of the clock pulse is measured to prevent a transmission error due to the noise. ing. That is, when the pulse width is larger than the predetermined value (2/3) · ta, it is determined that the pulse is the start pulse.

At this time, the communication counter C2
Is greater than or equal to “7”, the CPU 11 proceeds to step 406
To determine that the value of the counter C2 is other than "7", and
The new transmission data is read from the transmission / reception storage area 14a of the RAM 14 to update the transmission / reception buffer area 14b, and the value of the counter C2 is set to a hexadecimal two-digit number "FF" in step 408, and the counter C2 is set in step 409. Is incremented by "1" to set the count value to "0". After determining that the value of the counter C2 is less than “8” in step 410, the CPU 11 receives data from the microcomputer 1 in step 411, and transmits data to the microcomputer 1 in step 412. Thereafter, since the count value of the counter C2 is “0” in step 413, the CPU 11 gives an interrupt permission in step 405 in step 405, and ends the interrupt processing.

In FIG. 2, at time t3, the CPU 11 determines in step 401 that the interrupt edge of the clock pulse falls, and in step 402 (at t3 + ta) determines that the level of the clock pulse is "L". Proceed to. That is,
It is determined that the pulse is not a start pulse, and the value of the counter C2 is incremented by "1" in step 409, and steps 410 to 412
Is performed, the value of the counter C2 is not "0" at step 413, and therefore, the interrupt edge of the clock pulse is inverted and set at step 414 (at time t4, the interrupt is set at the rising edge. ). After that, CPU1
In step 1 405, the interrupt permission is given, and then the interrupt processing is terminated.

Hereinafter, similar processing is performed (indicated by t4 to t9 in FIG. 2). If the value of the counter C2 is "8" or more due to noise or the like at step 410, the value of the counter C2 is set to "8" at step 415 without receiving / transmitting data at steps 411 and 412.

In FIG. 2, at time t10, the CPU 11
Is determined to be an edge rising, and the process waits for a time ta in step 400b. After a lapse of time ta (time t11 in FIG. 2), it is determined in step 416 that the level of the clock pulse is "L". Then, in step 417, the CPU 11 obtains a difference tp (= t11−t10) between the time of the falling time latch circuit 18 and the time of the rising time latch circuit 17 which is an edge at the time of interruption. After confirming that the time difference tp, that is, the time of the pulse width is longer than a predetermined value ((2/3) · ta), the value of the counter C2 is determined to be “7” in step 406 and transmitted in step 418. The transmitted 8-bit data is rewritten from the transmission / reception buffer area 14b to the transmission / reception storage area 14a. After that, the CPU 11 executes the processing of steps 407, 408, and 409.

As described above, in the present embodiment, the start pulse is combined with the clock pulse and transmitted from the transmitting microcomputer 1 to the receiving microcomputer 2, and the combined start pulse is extracted by the receiving microcomputer 2 to transmit data. Is detected, data communication between microcomputers can be easily performed without using a start signal transmission port.

The present invention is not limited to the above embodiment. For example, in data communication, either MSB or LSB may be transmitted first, and 16-bit or 32-bit data other than 8 bits may be transmitted. You may. Further, a plurality of data signal lines 20 and 21 may be used to transmit and receive a plurality of data simultaneously. The first edge of the clock pulse may be either falling or rising.

Further, the communication data between the microcomputers is made into two types of data, that is, as shown in FIG. 7, the main microcomputer 1 sends the 8-bit data A (A7 to A0) and the 8-bit data B ( B7-B0), and 8-bit data C (C7-C0) and 8-bit data D (D7-D0) may be transmitted from the sub microcomputer 2 to the main microcomputer 1. That is, the start pulse (7th
In the figure, data may be switched by the rising and falling interrupt edges at time t1 and time t10).
That is, the communication data from the main microcomputer 1 to the sub-microcomputer 2 is stored in the storage areas M1 and M2 of the sub-microcomputer 2, and
Communication data from the sub-microcomputer 2 to the main microcomputer 1 is allocated to the storage areas M3 and M4 in the main microcomputer 1, respectively.

Then, the microcomputer 1 executes a routine interrupt processing routine for every tb time of the microcomputer 1 as shown in FIG. In FIG. 8, if the clock pulse level is "H" in step 500, the CPU 3 stores the received data in the storage area M3 in step 502.
If the clock pulse level is "L" in step 500, the received data is stored in the storage area M in step 502.
Rewrite to 4. Further, if the clock pulse level is "H" in step 503, the CPU 3 proceeds to step 504 to store the memory area M
In step 503, if the level of the clock pulse is "L", the transmission data to the storage area M2 is rewritten to the corresponding transmission buffer area in step 503.

In FIG. 8, the same step processes as those in FIG. 4 are denoted by the same step numbers, and the description thereof is omitted.

Further, an interrupt processing routine of the microcomputer 2 as shown in FIG. 9 is executed. In FIG. 9, the CPU 11 rewrites the received data to the storage area M1 in step 601 if the interrupt edge is falling in step 600, and stores the received data in step 602 if the interrupt edge is rising in step 600. Rewrite to area M2. If the interrupt edge is falling in step 603, the CPU 11
Rewrite the data sent to 3 to the corresponding buffer area,
If the interrupt edge is rising in step 603, the data transmitted to the storage area M4 is rewritten to the corresponding buffer area in step 605.

In FIG. 9, the same step processes as those in FIG. 6 are denoted by the same step numbers, and the description thereof is omitted.

In this manner, even when two data are alternately communicated, communication can be performed without providing a data determination signal.

[Effects of the Invention] As described in detail above, according to the present invention, an excellent effect that data communication between microcomputers can be performed easily and at high speed without using a start signal transmission port is exhibited.

[Brief description of the drawings]

1 is an electric circuit diagram of the microcomputer of the embodiment, FIG. 2 is a time chart of data communication, FIG. 3 is a flowchart, FIG. 4 is a flowchart, FIG.
FIG. 7 is a flowchart, FIG. 7 is a time chart of another example of data communication, FIG. 8 is a flowchart of another example, and FIG. 9 is a flowchart of another example. 1 is a microcomputer and 2 is a microcomputer.

Continued on the front page (72) Inventor Takashi Harada 1-1-1 Showa-cho, Kariya-shi, Aichi Japan Inside Denso Co., Ltd. (72) Inventor Tetsuya Abe 1-Toyota-cho, Toyota-shi, Aichi Prefecture Inside Toyota Motor Corporation (72) Inventor Kunio Nishimura 1 Toyota Town, Toyota City, Aichi Prefecture Inside Toyota Motor Corporation (72) Inventor Hirofumi Higashida 1-2-28 Goshodori, Hyogo-ku, Kobe City, Hyogo Prefecture Inside Fujitsu Ten Co., Ltd. (72) Inventor Konishi Hiroyuki 1-2-28, Goshodori, Hyogo-ku, Kobe, Hyogo Prefecture Inside Fujitsu Ten Limited (56) References JP-A-64-60036 (JP, A)

Claims (1)

(57) [Claims] 1. A receiving microcomputer detects the start of data transmission of a plurality of bits based on a start pulse from a transmitting microcomputer, and performs data communication between the microcomputers at a synchronous timing using an edge of a clock pulse train from the transmitting microcomputer. In the microcomputer communication method, a pulse having an edge interval (ta) shorter than the edge interval (tb) of the clock pulse train is created in the clock pulse train using an edge at which the transmitting microcomputer transmits the first bit data; A microcomputer communication method, wherein the pulse is the start pulse.