JPS6131481B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timer reading method for an electronic computer, and more specifically, when the update time of a timer whose value is updated from time to time and the read time are asynchronous, the read time is the update time. This invention relates to a timer read method that eliminates uncertainty in read data caused by overlapping data.

Various types of timers exist in electronic computer systems. The supervisor (OS) uses a hardware timer to detect the time at each point in time and
Provides services to programs regarding elapsed time and central processing unit usage time.

Here, for convenience of explanation, a reading method of a real time timer that displays real time in hours, minutes, seconds, and milliseconds will be described as an example of a timer.

As shown in Figure 1, the real-time timer is
Real-time timer 11, which is the upper part of a 6-digit timer that displays minutes and seconds, and 3 that displays milliseconds.
It consists of two real-time timers 12, which are the lower part of the digit length timer.

Since the data bus 18, which can transmit 4 bytes simultaneously, cannot read and transmit both real-time timers 11 and 12 at the same time, they must be read out twice. The read real time is taken into the processor 17 and then stored in the memory 2.
4 is also transmitted.

The read operation from the real-time timers 11 and 12 is performed by a microprogram, and as shown in the flow chart of FIG. After reading 6 digits, the lower part of the timer is read from the real-time timer 12, and 3 digits are transmitted to the processor 17. It takes time T from starting to read the upper part of the real-time timer to finishing reading the lower part, but since updating and reading of the real-time timers 11 and 12 occur asynchronously, the real-time timer 11 and 12 are updated during the reading time T. , 12 are updated, the upper and lower parts of the read data may have contradictory contents.

Therefore, in order to eliminate such contradictions, conventionally, as shown in the time chart of FIG. 3, an invalid period S of the real-time timers 11 and 12 is set before and after the time point (indicated by X) when the timers are updated. However, it is displayed that the data read during this period is invalid. Therefore, the update control circuit of the real-time timer is provided with a validity display bit that indicates the invalid period S. Here, the invalid period S is set so that S>T.

FIG. 4 is a block diagram of a conventional real-time timer update control circuit.

The update pulse sent via control bus 23 is latched into flip-flop 1 and then timed with clock CLK by AND gate 2 to set flip-flop 4.

When the flip-flop 4 is set, the reset output is turned off to turn off the validity indicating bit flip-flop 5, and at the same time, the counter 6 is instructed to start counting.

8 is the real time timer 1 from the output of the counter 6.
1 and 12. When the detection circuit 8 detects the update time, it sends an update pulse to the real time timers 11 and 12 via the flip-flop 9 and the AND gate 10, and the real time update.

7 is a circuit that detects when the validity display bit is released. When this detection circuit 7 detects the release time, the flip signal is output via the AND gate 3.
Reset flop 4. The flip-flop 4 turns on the validity indicating bit flip-flop 5 by means of a reset output, and at the same time instructs the counter 6 to stop counting.

The conventional method requires special hardware such as the validity display bit 5, the counter 6, and each detection circuit 7, 8 at the time of update and release. Although the read data is guaranteed to be valid, there is some overhead in which the read data becomes invalid because it is within the invalid period.

An object of the present invention is to eliminate the drawbacks of the conventional technology by using an electronic system that eliminates the uncertainty of timer read data using a microprogram without the need for special hardware and without setting an invalid period S. The purpose of this invention is to provide a computer timer reading method.

The timer read method for an electronic computer according to the present invention is to read the value of the timer in an electronic computer timer whose update time and read time are asynchronous, and then read the timer value again, and combine this value with the previously read value. The feature is that the validity of the timer read data is determined by comparing the data and detecting a match.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.

The upper part 11 of the real time timer and the lower part 12 of the real time timer are connected to an arithmetic section via a data bus 18 for reading, and the output of the arithmetic section is further connected to a control device (processor) 17.

Furthermore, the update control circuit and validity indicating bit flip-flop 5 as shown in FIG. 4 are not required, and update pulses can be applied directly to the real-time timers 11 and 12 using the clock CLK.

Also in FIG. 5, the data bus 18 is 4 bytes, and since both the upper part 1 and lower part 2 of the timer cannot be read out at the same time, they are read out in two or more stages. By micro program,
First, the contents of the real time timer 11 are transferred to the data bus 18.
The data is latched into the register 13 via the arithmetic unit 15 and the data bus 20 and stored in the memory 16. Next, the contents of the real time timer 12 are read out and stored in the memory 16 through the same route.

Next, the contents of the real-time timer 11 are latched into the register 13 again, and at the same time, the value of the real-time timer 11 stored in the memory 16 is loaded into the register 14 via the data bus 19, and the arithmetic unit 1
Compare with 5. If the values of register 13 and register 14 match, it means that there was no timer update between both reading periods, and the read data of the real-time timer is regarded as valid, and register 1
3 is sent to the control device 17.

Also, if the comparison results in a discrepancy, it means that a timer update occurred between both reading periods.
The read data is regarded as invalid and the control device 17 is notified of this fact.

In this way, in Figure 5, the validity of the data is determined from the read data, so there is no need for hardware to display the validity period of the data in advance, and the timer can be set up simply by programming the microprogram. This can solve the problem when reading data.

In addition, in the explanation so far, the case has been described in which the timer is divided and read out multiple times, but the present invention is also effective in the case where one timer is read out as a whole at one time. In other words, if a timer read and a timer update occur at exactly the same time, there is a possibility that a temporarily incorrect value may be read as is, such as when only a portion of the timer's bits are updated. There is.

In this case as well, as shown in FIG. 5, the same timer is read twice and compared by the arithmetic unit 15, and only if they match, the contents are considered valid, thereby eliminating the above-mentioned invalid values. be able to.

Note that, in FIG. 5, it is desirable that the time interval between two readings of the timer be made sufficiently smaller than the update time interval of the timer.

As described above, according to the present invention, uncertainty in read data can be eliminated using only a microprogram without installing special hardware for a timer that is updated asynchronously with reading.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of the real-time timer and the connection of read data, FIG. 2 is a flowchart of the microprogram when reading the real-time timer,
FIG. 3 is a time chart of timer updating and validity indicating bits, FIG. 4 is a block diagram of a conventional real-time timer update control circuit, and FIG. 5 is a block diagram showing an embodiment of the present invention. 11, 12... Real time timer, 13, 14...
Register, 15...Arithmetic unit, 16...Memory, 1
7...control device, 18,19,20...data/
Bus, 23... Control bus, 1, 4, 5, 9... Flip-flop, 6... Counter, 7, 8...
Detection circuit for update and release.

Claims (1)

[Claims] 1. In a computer timer whose update time and read time are asynchronous, after reading the value of the timer, read the value of the timer again, compare the read value with the value read earlier, and check if the comparison results match. 1. A timer read method for an electronic computer, characterized in that the validity of read data of the timer is determined by detecting the timer.