JPH0431420B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a serial I/O circuit built into a microcomputer or the like.

(b) Conventional technology In recent years, one-chip microcomputers have become more sophisticated and have come to include various peripheral circuits. As an example, when a plurality of microcomputers are used, there is a microcomputer that has a built-in serial I/O circuit for transferring data between the microcomputers using a small number of input/output terminals.

Conventionally, serial I/O circuits built into microcomputers were described on page 73 of "Fundamentals of One-Chip Microcomputers and Their Applied Technologies" published by CQ Publishing Co., Ltd. on April 1, 1981. It is structured as if it were there. Figure 2 shows its block diagram.

In FIG. 2, shift register 1 is composed of 8 bits, and its input is connected to serial input terminal 2.
The output is connected to serial output terminal 3. Also,
The synchronous clock CP that controls the shift operation of the shift register 1 uses an external synchronous clock SCP that is externally applied to the synchronous clock input/output terminal 4 when receiving data, and an internal synchronous clock SCP that is applied to the synchronous clock input/output terminal 4 when transmitting data. A clock SCP′ is used, but these synchronous clocks CP are AND
It is applied to the shift register 1 and the counter 7 via the gate 6. Counter 7 is shift register 1
It counts the number of constituent bits of ``8'', and when 8 synchronous clocks CP are counted, shift register 1
Assuming that data input to the shift register 1 or data output from the shift register 1 has been completed, the FF8 is reset and the synchronous clock CP is cut off at the AND gate. Note that FF8 is set when the data transmission/reception start command is executed.

(c) Problems to be solved by the invention In the serial I/O circuit shown in FIG. 2, when inputting data serially, the external synchronous clock SCP applied to the synchronous clock input/output terminal 4 By the falling edge of shift register 1
A shift operation is performed, and the data applied to the serial input terminal 2 is taken in. Therefore, when eight externally synchronized clocks SCP are counted by counter 7,
FF8 is reset and external synchronization clock SCP is cut off. After that, the synchronous clock input/output terminal 4
Even if a clock is applied to , the shift operation of the shift register 1 is not performed, and the serial input of data is completed.

However, if noise occurs in the external synchronization clock for some reason as shown in Figure 3 during serial input of data, the noise causes the shift operation of shift register 1 and the counting operation of counter 7 to be performed in the same manner. The data will be captured twice. Therefore, when the counter 7 counts eight items, the last sent data is not taken into the shift register 1, resulting in erroneous data transfer. Therefore, the serial I/O shown in FIG.
In circuits, the reliability of transfer due to noise decreases, so the same data must be repeated several times and a program must be used to determine whether the data matches or not. The drawback was that it took a long time.

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and it is possible to increase the counting capacity of a counter that counts synchronous clocks to a capacity larger than the number of synchronous clocks required for data transfer. and shift register control means for detecting that the counter has counted the number of synchronous clocks necessary for data transfer and prohibiting the shift operation of the shift register, and whether the count value of the counter has changed after the detection operation of the control means. An overrun detection means is provided to detect whether or not the data transfer has occurred, and an error in data transfer can be recognized based on the detection result of the overrun detection means.

(e) Effect According to the above means, if no noise occurs in the external synchronous clock SCP applied to the synchronous clock output terminal, the number of synchronous clocks required for data transfer is counted by the counter and the shift register is After the shift operation is prohibited by the control means,
Since the count value of the counter does not change, the detection result of the overrun detection means does not indicate an error in data transfer. On the other hand, if noise occurs in the external synchronous clock SCP, the counter counts the number of clocks required for data transfer and then continues counting, so the detection result of the overrun detection means is It will indicate a mistake,
Based on this instruction, it can be recognized that the data transferred to the shift register is erroneous.

(F) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention. The shift register 9 is composed of 8 bits, the input is connected to the serial input terminal 10, the output is connected to the serial output terminal 11, and the input/output of each bit of the shift register 9 is connected to the data bus 12, so that data can be sent and received. Constructed to run in parallel. An external synchronous clock SCP is applied to the synchronous clock input/output terminal 13 when receiving data serially, and a clock generated by the clock generating circuit 14 is applied when serially transmitting the data held in the shift register 9. This is the terminal to which the internal synchronous clock SCP' is sent. These synchronous clocks CP are
AND gate 16 controlled by the output Q of R-SFF 15 and controlled by the output Q of R-SFF 17
The output of AND gate 16 is connected to the shift clock input of shift register 9, and the output of AND gate 18 is applied to counter 1.
Connected to the counting input of 9. The counter 19 is 4
It is a hexadecimal binary counter consisting of bits, and counts the falling edge of the synchronized clock CP applied from the AND gate 18, and when the count value reaches "8", that is, "1000", the output is R-SFF15. Reset. That is, since the shift register 9 has an 8-bit configuration, one serial transfer of data is performed in units of 8 bits, and eight synchronous clocks CP are required for this transfer. By detecting ``8'', the end of 8-bit data transfer is detected. R-SFF1
Reference numeral 5 constitutes a shift register control means, which is set by the execution of a data transmission/reception start command and, during the set period, transfers the synchronized clock CP from the AND gate 16 to the shift register 9.
to be applied. In addition, each bit output of the counter 19
Q ₁ , Q ₂ , Q ₃ and ₄ are applied to an OR gate 20 , and the output of the OR gate 20 is connected to the flag 22 of the status register 21 . These, OR
The gate 20 and the flag 22 constitute overrun detection means. That is, when the count value of the counter 19 is "8", the output of the OR gate 20 is "0" and the flag 22 becomes "0", but when the count value of the counter 19 is other than "8" OR
The output of the gate 20 becomes "1" and the flag 22 is set to "1". On the other hand, R-SFF17 is
The counter 19 is set by executing the data transmission/reception start instruction and reset by executing the register read instruction to read the data in the shift register 9.
Even if the synchronous clock CP is cut off by the AND gate 16 when the counter counts "8", the clock generated at the synchronous clock input/output terminal 13 is supplied to the counter 19 until the register read command is executed. That is, since the counter 19 continues counting even after the shift operation of the shift register 9 is prohibited, if noise occurs in the external synchronization clock SCP and the number of pulses increases, the increased amount will be counted by the counter 19. become.

The operation of serially inputting data in the serial I/O circuit shown in FIG. 1 will be described. First, after executing an instruction to inhibit the generation of the internal synchronous clock SCP', when a data transmission/reception start instruction is executed, the R-SFFs 15 and 17 are set and the counter 19 is reset. Next, it sends a signal to the other party to which the data is to be serially sent, allowing it to send the data. Then, data is sequentially applied from the other party to the serial input terminal 10, and the external synchronous clock SCP is applied to the synchronous clock input/output terminal 13 in synchronization with the data. The external synchronization clock SCP is applied to the shift register 9 via the AND gate 16, and as the clock falls, the shift register 9 sequentially takes in and shifts the data applied to the serial input terminal 10. At the same time, the external synchronization clock SCP is counted by the counter 19 via the AND gate 18. When the count value of the counter 19 reaches "8", the R-SFF 15 is reset by its output, so that the AND gate 16 cuts off the external synchronization clock SCP that will arrive from then on, and prohibits the operation of the shift register 9. Ru. At this time, R-SFF
The output of 15 requests an interrupt to the computer, and interrupt processing is performed. In this interrupt processing, the flag 22 of the status register 21 is determined when a period of one cycle or more of the external synchronization clock has elapsed since the occurrence of the interrupt. That is,
If noise occurs before the counter 19 counts "8", it means that the noise has been counted by the counter 19, and since the external synchronous clock SCP is always counted after one cycle of the external synchronous clock SCP, OR The output of the gate 20 becomes "1" and the flag 22 is set to "1". Therefore, if the result of determining the flag 22 after one cycle of the external synchronous clock SCP is "0", data reception has been completed by the eight external synchronous clocks SCP, and the data accumulated in the shift register 9 is is determined to be correct, and in this case, a register read instruction is executed to take out the contents of the shift register 9 to the data bus 12 and predetermined processing can be performed. At this time, the R-SFF 17 is reset by executing the register read instruction, and the serial reception of data is completed. On the other hand, if the result of determining the flag 22 is "1", it is determined that the data accumulated in the shift register 9 is erroneous, and in this case, the data transmission/reception command is executed again. Request the other party to transfer the same data.

In this way, by determining the contents of the flag 22 after a predetermined period of time after it is determined that the data transfer has been completed, it is possible to detect whether noise has occurred in the external synchronization clock SCP and determine whether the data is correct or incorrect. . Therefore, there is no need to perform multiple transfers to confirm correctness. In addition, in the above-mentioned embodiment,
Although we have explained the case of serially inputting data, the same applies to the noise generated at the synchronous clock input/output terminal 13 when transmitting data based on the internal synchronous clock SCP' generated by the clock generation circuit 14. Through this operation, errors in data transfer can be detected.

(G) Effects of the Invention As described above, according to the present invention, there is no need to transfer the same data multiple times to determine whether the data is correct or incorrect, so the data transfer time is shortened and the computer's response becomes faster. have In addition, the program for determining correctness is shortened, and a microcomputer that is easy to use can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional example, and FIG. 3 is a timing diagram illustrating malfunctions due to noise. 9...Shift register, 10...Serial input terminal, 11...Serial output terminal, 12...Data bus, 13...Synchronized clock input/output terminal, 14
...Clock generation circuit, 15, 17...R-
SFF, 16, 18...AND gate, 19...Counter, 20...OR gate, 21...Status register, 22...Flag.

Claims (1)

[Claims] 1. In a serial I/O circuit having a shift register that sequentially inputs data applied to a serial input terminal based on a synchronous clock, the counting capacity is larger than the number of synchronous clocks required for data transfer of the shift register. and a counter that counts the synchronous clocks, and a counter that is set when the data transfer instruction of the shift register is executed and when the counter counts the number of synchronous clocks required for the data transfer of the shift register. a first flip-flop that is reset by a predetermined 1-bit output of the flip-flop, and a set output or a reset output of the first flip-flop;
a first logic gate that controls a state in which the synchronous clock is applied to the shift register; and a first logic gate that is set when the data transfer instruction is executed and reset when the shift register data read instruction is executed. a second flip-flop; a second logic gate for controlling the state in which the synchronous clock is applied to the counter; a third logic gate that detects a state in which the count value of the counter overruns; and a flag that is set by a logic output of the third logic gate when the count value of the counter overruns. generating an interrupt request by the reset output of the first flip-flop;
A serial I/O circuit, characterized in that it executes interrupt processing to determine the flag based on the interrupt request, thereby making it possible to recognize errors in data transfer of the shift register.