JP3013745B2 - Digital modulation / demodulation method, device, recording medium, and method of manufacturing - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to m bits (for example, 8 bits).
Bit) and a method for digital modulation / demodulation for converting an n-bit (for example, 15-bit) modulation code, an apparatus, a recording medium, and a manufacturing method thereof. And a digital modulation / demodulation method suitable for transmission.

[0002]

2. Description of the Related Art When digital data is recorded on a medium or transmitted using a communication channel, data code conversion (so-called Channel Coding) is usually performed so as to match the characteristics of the recording system and the transmission system. Is performed. Various modulation schemes for such encoding are already known, for example, Japanese Patent Publication No. 1-27510, Japanese Patent Publication No. 5-68031, Japanese Patent Application Laid-Open No. 58-220213, JP-A-58-2
JP-A-20214, JP-A-58-220215, JP-A-61-84124
There are those disclosed in Japanese Unexamined Patent Application Publication Nos. H11-157, and H10-A1. Hereinafter, typical ones will be described.

(1) 8/14 modulation (EFM, Eight to Fo
urteen Modulation) As is well known, this is a modulation method used in a CD system. The 8-bit data is converted into a 14-channel digital modulation code. A digital modulation code of 14 channel bits has a data bit interval T
, The minimum length between tansition
Tmin = 3T (d = 2), that is, logical values “1” and “1”
And at least two “0” are included between them. Maximum lenght between transitio
n) Tmax = 11T (k = 10), that is, a logical value “1”
The number of “0” between “1” and “1” is 10 at the maximum. It satisfies the condition.

When two consecutive blocks of such a 14-channel digital modulation code are combined to generate a digital modulation code sequence, a 3-bit combination bit is inserted between the blocks. As a result, the 8-bit digital data is converted into a 17-channel bit digital modulation code.

The setting of the logical value of the three combined bits is as follows:
If the minimum inversion interval condition Tmin = 3 is satisfied between the modulation code of the block before and after the combined bit, the maximum inversion interval Tmax is within 11T by setting one of the combined bits to “1”. And the DSV (Digital Sum Value) is reduced.

(2) 4/8 Modulation (Japanese Patent Application Laid-Open No. 61-84124) This publication discloses a digital modulation technique for converting 4-bit data into an 8-bit digital modulation code of Tmin = 3T. The purpose is to suppress low frequency components after modulation. A plurality of places in the conversion table include arbitrary bits whose logical value may be either “1” or “0”. As a result, the digital modulation code is converted into a time-series serial signal in which the logical value “1” is not continuous, and Tmax is limited and DSV is controlled.

When an 8-bit digital modulation code is continuously combined to form a time-series serial signal, the second bit from the end of the previous modulation code has a logical value of “1” and the next modulation code has the logical value “1”. If the first bit starts with a logical "1",
The condition of Tmin = 3T (d = 2) is not satisfied. Therefore, the last bit of the modulation code is set to a logical value “1”, and the second bit from the end of the previous modulation code and the first bit of the subsequent modulation code are each set to “0”. Processing is performed to satisfy d = 2.

In this background art, since data is converted into a digital modulation code in units of 4 bits, there is an advantage that the conversion table may be small and the hardware size may be small. In a digital processing device, signal processing is performed almost in units of bytes.
In the modulation method, data of 1 byte = 8 bits is divided into 4 bits, and each is converted into 8 bits. From such a point, it can be considered that this is substantially equivalent to a digital modulation method of converting 8-bit byte data into a 16-bit digital modulation code.

[0009]

Among the above background arts, in the 8/14 modulation system (EFM), the minimum inversion interval as viewed from 8-bit data is 3 × 8 /.
17 = 1.41 Tb, and therefore DR (Density Rati
o) becomes 1.41. On the other hand, in the 4/8 modulation method, the minimum inversion interval viewed from the 4-bit data is 3 × 4/8.
= 1.5Tb, so DR is 1.5. 8 /
Compared with the 14 modulation system, the DR is large, and it is a system capable of increasing the density of information.

However, recently, there has been a demand for recording and reproducing and transmitting information at a higher density, and a modulation system with a larger DR (longer minimum inversion interval) has been demanded. In general, in a modulation code having the same DR, it is preferable that the modulation signal has a low low frequency component in terms of influence on a servo system and data detection. The present invention focuses on the above points, and an object of the present invention is to improve information density in recording, reproduction, and transmission.

Another object is to obtain the maximum inversion interval Tmax and DS
V is to be minimized. Still another object is to improve controllability of the DSV and reduce low frequency components.

[0012]

In order to achieve the above object, according to the modulation method of the present invention, m-bit digital data is converted from a logical value "1" to a logical value "0" by a minimum inversion.
From d indicating the interval to k indicating the maximum inversion interval (k> d)
N (n> m) channels satisfying the inversion interval condition
N bits, and two consecutive n's after the conversion.
Connected bits inserted between channel bits and connected
Modulate and code to satisfy the inversion interval condition
At this time, between two consecutive blocks of the obtained n-bit digital modulation code, d-1 combination bits of a logical value satisfying the condition of the inversion interval are inserted.

At this time, if any one bit before and after the combined bit is “1”, a modulation process is performed to set these bits to “0” and set any one of the combined bits to “1”. In addition, “0” continues d + 1 or more on either side before or after the combined bit, and “0” is 2d + on the other side.
In the case where one or more bits are continuous, and in the case where 2d + 1 consecutive “0s” are present before and after the combined bit, the combined bit is set to “1”, and “0” is 2d + 1 or more consecutive modulation code blocks. A modulation process for setting the (d + 1) th bit from the combined bits to “1” is performed. In another invention, a modulation process is performed to set one or both of the (d + 1) th bits to “1” in consideration of DSV.

In the digital demodulation method according to the present invention, the demodulation processing opposite to the modulation processing is performed by referring to a combination bit of a digital signal modulated by the digital modulation method and a logical value of data of a modulation code block before and after the combined bit. And a demodulation process for obtaining a digital modulation code of n channel bits is performed. Then, the demodulated n-channel bit digital modulation code is subjected to the reverse conversion to the above data conversion to obtain m-bit digital data.

According to the digital modulation method of another invention,
In the above-mentioned modulation method, an insertion bit for selecting a pattern so as to arbitrarily obtain a polarity inversion is inserted into a code sequence at predetermined intervals, thereby improving the controllability of DSV. The number of bits to be inserted is as small as possible while satisfying the conditions of the minimum inversion interval and the maximum inversion interval.
For example, it is set to 5 bits or 4 bits.

The main aspects of the present invention are as follows. (1) At least two “0” s are included between the logical values “1” and “1” of the 8-bit digital data.
Means for converting to a modulation code of channel bits, and means for inserting a 1-bit combination bit when combining two consecutive blocks of the modulation code of 14 channel bits to generate a modulation code sequence, A digital modulation device for converting 8-bit digital data into a 15-bit modulation code and subjecting the output to NRZI conversion.

In the case where the last bit and the first bit of two consecutive blocks of the 14-channel bit modulation code are a combination of modulation codes in which both sides of the combination bit are "1", the combination bit is set to "1". And conversion means for changing both bits from “1” to “0”;

"0" is 3 on either side of the combined bit.
If more than 5 consecutive "0" s on the other side (including 5 or more consecutive "0" on both sides of the combined bit), set the combined bit to "1",
A bit at a position 3 bits away from the connected bit on the side where 5 or more “0” s are consecutive from the connected bit is “1”
Conversion means, whereby the maximum inversion interval or D
SV, or Digitally Le modulation apparatus characterized by both their selectively / adaptively controlled.

(2) 8-bit digital data is set to "1"
1 that contains at least two “0” s between “1” and “1”
As a code pattern of a conversion table for converting into a modulation code of 4 channel bits, the number of "0" between "1" and "1" is limited to 10 or less, and "0" is consecutive at the beginning or end of the pattern. The digital modulation device according to (1), wherein a pattern including twelve “0” s between “1” and “1” is used as a synchronization pattern when a conversion table in which the number of operations to be performed is eight or less is used.

(3) By interposing a d-1 bit combination bit provided for the purpose of combining two data blocks, m-bit digital data can be converted to n + d-
In the modulation method of converting into modulation code of 1 bit (m <n), generating a DSV controlled modulated coded information by further inserted adjacent to the bond bit insertion bit Tokoro Teibi Wattage predetermined intervals A digital modulation method.

(4) m = 8 , n = 14 , d = 2, k = 1
1 , and in a method of forming a modulation code of d = 2,
A digital modulation method, wherein the insertion bits having the number of insertion bits of 5 are inserted adjacent to combination bits at predetermined intervals.

(5) When inverting the polarity, the second bit or the third bit counted from the coupling bit is set to "1".
And If the polarity is not inverted, all 6 bits of the insertion bit and the combination bit are set to “0”, or 2 bits of the total of 6 bits of the insertion bit and the combination bit are set to “1” (3) Or the digital modulation method described in (4).

(6) The digital modulation method according to (5), wherein the selection of a non-inverted pattern is determined based on the last two bits of the preceding block and the preceding two bits of the succeeding block.

(7) By referring to the combination bits and the insertion bits of the digital signal modulated by the digital modulation method described in the above (3) and the logical values of the data of the modulation code blocks before and after the digital signal, the reverse of the modulation processing is performed. Demodulation processing of
A digital demodulation method and apparatus comprising a demodulation processing step of obtaining an n-bit digital modulation code and obtaining data demodulated from the n-bit logical value.

(8) m = 8 , n = 14 , d = 2, k = 1
1 , and in a method of forming a modulation code of d = 2,
(3) The digital modulation method according to (3), wherein the insertion bits having the number of insertion bits of 4 are inserted adjacent to the combination bits at predetermined intervals.

(9) When inverting the polarity, a bit that is two bits away from the combined bit is set to “1”. If not inverted, all 6 bits of the insertion bit and the combination bit are set to “0”, or 2 bits of the total of 6 bits of the insertion bit and the combination bit are set to “1”, or , The insertion bit or the combination bit is set to “1”, and the third bit from the back of the previous block or the third bit from the front of the rear block is set to “1” (8).

(10) The digital modulation method according to (9), wherein the selection of the non-inverted pattern is determined based on the last two bits of the preceding block and the preceding two bits of the succeeding block.

(11) Referring to the combination bit and the insertion bit of the digital signal modulated by the digital modulation method described in the above (8) and the logical value of the data of the modulation code block before and after the digital signal, the reverse of the modulation process is performed. A digital demodulation method and a demodulation method comprising a demodulation process step of performing demodulation processing to obtain an n-bit digital modulation code and obtaining data demodulated from the n-bit logical value.

(12) Referring to the exclusive OR of the combination bit and the insertion bit of the digital signal modulated by the digital modulation method described in the above (8) and the logical value of the data of the modulation code block before and after it, The digital demodulation method and apparatus according to (11), further comprising a demodulation step of performing an inverse demodulation process to the modulation process, obtaining an n-bit digital modulation code, and obtaining data demodulated from the n-bit logical value.

The above and other objects, features and advantages of the present invention will become apparent from the following detailed description and the accompanying drawings.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The digital modulation / demodulation method, the apparatus, the recording medium, and the manufacturing method of the present invention may have many embodiments, but an appropriate number of embodiments will be shown and described in detail.

* Example 1 * <Modulation Processing Method> First, a modulation processing method according to an embodiment will be described with reference to FIGS. In addition, 8
A case where bit data is converted into 14 channel bits by the conversion table of Table 1 will be described as an example. This conversion table is used in the above-described EFM. FIG. 10 is a flowchart summarizing the following conversion processing operations.

[0033]

[Table 1]

In the table, 8-bit data is represented in decimal. For example, 8-bit “2” is converted into a modulation code represented by 14 channel bits “10010000100000”. The 8-bit “128” is converted into a modulation code represented by 14 channel bits “01001000100001”. The other 8-bit data is as shown in the table. The blocks of the modulation code after the conversion are combined by one combination bit as shown in FIG. The combined bit is mb, and the preceding bit is b-4, b-3, b-2, b-1
(Or... B11, b12, b13, b14), and the subsequent bits are represented by b1, b2, b3, b4. Also, Tmin = 3T (d = 2), Tmax = 12T (k = 1
1).

(1) Normal case of the conversion sequence For example, as shown in FIG. 1B, the modulation code block before the combined bit mb is “00100000010010” (“255” of 8-bit data) and the subsequent block Is "0010010000
0000 "(" 7 "of 8-bit data). As described above, when the previous block ends with “... 10”, the combination bit mb cannot be set to the logical value “1” from the condition of Tmin = 3 (d = 2). (Step S14 → S16 in FIG. 10). As a result, NRZ
The signal waveform due to I (Non Return to Zero Inverted) is as shown in FIG. In the case where data is recorded as a series of pits and lands on a disk according to this signal waveform, if the H level of the waveform corresponds to the pits and the L level corresponds to the lands, the result is as shown in FIG.

(2) Case where the value before and after the combined bit is "1" Next, as shown in FIG.
Is a modulation code block “01001000100001” (“128” of 8-bit data), and a subsequent block is “1000”.
0100000000 ”(“ 1 ”of 8-bit data). Thus, when the previous block ends with "... 01" and the subsequent block starts with "10...", Tmin = 3T even if the combination bit mb is set to "0".
The condition (d = 2) cannot be satisfied.

Therefore, the previous block is "1".
And the subsequent block starts with "1", the combined bit mb is set to "1", the end bit of the previous block and the subsequent block are set as shown in FIG. Are converted to “0” (steps S10 → S12). By doing this,
It is possible to satisfy the condition of Tmin. N in this case
The signal waveform by RZI is as shown in FIG.

(3) When "0" is continuous before or after the combined bit for the maximum inversion interval Tmax or longer Next, for example, as shown in FIG.
Is a modulation code block “00000100010000” (8-bit data “5”), and a subsequent block is “00000001”.
000000 "(" 13 "of 8-bit data).
In this case, the previous block ends with four "0s" and the subsequent block starts with seven "0s".
Assuming that the value of the combination bit mb is 0, twelve “0” s continue before and after the combination bit, and Tmax = 12T (k
= 11).

On the other hand, if the two bits before and after the combined bit mb are both “0”, the condition of Tmin = 3 can be satisfied even if the combined bit mb is set to “1”. If the coupling bit mb is set to "1" to cause the inversion, the pit length or the land length is restricted from being continuously increased to "0" as shown in FIG. (Steps S20 → S22). But,
In this case, FIG.
It cannot be distinguished from the case of (B).

When the condition of Tmin is satisfied by the processing of FIG. 2, the value before and after the combination bit mb is always "1". Further, since the conversion table of Table 1 satisfies the condition of Tmin = 3, at least two “0” s are always consecutive to “1”. That is, the previous modulation code block is “……”
It can be guaranteed that it ends with "001" and the subsequent blocks start with "100 ...". In other words, in the case of FIG. 2, the third bit before and after the combination bit mb is always “0”.

Therefore, if any one of before and after the combined bit mb is a continuous "00000" of at least five or more "0" s, the combined bit mb is set to "1", and 3 bits are separated from the combined bit mb. One of the bits is set to "1" (steps S24, S26). In the example of FIG. 3A, the rear side of the combination bit mb is a sequence of five or more “0”. Therefore, as shown in FIG. 7B, the third bit from the beginning of the block after the combination bit mb is set to “1”. In this way, it is possible to distinguish from the case where Tmin in FIG. 2B is limited, and it is possible to satisfy the condition of Tmin as a whole. In this example, assuming that the third bit before the combination bit mb indicated by the dotted arrow is “1”, Tmin = 3
Condition cannot be satisfied. The signal waveform is as shown in FIG.

The third bit from the combination bit mb may be set to "1" in order to identify that such processing for limiting Tmax has been performed, either before or after that. Also,
Since it is necessary to avoid the case where the third bit is “1”, the condition for performing the process of limiting the Tmax is that at least five of the 5 bits before and after the combined bit mb are consecutive “0”. 00000 ”, and at the same time, at least one of the front and rear sides is“ 000 ”in which at least three“ 0 ”s are continuous.

As described above, 3 bits before and after the combination bit mb
Since the bit is “1”, for example, FIG.
When the fourth bit is “1” as shown in (B),
The combination bit mb cannot be set to “1”. Assuming that mb is “1”, as shown in FIG. 3C, the third bit before or after that is “1” by the above-described conversion processing.
Thus, "1" continues, and the condition of Tmin is not satisfied. Therefore, in such a case, the combined bit mb is set to “0” (step S18 → S16).

(4) Maximum Inversion Interval Next, the maximum inversion interval in the code sequence including the combination bit mb in this embodiment is obtained by the conversion processing before and after the combination bit for limiting Tmin and Tmax as described above. Tmax
Will be described. As shown in Table 1, in the 14 channel bits which are the modulation codes of the EFM 8 → 14 conversion, 10 “0” continuations and “0” continuations at both ends of the modulation code block are within 8 continuations. If it exists, the maximum inversion interval Tmax in the code sequence including the combination bit mb is 12T.

FIG. 5 shows an example of a code sequence of Tmax = 12T. In the example of FIG. 3A, the sequence is a sequence of modulation code blocks B1 to B3. Block B1, B
Since the value before and after the combination bit mb of “2” is “1”, the conversion processing shown in FIG. 2 is performed. At the combined bit mb of the blocks B2 and B3, the value is "0" because the condition of the above-described conversion processing is not particularly satisfied.
As a result of such conversion processing, as shown in FIG.
max = 12T.

(5) DSV Control Next, a DSV control method will be described with reference to FIGS. FIG. 6A shows a case where the block before the connection bit mb is “01001000100000” (8-bit data “0”) and the block after it is “00000001000000” (8-bit data “13”). Have been. In this example, the previous block ends with five "0s" and the subsequent block starts with seven "0s." in this case,
Assuming that the combination bit mb is “0”, the number of consecutive “0” including the combination bit mb becomes 13, which exceeds Tmax = 12T. Therefore, as shown in FIG. 3, the coupling bit mb is set to “1” to perform inversion, thereby limiting the pit length or the land length from becoming longer (FIGS. 6B, 6D, and 6F). )reference).

In this example, five or more “0” s are consecutively “00000” in all of the blocks before and after the combined bit mb, so that both the preceding and following blocks are combined bits mb.
The third bit can be set to “1”. FIG.
(B) is an example in which the third bit of the previous block is set to "1" (step S24), (D) is an example in which the third bit of the subsequent block is set to "1" (step S26),
(F) is an example in which the third bit of both blocks before and after is set to "1" (step S28).

The signal waveform by NRZI is shown in FIG.
(E) and (G) respectively. When (C) and (G) are compared, the polarities of the third and subsequent bits after the combined bit mb are reversed. If this is used, the DSV after the third bit after the combined bit mb
Can be controlled. That is, the determination of whether to perform the conversion process (B) or (F) is temporarily suspended, and both the case of (B) and the case of (F) over a certain range include the third bit DSV with subsequent data
It is possible to take a measure of calculating the variation of the data and selecting the smaller one as appropriate.

Similarly, when (E) and (G) are compared, the polarity of the third and subsequent bits from the combined bit mb is reversed. Further, comparing (C) and (E), the polarity is reversed between the third bit before and after the combined bit mb. In these cases, the conversion decision is also temporarily suspended,
It is sufficient to calculate the DSV variation due to the data of the third and subsequent bits over a certain range in both cases, and to appropriately select the smaller one.

Next, in the example of the code sequence shown in FIG. 7A, the number of “0s” between the last “1” of the previous block and the first “1” of the subsequent block is supposed to be a combination bit. Even if mb is set to “0”, the number is 11 and does not exceed Tmax = 12T. Therefore, as shown in FIG.
Need not necessarily be inverted. However, as shown in (D), (F), and (H) of the same figure, the combined bit mb may be set to “1”, and either or both of the third and preceding bits may be converted to “1”. .

Therefore, in this case, there are four possible bit patterns in total (step S3).
0, S32, S34, S36). The signal waveforms are as shown in FIGS. 3 (C), 3 (E), 3 (G) and 3 (I). Any of these patterns may be appropriately selected so that the DSV is reduced.

Next, in the example of the code sequence shown in FIG. 8A, even if the combined bit mb is set to "0", the value does not exceed Tmax, and therefore, as shown in FIGS. Two patterns can be selected depending on whether the combination bit mb is "0" or "1" (steps S36 and S3).
2). If the third bit before the combined bit mb is set to "1", the condition of Tmin = 3 is not satisfied, so that this pattern cannot be selected. The signal waveform is shown in FIG.
As shown in (E), it may be appropriately selected from these to reduce the DSV. Through the above processing, both the inversion interval and the DSV can be selectively and adaptively controlled.

<Frame Synchronization Pattern> As described above, in this embodiment, 8 / T is such that Tmax is 12T.
Fourteen conversion tables have been selected. For this reason, since a pattern of 13T or more in which twelve “0” s are continuous does not occur, as shown in FIG.
If the pattern includes 3T, reliable frame synchronization can be realized.

Note that X in the frame synchronization pattern shown in FIG.
Is a bit that can be set to "0" or "1" arbitrarily,
This is inserted in order to set the DSV to be small. That is, the determination as to whether X = 0 or X = 1 can be made arbitrarily until the end of the next frame, or can be arbitrarily set so that the DSV described in the section of (5) DSV control becomes small. Hold the decision temporarily until the bit appears.

Then, the variation of the DSV up to that time is calculated, and it is appropriately selected whether X = 0 or X = 1 so that the DSV value is reduced. By doing so, the controllability of the DSV is improved as compared with the case of the DSV control using only the combination bit, and the low-frequency component of the signal can be reduced. FIGS. 7B and 7C respectively show X
NRZI signal waveforms when = 0 and X = 1 are shown.

<Modulator and Disk Manufacturing Apparatus> Next, a modulator and a disk manufacturing apparatus using the modulator will be described with reference to the block diagram of FIG.

The 8-bit data is input to the conversion ROM 10. The conversion table shown in Table 1 is stored in the conversion ROM 10, whereby 8-bit data is converted into a modulation code of 14 channel bits. The converted modulation code block is sequentially transferred to the registers 12 and 14, and the registers 12 and 14 store data of two blocks before and after, respectively. The data stored in the register 14 is supplied to the selector 18 together with the code of the frame synchronization pattern output from the synchronization code output unit 16, where the data is selected and stored in the memory 20.

On the other hand, the front few bits of the modulation code block stored in the register 12 and the rear several bits of the previous modulation code block stored in the register 14 are referred to by the combined bit processing unit 22 and The connection of the logical values of the codes is determined, and the connection bit is provisionally determined. At this time, if the logical value pattern is DSV-controllable, the address value of the selectable bit position of the logical value is:
It is stored in the address pointer 24 and supplied to the DSV calculation & code determination unit 26.

The DSV control & code determination section 26 is supplied with the provisionally determined combination bit, the address of a selectable bit position, and the subsequent modulation code block data. Then, based on these data, the variation of the DSV corresponding to the logical value of the selectable address is calculated, and the logical value at which the DSV is optimal is obtained as described above. As a result, the logical value of the subsequent modulation code block and the logical value of the combination bit are determined. When the logical value of the provisionally determined combined bit is changed, the logical value is changed to the logical value. When it is not necessary to change the logical value, the provisionally determined logical value is determined as the logical value of the combined bit. The above modulation processing operation is as shown in FIG.

The address value from which the logical value can be selected is stored in the pointer register 24 as described above, and the address is designated by the pointer register 24 when the address is counted by the address counter 28. Then, the logical value of the designated address is determined by the DSV calculation & code determination unit 2.
The instruction is set based on the output of No. 6, and the final determined value is stored in the memory 20.

The 14-channel bit data and the combination bits of the modulation code block stored in the memory 20 are output in parallel to the parallel / serial conversion unit 30, where they are serially converted and supplied to the NRZI conversion unit 32. . NRZI
The conversion unit 32 generates an inverted NRZI modulated signal based on the input data with a logical value “1” and a non-inverted NRZI with a logical value “0”. This modulation signal is supplied to the optical modulator driving circuit 34.

A light source 3 is provided on a disk 36 as a recording medium.
After the recording light output from 8 is modulated by the optical modulator 40, it is irradiated via the projection optical system 42. In the optical modulator driving circuit 34, the optical modulator 40 is driven in accordance with the input modulation signal. That is, the light supplied from the light source 38 is modulated by the optical modulator 40 based on the modulation signal. Then, pits and lands are formed on the disk 36 based on the modulated light.

<Demodulation Processing Method> Next, a demodulation processing method will be described with reference to FIG. Basically, a process that is the reverse of the conversion process of the modulation method described above may be performed. Since the frame synchronization pattern is added to the signal sequence reproduced or transmitted from the recording medium as described above, the modulation code block and the combination bit are recognized by referring to the frame synchronization pattern.

First, the connection bit mb is set to the logical value “1”.
It is determined whether or not (FIG. 12, step S50). As a result, when the combination bit mb is not “1”, that is, when it is “0”, for example, FIG. 1 (B), FIG. 7 (B), FIG.
Since the modulation process as shown in FIG. 9B has been performed, the inverse 14 → 8 conversion in Table 1 is performed on the modulation code block before the combined block mb (step S52).

Next, when the combined block mb is "1" and the preceding three bits are "100", for example, FIG.
Since the modulation process as shown in (D) and (H) is performed, the third bit before is set to “0” (step S54 →
S56). Similarly, three bits after the combination bit mb are “00”.
1 ", for example, as shown in FIG. 3 (B), FIG. 6 (D),
(F), FIG. 7 (F), FIG. 7 (H), and FIG. 8 (D) when the modulation processing is performed.
(Steps S58 → S60, FIG. 6 (F), FIG. 7)
In the case of (H), steps S59 → S60). Then, the conversion from 14 to 8 is performed (step S52).

Next, based on the determination results in steps S54 and S58, when the combination bit mb is "1" and before and after "0",
Since the modulation processing shown in FIG. 2B has been performed, the bits before and after the combined bit mb are converted to “1” (step S62). Then, the conversion from 14 to 8 is performed (step S52).

<Demodulator> Next, the demodulator will be described with reference to the block diagram of FIG. The apparatus shown in the drawing is an example in which the demodulation apparatus of this embodiment is applied to a disk reproducing apparatus for reproducing a signal read from the disk 36 recorded by the disk recording apparatus shown in FIG.

The signal read from the disk 36 is supplied to a detector 50, where a modulation code block and a combination bit are respectively detected from the frame synchronization pattern.
The detected data is combined bit memory (displayed in mb)
52, the shift register 54, the combination bit memory 56, and the shift register 58 are stored in the order of arrangement. Then, the code conversion unit 60 refers to the logical value of each of the three bits on the combined bit memory 56 side of the shift registers 54 and 58 and the logical value of the combined bit of the combined bit memory 56.

In the code conversion section 60, the demodulation processing shown in FIG. 12 is performed, and the logical values of the corresponding bits of the shift registers 54 and 58 are converted. After that, the 14-channel bit data stored in the shift register 58 is supplied to the inverse conversion memory 62, where it is inversely converted to 8-bit data with reference to Table 1 to obtain a demodulated output.

<Effects of the First Embodiment> As described above, according to this embodiment, when two consecutive blocks of the modulation code of 14 channel bits are combined to generate a digital modulation code sequence, one bit of the modulation code is generated. The maximum inversion interval Tmax is limited and the DSV is minimized while the condition of the minimum inversion interval Tmin is satisfied by inserting the coupling bit. Thus, a digital modulator for converting 8-bit data into a digital modulation code of substantially 15 bits and a demodulator for demodulating the digital modulator are realized.

As a result, the minimum inversion interval Tmin = 3 × 8/15 = 1.6T as viewed from the 8-bit data can be realized.
A digital modulation code with DR = 1.6 can be constructed. That is, higher-density recording can be realized than the EFM or 8/16 modulation method shown in the background art.

As the 8/14 bit conversion table, an EFM table used in a CD system can be used. For this reason, the reproduction of the disk using the format adopting the present system and the reproduction of the disk using the format of the CD system can be performed using the common decoding table, and the demodulation device can be configured at lower cost.

<Modification of First Embodiment> Next, the first embodiment will be described.
Some of the modifications will be described. (1) The above embodiment is a case of conversion between 8-bit data and 14-channel bit data, where Tmin = 3, Tmax =
Although the value is 12, these values may be appropriately changed as needed. For example, the following combinations are useful. d = 3, m = 8, n = 17, combination bit = 2, conversion rate = 8/19, Tmin = 4T, DR = 1.68Tb, T
max = 13T d = 4, m = 8, n = 19, combination bit = 3, conversion rate = 8/22, Tmin = 5T, DR = 1.82Tb, T
max = 17T Since data is often processed in 1-byte units, m =
Although it is 8, it may be more or less. n is also 1
Other values such as 8 may be used. Tmax may also be 14T, 15T or the like.

In the above embodiment, the conversion between m-bit digital data and an n (n> m) -bit digital modulation code of Tmax = k + 1 is generally performed by inserting d-1 combined bits. The present invention can be applied to a digital modulation / demodulation for substantially converting between m-bit digital data and (n + d-1) -bit digital modulation code. In the above embodiment, the NRZI is applied, but another method may be used.

(2) In the above embodiment, the present invention is applied to the recording and reproduction of data on a disk. However, the present invention is applied to the case of recording and reproducing data on a recording medium such as another tape or transmitting data. However, this embodiment is applicable. Various design changes can be made to the device configuration so as to achieve the same operation.

* Embodiment 2 * Next, Embodiment 2 will be described. 8 shown in Example 1
In the / 15 modulation scheme, when two consecutive blocks of a 14-bit digital modulation code are combined to generate a digital modulation code sequence, 1-bit combination bits are inserted to satisfy the condition of the minimum inversion interval and Reversal interval limit,
DSV is to be minimized. Thereby, a digital modulation method for substantially converting 8-bit digital data into a 15-bit digital modulation code, specifically, a minimum inversion interval of 3 × 8/15 = 1.6T can be realized, and DR = A digital modulation code of 1.6 can be configured, and higher-density information recording can be realized than EFM or 8/16 modulation.

In the system of the first embodiment, when data of a pattern in which five or more “0” s are continuous before and / or after the connection bit, the pattern before and after the connection bit is selected. By doing so, the DSV can be controlled, but the appearance frequency of such a pattern is not always high.

Generally, in a modulation code having the same DR, it is preferable that the low frequency component of the modulation signal is small in terms of influence on a servo system and data detection. In the second embodiment, DR = 8/15 of the conversion rate shown in the first embodiment is used.
In the digital modulation code of 1.6, DSV controllability is improved by inserting DSV control bits as short as possible to reduce low frequency components.

In this embodiment, a predetermined interval, for example, 1
Five DSV control bits are inserted every 0 bytes. By selecting the pattern of the insertion bit cb as described below, the polarity is inverted or non-inverted after passing through the insertion bit cb (including the case where the inversion is performed twice).
Can be arbitrarily selected, and control is performed so that the DSV value becomes small.

Note that the following description is based on the 8 shown in the first embodiment.
This is an example of application to the / 15 modulation scheme, and it is considered that the insertion of DSV control bits also satisfies d = 2 and k = 11 which are the run length conditions of 8/15 modulation.

<Insertion Pattern Selection Rule 1> FIG.
4 shows a bit pattern according to the present embodiment. According to the first embodiment, since the combined bit mb is inserted every 14 bits, one block of data is represented by 14 bits of b1 to b14.
Bit and a combination bit mb. Further, according to the present embodiment, the insertion bit cb for DSV control is inserted and added at predetermined intervals. By selecting the pattern c1 to c5 of the insertion bit cb, the polarity after the insertion bit is inverted or non-inverted (including the case of two inversions), whereby the DSV value is controlled to be small.

Table 2 shows insertion bit patterns c1 to c5 when the 5-bit insertion bit cb is inserted before the combination bit mb, and conditions for selecting those patterns. Hereinafter, the selection rule 1 of the insertion pattern will be described with reference to Table 2.

[0083]

[Table 2]

(1) When the polarity is inverted by the insertion bit (pattern in [A] of Table 2) When the polarity is inverted by the insertion bit cb, the pattern “00100” in which c3 in the insertion bit is “1” is used. insert. At this time, the subsequent combination bit mb is always “0”.
To Instead, the pattern “00” with c4 set to “1”
010 "may be used.

The pattern “0” shown in Table 2 [A] as described above
Regarding the polarity inversion by “0100” and “00010”, as described in “Description of Conditions” in the table, there is no particular condition for the bit pattern x of the block before and after the insertion bit cb. Inversion is possible.

Consider the minimum inversion interval (d = 2) at this time. First, it is assumed that the pattern “00100” is inserted, and the last channel bit b14 of the previous block and the first channel bit b1 of the subsequent block are both “1”.
On the front side, the upper two bits c1, c2,
Since c2 is "0", the condition of d = 2 is satisfied. For the rear side, the lower two bits c of the insertion bit cb
Since 4, c5 and the combination bit mb are all "0", the condition of d = 2 is similarly satisfied.

On the other hand, when the case of the pattern “00010” is inserted, the upper three bits c1, c2, and c3 of the insertion bit cb are all “0” on the front side, so that the condition of d = 2 is satisfied. On the rear side, since the lower 1 bit c5 of the insertion bit cb and the combination bit mb are both "0", the condition of d = 2 is similarly satisfied.

Next, the maximum inversion interval (k = 11) will be considered. First, the pattern “00100” is inserted, and m =
When an EFM table is used as the m / n conversion table for 8, n = 14, the maximum number of consecutive “0” s in the blocks on both sides is eight. Therefore, on the front side, since the upper two bits c1 and c2 of the insertion bit cb are "0", the number of consecutive "0" is 8 + 2 = 10, which satisfies the condition of k = 11.

On the other hand, when the pattern “00010” is inserted, the number of consecutive “0” becomes 8 + 3 = 11 on the front side,
The condition of k = 11 is satisfied. On the rear side, the continuous number of “0” becomes 1 + 1 + 8 = 10 including the combination bit mb, and the condition of k = 10 is similarly satisfied.

As described above, the 5-bit pattern “0010”
By inserting “0” or “00010” as the insertion bit cb, while satisfying the conditions of d = 2 and k = 11,
The polarity can be reversed.

(2) When the polarity is not inverted by the insertion bit (patterns [B] to [D] in Table 2) Based on the following conditions, all the insertion bits cb are set to “0” or the insertion bit cb And combination bit m
By inverting twice by setting 2 bits out of a total of 6 bits of b to “1”, non-inversion can be achieved as a result. Table 2 shows three types of insertion bit patterns and their conditions when the polarity is not inverted, which are indicated by [B], [C], and [D]. Hereinafter, description will be made in order.

In the case of Table 2 [B], in the bit pattern y of the preceding and succeeding blocks, one of the last two bits b13 and b14 of the previous block is "1", and one of the first two bits b1 and b2 of the subsequent block. Is “1”, the insertion bit cb and the subsequent combined bit mb
Are all “0”.

FIG. 15 shows an example of such a case. (A) in the figure is an example of a pattern corresponding to the condition of Table 2 [B]. On the other hand, when the polarity inversion of Table 2 [A] described above is performed, a pattern as shown in FIG. 15B is obtained. Further, when the polarity non-inversion of Table 2 [B] is performed on FIG. 15A, a pattern as shown in FIG. 15C is obtained. The waveforms after performing the NRZI conversion on the patterns of FIGS. 15B and 15C are shown in FIG.
5 (D) and (E).

In the case of Table 2 [C] If the first two bits b1 and b2 of the rear block are both "0", the insertion bit cb is set to "00100" and the subsequent combined bit mb is set to "1". And In addition,
In this case, there is no particular condition for the pattern x of the previous block.

FIG. 16 shows an example of such a case. FIG. 16A shows an example of a pattern corresponding to the condition of Table 2 [C]. In contrast, Table 2 described above
When the polarity inversion of [A] is performed, a pattern as shown in FIG. 16B is obtained. In addition, FIG.
When the polarity non-inversion of [C] is performed, a pattern as shown in FIG. 16C is obtained. The waveforms after performing NRZI conversion on the patterns of FIGS. 16B and 16C are as shown in FIGS. 16D and 16E, respectively.

In the case of Table 2 [D] When both the last two bits b13 and b14 of the previous block are "0", the insertion bit cb is set to "10010" and the subsequent combined bit mb is set to "0". And In addition,
In this case, there is no particular condition for the pattern x of the subsequent block.

FIG. 17 shows an example of such a case. FIG. 17A shows an example of a pattern corresponding to the condition of Table 2 [D]. In contrast, Table 2 described above
When the polarity inversion of [A] is performed, a pattern as shown in FIG. 17B is obtained. In addition, FIG.
When the polarity non-inversion of [D] is performed, a pattern as shown in FIG. 17C is obtained. FIGS. 17D and 17E show waveforms after performing NRZI conversion on the patterns of FIGS. 17B and 17C, respectively.

The last two bits b13 and b of the previous block
14 are both "0" and the first two bits b of the subsequent block
When both 1 and b2 are "0", [C],
Since any condition of [D] is satisfied, any bit pattern may be used.

Regardless of whether any of these insertions / conversions in Table 2 [B], [C], and [D] is performed, consideration is given to obtain a code pattern satisfying the conditions of d = 2 and k = 11. Yes,
It is the same as Table 2 [A] above. For example, in Table 2 [B],
The number of consecutive “0” is the insertion bit cb and the combination bit mb.
And at least 5 + 1 = 6, and the minimum inversion interval (d =
The condition of 2) is satisfied. Also, from the condition of the bit pattern y of the preceding and following blocks, the number of consecutive “0” is
5 + 1 + 2 = 8 at the maximum, including the combined bit mb, and the condition of the maximum inversion interval (k = 11) is satisfied. Table 2
It is understood that the similar considerations are applied to [C] and [D], and that the conditions of the minimum inversion interval (d = 2) and the maximum inversion interval (k = 11) are satisfied.

<Insertion Pattern Selection Rule 2> Next, the insertion pattern selection rule 2 will be described with reference to Table 3. Table 3 shows insertion bit patterns and other examples of the conditions.

[0101]

[Table 3]

(1) Case of Inverting Polarity by Insertion Bit (Pattern of [A] of Table 3) The rule of the polarity inversion shown in [A] of Table 3 is the same as that of [A] of Table 2 above. The pattern "00100" in which the bit pattern c3 in the insertion bit cb is "1" is inserted, and the subsequent combination bit mb is always "0".

(2) When the polarity is not inverted by the insertion bit (patterns 3 [B] to [F]) Next, when the polarity is not inverted, the insertion bit is set based on the conditions shown in the table. By setting all of the bits cb to "0" or setting two bits of the insertion bit cb and the combination bit mb to "1", the inverted 2
It can be made non-inverted by turning. Table 3 shows the insertion bit patterns and the conditions when the polarity is not inverted.
There are five types shown in [B] to [F]. Hereinafter, description will be made in order.

In the case of Table 3 [B] If the preceding block ends with "1" and either of the first two bits b1 and b2 of the succeeding block is "1", the insertion bit cb and the subsequent combined bit mb is all set to “0”.

In the case of Table 3 [C] If the previous block ends with "1" and the first two bits b1 and b2 of the subsequent block are both "0", the insertion bit c
b is set to “00100”, and the subsequent combined bit m
b is set to “1”.

In the case of Table 3 [D], the last two bits b13 and b14 of the previous block are "10",
If the subsequent block starts with “1”, the insertion bit cb
And all subsequent combination bits are set to “0”.

In the case of Table 3 [E], the last two bits b13 and b14 of the previous block are "10",
If the subsequent block starts with “0”, the insertion bit cb
Is set to “01001” and the subsequent combined bit mb
Is set to “0”.

In the case of Table 3 [F] When the last two bits b13 and b14 of the previous block are "00", the insertion bit cb is set to "10010", and
The subsequent combined bit mb is set to “0”. In this case, there is no particular condition for the pattern x of the subsequent block.

A code pattern satisfying the conditions of d = 2 and k = 11 is obtained by performing any of these insertions / conversions in Tables 3 [B] to [F]. For example, in Table 3 [B],
The number of consecutive “0” is the insertion bit cb and the combination bit mb.
And at least 5 + 1 = 6, and the minimum inversion interval (d =
The condition of 2) is satisfied. Further, from the conditions of the bit patterns of the preceding and succeeding blocks, the maximum number of consecutive “0” s is 5 + 1 + 1 = 7 including the insertion bit cb and the combination bit mb, which satisfies the condition of the maximum inversion interval (k = 11). Table 3
It is understood that the similar considerations are applied to [C] to [F], and that the conditions of the minimum inversion interval (d = 2) and the maximum inversion interval (k = 11) are satisfied.

<Modulation Circuit> Next, a modulation circuit according to the second embodiment will be described with reference to FIG. The 8-bit input data is converted into 14-channel bit data in the modulation table 100 and output to the data selector 102. The data selector 102 is supplied with a frame synchronization pattern from the synchronization pattern output unit 104. At the beginning of each frame, a frame synchronization pattern is selected. Otherwise, 14 channel bit data is selected.

The 14 output from the data selector 102
The channel bit data is loaded into the shift register 106 and subjected to parallel / serial conversion. The converted data is sequentially transferred through the register 106 and the shift register 110. Also, 14-channel bit data is loaded into the lower shift register 112 in FIG. Then, the converted data is sequentially transferred to the register 112 and the shift register 116. Note that the combination bits are stored in the registers 108 and 114.

Next, in the determination / pattern control section 118 for limiting the minimum inversion interval Tmin and the maximum inversion interval Tmax, determining whether the DSV can be controlled, and performing pattern control, the 5 bits after the shift register 106 and the 5 bits before the shift register 110
Bits are referenced, and conversion for limiting Tmin and Tmax is performed from a bit pattern between two blocks sandwiching the combined bit mb (see Embodiment 1). Also, the combination bit mb
If five or more “0s” continue before and after the flag, it is determined that DSV control is possible, and a flag to that effect is set in the shift register 1.
17 and a DSV value comparison circuit 132, which will be described later.
… ”. On the other hand, the shift register 11
2, register 114 and shift register 116 are "... 10
0 [1] 000… ”or“ …… 000 [1] 001… ”.

Next, two insertion bit generation circuits 120,
Reference numeral 122 denotes a circuit for generating the insertion bit pattern shown in Table 2 or Table 3 of the second embodiment. When inserting an insertion bit pattern for DSV control, the switches 124 and 126 are switched to the insertion bit generation circuits 120 and 122 at the timing determined by a timing circuit (not shown). That is, the bit pattern shown in [A] of Table 1 or Table 2 is inserted. The lower shift register 116 has a non-inverted bit pattern according to Table 2 [B] to [D],
Alternatively, a non-inverted bit pattern according to Table 3 [B] to [F] is inserted.

It should be noted that which of the patterns [B] to [D] in Table 2 is selected or which of the patterns [B] to [F] in Table 3 is selected depends on whether the upper shift register 106 or the register 108, and is determined by the determination / pattern control unit 118 according to the input bit pattern from the shift register 110.

Next, in the arithmetic circuits 128 and 130, the D of each code string supplied from the shift registers 110 and 116 is obtained.
The SV is calculated. Then, the determination / pattern control unit 11
8, when it is determined that DSV control is possible, and when an insertion bit pattern for DSV control is inserted, a flag indicating that DSV control is possible is supplied to the shift register 116 and added to the data block. Are compared by the comparison circuit 132, and a flag indicating the smaller one of the DSVs calculated by the calculation circuits 128 and 130 is output to the FIFO 134.

The code sequence of the upper shift register 110 is
The data is sequentially transferred to the shift register 136. The code sequence of the lower shift register 116 is sequentially transferred to the shift register 138 together with the DSV controllable flag. Then, when the DSV controllable flag is indicated to be possible at a position delayed by a predetermined interval at which the insertion bit is inserted, the flag indicated by the output of the FIFO memory 134 selects the lower bit pattern. If it is indicated that the pattern is to be converted, the pattern of the upper shift register 136 is replaced by the pattern of the lower shift register 138 by the pattern converter 140. Then, the bit pattern that has been appropriately replaced is supplied to the NRZI conversion circuit 142, where it is subjected to NRZI conversion and output. The converted signal is recorded on a recording medium such as a disk (see FIG. 19), or transmitted via a communication path.

<Demodulation Circuit> Next, a demodulation circuit according to the second embodiment will be described with reference to FIG. Basically, a process that is the reverse of the conversion process of the modulation method described above may be performed. Since the frame synchronization pattern is added to the signal sequence reproduced or transmitted from the recording medium as described above, a modulation code block, an insertion bit, or a combination bit is recognized by referring to the frame synchronization pattern. .

In the figure, for example, a signal recorded on the disk 150 by the modulation circuit is detected by a detector 152. The detected data is stored in the shift register 15
4, the register 156, the shift register 158, the register 160, and the shift register 162 are sequentially shifted and stored. Registers 156 and 160 have a combined bit m
b is stored. However, during the period of the insertion bit cb, the storage in the shift register is stopped. Therefore, the insertion bit cb is stored in the three shift registers 154, 158, and 162.
Is stored. The insertion bit cb is
Since it is intended only for DSV control, its bit pattern is not directly related to demodulation. Therefore, it is removed from the code sequence.

In the code conversion section 164, the two bits b3 and b1 on the front side of the subsequent block stored in the shift register 154, the combined bit mb stored in the register 156, and the shift register 158 are stored. A total of 5 bits of 2 bits b14 and b12 on the rear side of the central block are input. On the other hand, the code conversion unit 166 has two bits b3 and b1 at the front side of the center block stored in the shift register 158, the combined bit mb stored in the register 160, and the previous bit stored in the shift register 162. A total of 5 bits of 2 bits b14 and b12 on the rear side of the block are input.

The code converters 164 and 166 perform the inverse conversion of the combined bits at the time of modulation and the processing before and after by looking at the input bits. That is, when the combination bit is “1”, the three bits before and after the combination bit are “000 [1] 000”, “001 [] 100”, and when the combination bit is “100 [1]. [] ... ”, and in the case of“… [1] 001 ”, it is converted to“… [] 000 ”.

The central 10 bits of the 14-bit data stored in the shift register 158 and the code conversion unit 16
The two bits before and after the code conversion in 4,166 are supplied to the inverse conversion table 168. Then, the data is demodulated by the inverse conversion table 168. The demodulated 8-bit data is output via the D-flip-flop 170.

<Effects of Second Embodiment> As described above, according to the second embodiment, insertion bits are inserted at predetermined intervals, so that controllability of DSV is improved and low frequency components are reduced. Is done.

<Modification of Second Embodiment> In both the rules of Tables 2 and 3, the insertion bit cb is arranged before the combination bit mb, but the insertion bit cb is arranged after the combination bit mb. Even if they are arranged adjacently, d = 2 and k =
Polarity inversion / non-inversion satisfying the eleventh condition can be realized.

* Third Embodiment * Next, a third embodiment will be described. This embodiment is also similar to the second embodiment. The DSV is controlled by inserting insertion bits at predetermined intervals. In the second embodiment, five insertion bits are used. In the third embodiment, four insertion bits are used. This embodiment is also an example of application to the 8/15 modulation scheme shown in the first embodiment.
15 modulation run length conditions d = 2 and k = 1
1 is considered.

<Insertion Pattern Selection Rule> FIG. 20 shows a bit pattern according to this embodiment. According to the first embodiment, since the combination bit mb is inserted every 14 bits, one block of data is composed of 14 bits b1 to b14 and the combination bit mb. Further, according to the present embodiment, the insertion bit c for DSV control is provided at predetermined intervals.
b is inserted and added. The pattern c of this insertion bit cb
The polarity after the insertion bit is inverted by selecting 1 to c4,
Alternatively, non-inversion (including two inversions) is performed so that the DSV value is controlled to be small.

Table 4 shows insertion bit patterns c1 to c4 when the 4-bit insertion bit cb is inserted before the combination bit mb, and conditions for selecting those patterns. Hereinafter, the selection rule of the insertion pattern will be described with reference to Table 4.

[0127]

[Table 4]

(1) When the polarity is inverted by the insertion bit (pattern of [A] in Table 4) When the polarity is inverted by the insertion bit cb, the pattern “0010” in which c3 in the insertion bit is “1” is used. insert. At this time, the subsequent combination bit mb is always set to “0”.

The pattern “0” shown in Table 4 [A] as described above
Regarding the polarity inversion by "010", as described in "Description of Conditions" in the table, there is no particular condition in the bit pattern of the block before and after the insertion bit cb, and the polarity can always be inverted by inserting this pattern. is there.

Consider the minimum inversion interval (d = 2) at this time. First, it is assumed that the pattern “0010” is inserted, and the last channel bit b14 of the previous block and the first channel bit b1 of the subsequent block are both “1”. For the front side, the upper two bits c1 and c2 of the insertion bit cb
Are “0”, so that the condition of d = 2 is satisfied.
On the rear side, the lower one bit c4,
And the combination bit mb is both “0”, so that the condition of d = 2 is also satisfied.

Next, the maximum inversion interval (k = 11) will be considered. First, a pattern “0010” is inserted, and m = 8,
When an EFM table is used as the m / n conversion table for n = 14, the maximum number of consecutive “0” s in the blocks on both sides is eight. Therefore, on the front side, the upper two bits of the insertion bit cb
Since the bits c1 and c2 are "0", the number of consecutive "0" is 8 + 2 = 10, which satisfies the condition of k = 11.

As described above, the 4-bit pattern "0010"
Is inserted as an insertion bit cb, so that d =
The polarity can be inverted while satisfying the conditions of 2, and k = 11.

(2) When the polarity is not inverted by the insertion bit (patterns [B] to [F] in Table 4) Next, in the case of non-inversion of polarity, based on the conditions shown in the table, a, All of the insertion bits cb are set to "0", b, any two bits out of a total of 5 bits of the insertion bit cb and the combination bit mb are set to "1", c, Any of the insertion bit cb or the combination bit mb Is set to "1", and the third bit from the back of the previous block or the third bit from the front of the subsequent block is set to "1". As a result, non-inversion can be performed by inversion twice. Table 4 shows [B] to [F] in Table 4 as the insertion bit patterns and the conditions when the polarity is not inverted.
There is a street. Hereinafter, description will be made in order.

In the case of Table 4 [B], the last two bits b13 and b14 of the previous block are both "0"
If the first two bits b1 and b2 of the rear block are both "0", the insertion bit cb is set to "1000" and the subsequent combined bit mb is set to "1".

FIG. 21 shows an example of such a case. FIG. 21A shows an example of a pattern corresponding to the condition of Table 4 [B]. In contrast, Table 4 described above
When the polarity inversion of [A] is performed, a pattern as shown in FIG. In addition, FIG.
When the polarity non-inversion of [B] is performed, a pattern as shown in FIG. 21C is obtained. The waveforms after performing NRZI conversion on the patterns of FIGS. 21B and 21C are as shown in FIGS. 21D and 21E, respectively.

In the case of Table 4 [C] If either of the last two bits b13 and b14 of the previous block is "1" and any of the first 5 bits b1 to b5 of the subsequent block is "1", The insertion bit cb and the subsequent combination bit mb are all set to “0”.

FIG. 22 shows an example of such a case. (A) in FIG. 22 is an example of a pattern corresponding to the condition of Table 4 [C]. In contrast, Table 4 described above
When the polarity inversion of [A] is performed, a pattern as shown in FIG. In addition, FIG.
When the polarity non-inversion of [C] is performed, a pattern as shown in FIG. The waveforms after performing the NRZI conversion on the patterns of FIGS. 22B and 22C are as shown in FIGS. 22D and 22E, respectively.

In the case of Table 4 [D] When one of the last 5 bits b10 to b14 of the previous block is "1" and any of the first 2 bits b1 and b2 of the subsequent block is "1" Sets all the insertion bit cb and the subsequent combination bit mb to “0”.

In the case of Table 4 [E] If either of the last two bits b13 and b14 of the previous block is "1" and the first five bits b1 to b5 of the subsequent block are both "0", Set the insertion bit cb to “000
In addition to "0", the subsequent combined bit mb and the third bit b3 from the front of the subsequent block are set to "1".

FIG. 23 shows an example of such a case. FIG. 23A shows an example of a pattern corresponding to the condition of Table 4 [E]. In contrast, Table 4 described above
When the polarity inversion of [A] is performed, a pattern as shown in FIG. In addition, FIG.
When the polarity non-inversion of [E] is performed, a pattern as shown in FIG. FIGS. 23D and 23E show waveforms after performing NRZI conversion on the patterns of FIGS. 23B and 23C, respectively.

In the case of Table 4 [F], the last 5 bits b10 to b14 of the previous block are all "0"
And if either of the first two bits b1 and b2 of the subsequent block is "1", the insertion bit cb is set to "1000".
And the subsequent combined bit mb is set to "0", and the third bit b12 from the back of the previous block is set to "1".

FIG. 24 shows an example of such a case. FIG. 24A shows an example of a pattern corresponding to the condition of Table 4 [F]. In contrast, Table 4 described above
When the polarity inversion of [A] is performed, a pattern as shown in FIG. In addition, FIG.
When the polarity non-inversion of [F] is performed, a pattern as shown in FIG. FIGS. 24D and 24E show waveforms after performing NRZI conversion on the patterns of FIGS. 24B and 24C, respectively.

It is considered that a code pattern satisfying the conditions of d = 2 and k = 11 can be obtained by performing any of the insertions / conversions of [B] to [F]. Is the same as

<Modulation Circuit> Next, a modulation circuit according to the third embodiment will be described. The circuit configuration is the same as that of the second embodiment, and is as shown in FIG. However, in the case of the present embodiment, the insertion bit patterns shown in Table 4 are generated in the insertion bit generation circuits 120 and 122. When inserting an insertion bit pattern for DSV control, the switch 12 is turned on at a timing determined by a timing circuit (not shown).
4 and 126 are switched to the insertion bit generation circuits 120 and 122, and the inverted pattern, that is, the bit pattern shown in [A] of Table 4 is inserted into the upper shift register 110. In the lower shift register 116, Table 4 [B]
To [F] are inserted.
Which of the patterns [B] to [F] in Table 4 is selected is determined by the determination / pattern control unit 118 in accordance with the bit patterns input from the upper shift register 106, the register 108, and the shift register 110. Other parts are the same as in the second embodiment.

<Demodulation Processing Method> Next, a demodulation processing method when there is an insertion bit will be described with reference to FIG. Basically, a process that is the reverse of the conversion process of the modulation method described above may be performed. As described above, insertion bits are inserted at predetermined intervals, for example, every 10 bytes. The demodulation process on the combined bits with the inserted bits inserted is performed as shown in FIG. 25, and the demodulation process on the combined bits without the inserted bits is the same as in the first embodiment, and is performed as shown in FIG. FIG.
Only the first step 200 is different from FIG. Hereinafter, the demodulation processing of FIG. 25 will be described.

In the part where the insertion bit mb is adjacent to the combination bit cb in the code sequence, the combination bit mb
And the exclusive OR (E) of c1 of the insertion bits cb
X-OR) is performed (FIG. 25, step S20).
0), and a demodulation process reverse to the modulation process is performed based on the result. In other words, the bit pattern of the insertion bit cb and the combination bit mb in Table 4 is determined so that such processing can be performed.

(1) In the case of Table 4 [A], [C], [D] In these cases, c1 = mb = “0” and (mb)
EXOR (c1) = "0". Therefore, the modulation codes of the preceding block and the succeeding block are inversely transformed by the 14 → 8 conversion table and demodulated (N, N in step S200).
S52).

(2) Case of Table 4 [B] In this case, c1 = mb = “1”, and similarly, (m
b) EXOR (c1) = "0". Therefore, in this case as well,
The modulation code of the previous block and the rear block is 14 →
8 and demodulated (N, N in step S200).
S52).

(3) In the case of Table 4 [E] and [F] In either case, since either c1 or mb is “1”, (mb) EXOR (c1) = “1” (Y in step S200). That is, when the logical value of the previous block or the subsequent block has not been changed by the conversion side at the time of insertion bit insertion, that is, in the case of [A] to [D] in Table 4, E
XOR becomes “0”. However, when any one of the logical values has been changed, that is, in the case of [E] and [F] in Table 4, EXOR is “1”.

In the case of Table 4 [E], the connection block mb
Since the three bits b12, b13, b14 before are not "100" (N in step S54), it is determined whether the three bits b2, b3, b4 after the combined block mb are "001" (step S58). If it is Y, b3 is converted to "0" (step S60), and then inversely converted from 14 to 8 (step S52). In the case of Table 4 [F], if the previous block is "100", b12 is converted to "0" (step S56), and then converted back to 14 → 8 (step S5).
2).

In Example 3, Table 4 shows that
Although there is no process corresponding to step 62, the process of step 62 is performed on a block that does not include an insertion bit.

<Demodulation Circuit> Next, the demodulation circuit will be described with reference to FIG. As compared with the demodulation circuit of the second embodiment (FIG. 19), only the shift register 200, the switch 202, and the EXOR circuit 204 are different.

In the figure, the detection data output from the detector 152 is
6, the data is sequentially shifted and stored in the shift register 158, the register 160, and the shift register 162. However, during the period of the insertion bit cb, the insertion bit cb is stored in the shift register 200, and the storage in the shift register 154 is stopped. Therefore, the registers 154 to 162 store only the data from which the insertion bit cb has been removed.

In order to execute the processing of step S200 shown in FIG. 25, the switch 202 is switched to the shift register 200 when the combined bit mb following the insertion bit cb is obtained at the output of the detector 152. .
As a result, mb and c1 are input to the EXOR circuit 204, and (mb) EXOR (c1) operation is performed. And
The obtained EXOR value is shifted to the shift register 154. As a result, the demodulation processing based on the logical value of the combination bit mb stored in the registers 156 and 160 performs the same code conversion for the normal combination bit and the combination bit following the insertion bit. It becomes possible. That is, with reference to the logical value of the combination bit mb, Table 4 (E),
Processing opposite to that of (F) is performed.

<Modification of Embodiment 3> In Table 4, the insertion bit cb is arranged before the combined bit mb. However, the insertion bit cb may be arranged adjacent to the rear side of the combined bit mb. Similarly, polarity reversal / non-reversal satisfying the conditions of d = 2 and k = 11 can be realized.

<Comparison of Embodiments 2 and 3> In order to control the DSV while satisfying the conditions of the minimum inversion interval and the maximum inversion interval, the degree of freedom of control increases as the number of inserted bits increases. However, an unnecessarily large number of bits only increases redundancy. In the second embodiment, since the insertion bits are 5 bits, the condition of the minimum inversion interval is easily satisfied.
There is no need to change the logical values of the preceding and following blocks. On the other hand,
In the third embodiment, since the insertion bits are 4 bits, it is necessary to change the logical values of the blocks before and after to satisfy the condition of the minimum inversion interval. However, the third embodiment is superior from the viewpoint of redundancy.

[0157]

As described above, according to the present invention, the following effects can be obtained. (1) According to the present invention according to claims 1 to 10,
Discuss m-bit digital data between logical values of “1”.
The theoretical value "0" indicates the minimum inversion interval d to the maximum inversion interval
Satisfies the inversion interval condition including up to k (k> d)
And convert it into n (n> m) channel bits, and convert
Later, a connection bit is set between two consecutive n-channel bits.
When the equivalent is inserted and connected, the above-mentioned inversion interval condition is satisfied.
When performing modulation and encoding in such a manner,
Bits to reduce the number of combined bits.
Thus, high-density coding can be achieved. Change
In addition, even if the number of combined bits is reduced, the modulation code block
Multiple inversions, which can reduce the inversion interval.
It is possible to control DSV by shortening it.
You. Along with the modulation and coding described above, a method of manufacturing a recording medium
Recording medium, digital demodulation method and digital demodulator are also on top
There is an effect accompanying the note.

(2) Further, according to claims 11 to 21,
According to the present invention, m-bit digital data is
The logical value “0” indicates the minimum inversion interval d between the logical values “1”.
Included within k (k> d) indicating the maximum reversal interval
N (n> m) channel bits by satisfying the inversion interval condition
Conversion using the conversion table, and continuous after conversion
A state in which connection bits are inserted and connected between n channel bits
While satisfying the reversal interval condition and taking DSV into consideration.
When modulating and encoding from
And insert a predetermined number of bits for DSV control.
Prepare a plurality of input bits and combine bits between n channel bits.
At a predetermined interval of the code sequence connected by inserting
Combines one insertion bit selected from the insertion bits
By inserting more adjacent to the bit,
Run length (d = 2,
k = 11) while keeping the number of bits as small as possible
Of the insertion bit and the combination bit
Or selection of non-inversion (including twice inversion)
This enables DSV control in this area,
This can improve the number component. With the above modulation and coding,
Therefore, the digital demodulation method and digital demodulator
There is an effect accompanying.

[0159]

[0160]

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a modulation processing method according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a modulation processing method according to the first embodiment.

FIG. 3 is a diagram illustrating a modulation processing method according to the first embodiment.

FIG. 4 is a diagram illustrating a modulation processing method according to the first embodiment.

FIG. 5 is a diagram illustrating a maximum inversion interval according to the first embodiment.

FIG. 6 is a diagram illustrating a modulation processing method according to the first embodiment.

FIG. 7 is a diagram illustrating a modulation processing method according to the first embodiment.

FIG. 8 is a diagram illustrating a modulation processing method according to the first embodiment.

FIG. 9 is a diagram illustrating an example of a frame synchronization pattern according to the first embodiment.

FIG. 10 is a flowchart illustrating a modulation process according to the first embodiment.

FIG. 11 is a block diagram illustrating a main part of a disk recording device to which the modulation device according to the first embodiment is applied.

FIG. 12 is a flowchart illustrating a demodulation process according to the first embodiment.

FIG. 13 is a block diagram illustrating a main part of a disc reproducing apparatus to which the demodulating device according to the first embodiment is applied.

FIG. 14 illustrates a code sequence according to the second embodiment.

FIG. 15 is a diagram illustrating a modulation processing method according to the second embodiment.

FIG. 16 is a diagram illustrating a modulation processing method according to the second embodiment.

FIG. 17 is a diagram illustrating a modulation processing method according to the second embodiment.

FIG. 18 is a block diagram illustrating a modulation circuit according to a second embodiment.

FIG. 19 is a block diagram illustrating a demodulation circuit according to a second embodiment.

FIG. 20 is a diagram illustrating a code sequence according to a third embodiment.

FIG. 21 is a diagram illustrating a modulation processing method according to a third embodiment.

FIG. 22 is a diagram illustrating a modulation processing method according to a third embodiment.

FIG. 23 is a diagram illustrating a modulation processing method according to the third embodiment.

FIG. 24 is a diagram illustrating a modulation processing method according to the third embodiment.

FIG. 25 is a flowchart illustrating a demodulation process according to the third embodiment.

FIG. 26 is a block diagram illustrating a demodulation circuit according to a third embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Conversion ROM (data conversion means) 12, 14 ... Register (conversion data storage means) 16 ... Synchronization code output part (synchronization pattern generation means) 18 ... Selector (synchronization pattern addition means) 20 ... Memory (code sequence generation means) 22: Combined bit processing unit (code sequence generation unit) 24: Pointer register (modulation processing unit) 26: DSV calculation & code determination unit (modulation processing unit) 28: Address counter (modulation processing unit) 30: Parallel / serial conversion 32 ... NRZI conversion unit 34 optical modulator drive circuit 36 disk (recording medium) 38 light source 40 optical modulator 42 projection optical system 50 detector (data detecting means) 52, 56 coupled bit memory (detection data storage) Means) 54, 58: shift register (detection data storage means) 60: code conversion unit (demodulation processing means) 62: inverse conversion memo (Inverse data transformation unit) 100 ... table 102 ... data selector 104 ... sync pattern output unit 106,110,112,116,136,138,1
54, 158, 162, 200 shift register 108, 114, 156, 160 register 118 decision / pattern control unit 120, 122 insertion bit generation circuit 124, 126, 202 switch 128, 130 DSV calculation unit 132 Comparison section 134 FIFO memory 140 Pattern conversion section 142 NRZI conversion section 150 Disk 152 Detector 164, 166 Code conversion section 168 Inverse conversion table 170 D-flip-flop 204 EXOR circuit B1, B2, B3 ... modulation code block cb ... insertion bits mb ... combination bits

Continuation of the front page (56) References JP-A-58-220214 (JP, A) JP-A-58-220214 (JP, A) JP-A-6-139708 (JP, A) JP-A-62-272726 (JP) JP-A-63-13425 (JP, A) JP-A-6-197024 (JP, A) JP-A-6-311042 (JP, A) JP-A-7-245565 (JP, A) (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 7/14

Claims (21)

(57) [Claims] 1. An m-bit digital data is read from d data whose logical value “0” indicates the minimum inversion interval between logical values “1”.
K number indicating the maximum inversion interval (k> d) within inverted between that Mase including
Convert to n (n> m) channel bits by satisfying the interval condition
And between two consecutive n-channel bits after conversion
With the coupling bit inserted and connected to the
Digital modulation method that modulates and codes to satisfy the condition
In the law, to set the coupling bits to d-1 bits, and, wherein when any one bit before and after the coupling bit is "1", these together with a "0", either in the coupling bits a first modulation process step of "1";"0" on one side either before or after the coupling bits d +
Continuously for one or more, if the other side of the "0" continues 2d + 1 or more, and wherein when both before and after the coupling bits "0" 2d + 1 consecutive, either in the coupling bits “1” and “0” is 2d + 1
Digital modulation method comprising: second modulation processing step of "1" and d + 1 bit from the coupling bit of the modulation code block consecutive FOB. 2. The method according to claim 1, wherein the m bits of digital data are converted from d data whose logical value “0” indicates the minimum inversion interval between the logical values “1”.
Inversion between up to k (k> d) indicating the maximum inversion interval
Convert to n (n> m) channel bits by satisfying the interval condition
And between two consecutive n-channel bits after conversion
With the coupling bit inserted and connected to the
Digital modulator that modulates and codes to satisfy the condition
In location, set the coupling bits to d-1 bits, and, wherein when any one bit before and after the coupling bit is "1", these together with a "0", either in the coupling bits first modulation processing means to "1";"0" on either one side of the front and rear of the coupling bits is d +
Continuously for one or more, if the other side of the "0" continues 2d + 1 or more, and wherein when both before and after the coupling bits "0" 2d + 1 consecutive, either in bonds bits " with a 1 "from the coupled bit modulation code blocks consecutive" 0 "2d + 1 or more d +
A second modulation processing means for setting the first bit to "1"; 3. The method according to claim 1, wherein the m-bit digital data is converted from d data whose logical value “0” indicates the minimum inversion interval between the logical values “1”.
Inversion between up to k (k> d) indicating the maximum inversion interval
Convert to n (n> m) channel bits by satisfying the interval condition
And between two consecutive n-channel bits after conversion
With the coupling bit inserted and connected to the
Satisfies the condition and modulates and encodes considering DSV
In the digital modulation method, the combination bit is set to d-1 bits, and
If both bits before and after the bit are “1”,
Are set to “0”, and any of the
A first modulation processing step of setting “1” to “1”; “0” is d +
One or more consecutive “0” s on the other side 2d + 1 or more consecutive
And before and after the combined bit
When 2d + 1 “0” s are consecutive, the combined bit
Is set to “1” and “0” is 2d + 1
From the combination bits of the modulation code block
Consider DSV for one or both of the (d + 1) th bits.
A third modulation processing step that takes into account "1" . 4. An m-bit digital data having a logical value
From "d" logical values "0" indicating the minimum inversion interval between "1"
Inversion between up to k (k> d) indicating the maximum inversion interval
Convert to n (n> m) channel bits by satisfying the interval condition
And between two consecutive n-channel bits after conversion
With the coupling bit inserted and connected to the
Satisfies the condition and modulates and encodes considering DSV
In the digital modulator, the combination bit is set to d-1 bits, and
If both bits before and after the bit are “1”,
Are set to “0”, and any of the
First modulation processing means for setting “1” to “1”; “0” is d + on either side before or after the combined bit
One or more consecutive “0” s on the other side 2d + 1 or more consecutive
If it continues, and, also Re Izu before and after the coupling bits
When 2d + 1 “0” s are consecutive, the combined bit
Is set to “1” and “0” is 2d + 1
From the combination bits of the modulation code block
Consider DSV for one or both of the (d + 1) th bits.
A digital modulation device comprising : a third modulation processing unit that sets “1” in consideration . 5. m = 8, n = 14, d = 2, k = 11
Yes, m bits of digital data are converted to n channel bits
When converting to, based on the conversion table used for EFM
4. The digital conversion according to claim 1, wherein the data conversion is performed by
Tuning method. 6. When m = 8, n = 14, d = 2, k = 11,
Yes, m bits of digital data are converted to n channel bits
When converting to, based on the conversion table used for EFM
5. The digital converter according to claim 2, wherein data conversion is performed by using
Control device. Step of recording data onto a recording medium based on the recording signal thus obtained; 7. to obtain a recording signal based on the digital data modulated by the digital modulation method according to claim 1 or 3, wherein And a method for producing a recording medium. 8. A method for manufacturing a recording medium according to claim 7, wherein
Recording medium on which digital data is recorded . 9. A digital modulation method according to claim 1, wherein
Combining bits of a digital signal modulated by
Refer to the logical value of the data of the modulation code block before and after it.
Performs the demodulation process opposite to the modulation process,
Demodulation processing step of obtaining a digital modulation code of n bits ;
Inverse conversion of modulation code to original m-bit digital data
A digital demodulation method. 10. Digital modulation according to claim 1 or 3.
Combined bits of digital signal modulated by method
And the logical value of the data of the modulation code block before and after it.
And performs a demodulation process that is the reverse of the modulation process to obtain n channels.
Demodulation processing means for obtaining a digital modulation code of n bits ;
Inverse conversion of modulation code to original m-bit digital data
Digital demodulation apparatus provided with; inverse data transformation unit for. 11. An m-bit digital data is logically
Is the logical value "0" between the values "1" the d number indicating the minimum inversion interval?
Up to k (k> d) indicating the maximum inversion interval
Converts to n (n> m) channel bits by satisfying the interval condition
Convert using the table and n consecutive
With connecting bits inserted between channel bits and connected
The change is satisfied while satisfying the inversion interval condition and considering the DSV.
In a digital modulation method for performing modulation and coding, a combination bit is set to d-1 bits, and DSV control is performed.
A plurality of insertion bits having a predetermined number of bits are prepared for use, and the connection bits are inserted and connected between n channel bits.
At a predetermined interval of the encoded code sequence,
One of the insertion bits selected from the
A switch that controls DSV by touching and inserting further
Digital modulation method including steps. 12. m = 8, n = 14, d = 2, k = 11
And said insertion bit is 5 bits.
12. The digital modulation method according to item 11. 13. The method according to claim 13, wherein the polarity is reversed in said step.
In the case of making the connection bits
If one of the bit and the third bit is set to “1” and the polarity is not inverted, the insertion bit and the combination
Set all bits to "0" or any two bits
13. The digital modulation method according to claim 12, wherein “1” is set to “1”. 14. m = 8, n = 14, d = 2, k = 11
And said insertion bit is 4 bits.
12. The digital modulation method according to item 11. 15. In the step, the polarity is inverted.
To add the second bit from the combination bit in the insertion bits
Is set to “1”, and if the polarity is not inverted,
Set all to "0" or any two bits to "1"
Either, or, any one bit and is set to "1"
In both cases, the third or last block from the back of the previous block
15. The method according to claim 14, wherein the third bit from before the lock is "1".
Digital modulation method. 16. The method according to claim 16, wherein in the step, the polarity is not inverted.
Select the bit pattern to insert the insertion bit
Logical value of the last two bits of the block before the combined bit
A request to make a decision based on the logical value of the previous two bits of the subsequent block
13. The digital modulation method according to claim 12. 17. An m-bit digital data is logically
Is the logical value "0" between the values "1" the d number indicating the minimum inversion interval?
Up to k (k> d) indicating the maximum inversion interval
Converts to n (n> m) channel bits by satisfying the interval condition
Convert using the table and n consecutive
With connecting bits inserted between channel bits and connected
The change is satisfied while satisfying the inversion interval condition and considering the DSV.
In a digital modulation device that performs modulation and encoding, a combination bit is set to d-1 bits, and DSV control is performed.
A plurality of insertion bits having a predetermined number of bits are prepared for use, and the connection bits are inserted and connected between n channel bits.
At a predetermined interval of the encoded code sequence,
One of the insertion bits selected from the
Hand to control DSV by touching and inserting further
Digital modulator with steps. 18. The method of claim 11, 12, 13, 14, 1.
The digital modulation method according to any one of 5, or 16,
A demodulation method for a modulated code, comprising: the insertion bit, the combination bit, and modulation before and after the insertion bit, the combination bit,
The modulation processing is performed with reference to the logical value of the data of the code block.
Performing an inverse demodulation process; converting an n-bit modulation code to m-bit digital data
Obtain demodulated data using the inverse conversion table for conversion
Digital demodulation method comprising: a step that. 19. A digital demodulation method according to claim 18,
A digital demodulator for performing the modulation, the modulation of the insertion bits, the combination bits, and modulations before and after the combination bits.
The modulation processing is performed with reference to the logical value of the data of the code block.
Reverse modulation code of n bits into digital data of m bits; means for performing physical and inverse demodulation processing
Convert the demodulated data using the inverse conversion table
Means for obtaining a digital demodulation device. 20. A digital demodulation method according to claim 18,
A is, an exclusive OR of the insertion bit and the coupling bits, its
Refer to the logical value of the data of the modulation code block before and after
Performing a demodulation process reverse to the modulation process; converting an n-bit modulation code into m-bit digital data.
Obtain demodulated data using the inverse conversion table for conversion
Digital demodulation method comprising: a step that. 21. A digital demodulation method according to claim 18,
A digital demodulation device for performing an exclusive OR operation of the combined bit and the insertion bit,
Refer to the logical value of the data of the modulation code block before and after
Means for performing demodulation processing opposite to the modulation processing; and converting an n-bit modulation code to m-bit digital data.
Convert the demodulated data using the inverse conversion table
Means for obtaining a digital demodulation device.