KR0185944B1 - Method for coding using (1, 7) encoded code - Google Patents

Abstract

The present invention relates to a decoding method using the (1,7) modulated code and an apparatus thereof. In the (overlapping) decoding method according to the present invention, a first step of converting codewords transmitted serially into blocks of 6-bit units and shifting them by 3 bits and outputting them is performed. And a second step of generating a decoded word by overlapping the current blocks, and a third step of selecting and outputting one of the decoded words generated by the overlapped step through the second step. As described above, the present invention has an effect of increasing decoding efficiency by minimizing an error propagation problem, which is the maximum difficulty of the (1,7) modulation code.

Description

(1,7) Decoding method using modulated code and apparatus therefor

1 is a block diagram showing a decoder according to the present invention,

2 is a detailed configuration diagram of the control unit 16 in FIG.

3 is a conceptual diagram for explaining the operation of the present invention.

* Explanation of symbols for main parts of the drawings

10: S / P converter 12,14: lookup table

16,24 control unit 18 inverter

20, 26: multiplexer 22: delay

The present invention relates to the decoding of a digital signal, and in particular, it is possible to minimize error propagation by performing overlapping decoding by shifting the codewords encoded by (1,7) modulated code by 6 bits. 1,7) The present invention relates to a decoding method using a modulated code and an apparatus thereof.

In general, in order to record a digital signal on a storage medium such as a magnetic tape, a hard disk, or an optical disk, 'RLL (Run Length Limited)' modulation is performed. The RLL modulation method is to encode m-bit data so as to satisfy the (d, k) condition in converting n-bit codewords. Here, d and k represent the minimum and maximum number of '0' existing between two consecutive '1', respectively.

In this RLL modulation method, the recording density ratio DR is defined as follows.

In order to increase the recording density ratio, the coding rate (m / n) may be increased or d may be increased. On the other hand, in order to accurately detect the signal modulated by the RLL modulation method in the demodulator, the signal detection window width of the modulation code must be large. When the bit interval of the original data is T, the detection window width Tw is given as follows.

Since the detection window width of the signal is proportional to the code rate (m / n), the closer the code rate is to '1', the more effective. In this case, an integer n, m that satisfies the condition (d, k) increases.

As such, the RLL modulation code may be characterized as (d, k, m, n), and the RLL modulation code may be referred to as '(d, k) modulation code'.

Current commercially widely used RLL modulation codes include EFM (Eight Fourteen Modulation) codes in which (d, k, m, n) is (2,10,8,14). The EFM modulated code is a code proposed by Philips and is used in the current compact disc system. However, since the EFM modulation code requires an additional 3 bits of merging bit to control the digital sum value (DSV), the coding rate is reduced to 8/17. In addition, it is judged that the EFM modulation code is not suitable for a high-density recording system that requires a real-time processing due to the large size of the codebook for modulation and demodulation.

The RLL modulated code also includes (2,7) modulated code with (d, k, m, n) of (2,7,1,2) and (1,7) with (1,7,2,3). Modulation codes; (2,7) modulation codes and (1,7) modulation codes are now widely used in magnetic recording and optical recording media.

Table 1 and Table 2 below show the basic code table and additional code table used for encoding (1,7) modulation code among the above-described modulation codes.

TABLE 1

TABLE 2

The decoding table by the (1,7) modulation code corresponds to the inverse of the basic sign table and the additional sign table in Tables 1 and 2 described above, and Table 3 shows the decoding rules by the (1,7) modulation code. .

Table 3 (Next Chapter)

In Table 3, 'N' represents a Don't Care condition, and 'x' represents a case where at least one '1' exists.

As can be seen from Table 3, if an error occurs in the last bit of the previous code when decoding data using the (1,7) modulated code, it affects the decoding of the current code and the next code. As such, the (1,7) modulation code had a problem of propagating an error.

TABLE 3

An object of the present invention for solving the above-described problems is to minimize error propagation by using an overlapping decoding method when decoding data encoded by a (1,7) modulation code. And 7) a decoding method using a modulation code.

Another object of the present invention is to provide a decoder that implements the above-described method.

The decoding method using the (1,7) modulation code according to the present invention for achieving the above object, adds the data encoded by the (1,7) modulation code and the basic decoding table of the (1,7) modulation code In the decoding method using a decode table, the first step of converting the codeword transmitted serially into a block of 6-bit units, shifted by 3 bits to output, Decoding the blocks shifted by the 3 bits input, And a second step of generating a decoded word by overlapping the previous block and the current blocks, and a third step of selecting and outputting one of the decoded words generated by the overlapped value through the second step.

A decoder for achieving another object of the present invention is an apparatus for decoding data encoded by a (1,7) modulation code using a basic decoding table and an additional decoding table of a (1,7) modulation code. A serial / parallel converter converts a codeword transmitted to a block into 6-bit units and shifts it by 3 bits for output, and decodes 6-bit unit data shifted by 3 bits from the serial / parallel converter. A decoder, a delayer for delaying and outputting a decoded word outputted from the decoder by a predetermined time, a current decoded word outputted from the decoder, a previous decoded word outputted from the delayer, and an input terminal of which one side is grounded. A first multiplexer for selecting and outputting one of the generated data according to the control of the first controller; and receiving the current decoded word and the previous decoded word; A first controller for generating a selection control signal supplied to the first multiplexer.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 shows the configuration of a decoder according to the present invention. First, the decoder of FIG. 1 includes an S / P (Serial / Parallel) converter 10 for converting codewords input in a serial form into parallel data of a predetermined bit. In the S / P converter 10, first and second look up tables (LUT1, LUT2) 12 and 14, which store decoded words based on a basic decoding table and an additional decoding table, respectively, are arranged in parallel. Connected. A first multiplexer (MUX1) 20 for selectively outputting one of the decoded words output from the lookup tables 12 and 14 is connected to the first and second lookup tables 12 and 14. .

The S / P converter 10 receives a predetermined bit of parallel data and selects one of the lookup tables 12 and 14 and one of the input data of the first multiplexer 20. The first control unit 16 for generating (cntl) is connected. 1 shows a selection control signal cntl between the first controller 16 and the first lookup table 12 to supply different selection control signals cntl to the lookup tables 12 and 14. The inverting inverter 18 is connected.

In the decoder of FIG. 1, the first multiplexer 20 is connected with a delay 22 for delaying and outputting a decoded word for a predetermined time. The first multiplexer 20 and the delayer 22 have a second multiplexer MUX2 for selectively outputting one of the decoded words applied from these components and data generated from an input terminal of which one side is grounded. 26) is connected. The first multiplexer 20 and the retarder 22 are also connected to a second control unit 24 which receives these output data and generates a selection control signal to be supplied to the second multiplexer 26.

On the other hand, Figure 2 shows a detailed configuration of the first control unit 16 in the present invention as described above. The first controller 16 is composed of a negative logic gate (NOR gate) that receives a lower 3 bits C ₃ C ₄ C ₅ of the parallel data applied from the S / P converter 10 and performs a logical operation.

Referring to Figure 3 the operation of the present invention configured as described above is as follows.

3 is a diagram for explaining overlap decoding according to the present invention.

First, in the decoder of FIG. 1, the S / P converter 10 receives codewords transmitted serially and converts the codewords into 6-bit parallel data. The S / P converter 10 shifts 6-bit data by 3 bits and applies them to the first and second lookup tables 12 and 14. The first and second lookup tables 12 and 14 are memories that store decoded words corresponding to a basic decoding table and an additional decoding table, respectively, and a decoded word is output from one of them. The operation of selecting one of the first and second lookup tables 12 and 14 is performed from the first controller 16. In other words, the first controller 16 receives the 6-bit parallel data (C = C ₀ C ₁ C ₂ C ₃ C ₄ C ₅ ) output from the S / P converter 10 to negate the lower 3 bits. The logical sum operation generates the selection control signal cntl.

cntl = (C ₃ + C ₄ + C ₅ ) '

As shown in Table 2 and Table 3, if all of the following subwords are '0', the decoded word should be obtained using the additional decoding table. The control unit 16 generates the selection control signal cntl of the high level value '1', which negates and logically combines the respective binary bit values when the lower three bits are all '0'. At this time, the selection control signal cntl of the low level value '0' is input to the first lookup table 12, and the selection control signal of the high level value '1' is input to the second lookup table 14. cntl) is entered. That is, the first controller 16 selects the second lookup table 14 to which the selection control signal cntl of the high level value '1' is input. The second lookup table 14 outputs a decoded word corresponding to a code word received from the S / P converter 10. At this time, the second lookup table 12 outputs an error flag signal indicating whether an error has occurred in the currently output decoded word together with the decoded word. The second lookup table 14 applies the output data to the input terminal '1' of the first multiplexer 20. Meanwhile, the selection control signal cntl of the first controller 16 is also input to the first multiplexer 20, and when the selection control signal cntl is a high level value '1', the first multiplexer 20 Data from the second lookup table 14 input to the input terminal '1' are selected and output.

On the other hand, when at least one of the lower 3 bits of the parallel data has '1', the first controller 16 generates the selection control signal cntl of the low level value '0'. In this case, the first lookup table 12 to which the selection control signal cntl of the high level value '1' is input is selected. The first lookup table 12 outputs a decoded word corresponding to an input codeword and an error flag signal corresponding to the decoded word and applies it to the input terminal '0' of the first multiplexer 20. In this case, the first multiplexer 20 selects and outputs data input to the input terminal '0'.

The delay unit 22 receives the decoded word and the error flag signal selectively output from the first multiplexer 20, and delays one decoded word, that is, two bits. Meanwhile, while delaying the decoded word in the delayer 22, the next codeword is decoded through the same process described above.

The second multiplexer 26 receives a decoded word currently output from the first multiplexer 20 and a previous decoded word stored in the delay unit 22 and receives one of them from the second control unit 24. Select and output according to.

Referring to Tables 1 and 2 described above, there are cases where a decoded word exists or does not exist. The second control unit 24 generates a selection control signal based on the rule to be described below. The decoded word obtained from the currently input codeword (C ₃ C ₄ C ₅ , C ₁₀ C ₁₁ C ₁₂ ) is called r _n (r ₁₀ ˜r ₁₃ ), and the previous code words (C ₀ C ₁ C ₂ , When the decoded word obtained from C ₃ C ₄ C ₅ ) is r _p (r ₀ to r ₃ ), the selection rule for the two decoded words is as follows.

Case 1: select r _n if r _p does not exist

Case 2: If r _n does not exist, select r _p

Case 3: If r _p and r _n are equal, select r _n

Case 4: If r _p and r _n are not equal, select r _n

Case 5: select '00' if both r _p and r _n do not exist

Case 1 and Case 2 are cases where the sign and the decode table of the current block and the previous block are different from each other. That is, when encoding, a codeword is obtained using a basic code table, and when decoding, a codeword is obtained by using an additional decoding table or vice versa. That is, when the error flag signal applied from the delayer 22 is the high level value '1', the second controller 24 determines that the previous decoder does not exist. At this time, if the error flag signal received from the first multiplexer 20 is a low level value ('0'), the second controller 24 determines that the current decoded word does not generate an error (case 1). A selection control signal for selecting the current decoder r _n is generated. At this time, the second multiplexer 26 outputs a decoder r _n input to the input terminal '01'.

On the other hand, if the error flag signal from the first multiplexer 20 is the high level value ('1') and the error flag signal from the delay unit 22 is the low level value ('0') (case 2), The second controller 24 generates a selection control signal for selecting the previous decoder r _p . The second multiplexer 26 receives the selection control signal from the second controller 24 and outputs a decoder r _p input to the input terminal '10'.

On the other hand, the same decoded word may be obtained when the code table and the decode table are different. Case 3 is an example. In Table 2, '0' and '2' are encoded according to the basic sign table, and when decoding, a decoded word is obtained according to an additional decoding table. . Here, since the decoded words for the two codewords are the same, any one may be selected. In order to simplify the selection condition, the second control unit 24 generates a selection control signal to select the current decoded word r _n . At this time, the second multiplexer 26 outputs a decoder r _n input to the input terminal '01'.

Case 4 is the case opposite to case 3 described above, in which '1' or '3' is encoded in the additional code table of Table 2. When the codeword is decoded using the basic decoding table, a completely different result is obtained. At this time, the second controller 24 generates a selection control signal for selecting the decoded word r _n obtained by using the additional decoding table, and the second multiplexer 26 receives the selection control signal and receives the input terminal '01. Outputs a decoded word r _n input as'.

Finally, since case 5 is an error, a random value is selected. The second controller 24 selects the input terminal '00' to the second multiplexer 26 when the error flag signals from the first multiplexer 20 and the delayer 22 are both high level values '1'. Generates and supplies a selection control signal. The second multiplexer 26 outputs data '00' from the input terminal '00' at this time.

As described above, the decoding method using the (1,7) modulation code and the apparatus according to the present invention, when decoding the data encoded by the (1,7) modulation code, the two obtained from the current block and the previous block by overlapping decoding Select one of the decryptors. Therefore, the present invention has the effect of increasing the decoding efficiency by minimizing the error propagation problem, which is the maximum difficulty of the (1,7) modulation code.

Claims (14)

A method of decoding data encoded by a (1,7) modulation code using a basic decoding table and an additional decoding table of a (1,7) modulation code, wherein the codewords transmitted in series are converted into blocks of 6-bit units. A first step of converting and outputting by shifting by 3 bits; A second step of decoding the input blocks shifted by 3 bits and generating a decoded word by overlapping the previous block and the current blocks; And a third step of selecting and outputting one decoded word from among the decoded words generated by overlapping through the second step. The method of claim 1, wherein the second step is to generate a decoded word by the additional decoding table when the lower 3 bits are all '0' in the 6-bit data shifted by 3 bits. 1,7) Decoding method using a modulated code. The decoding method according to claim 1, wherein the third step selects a decoded word in the current block when there is no decoded word in the previous block. The decoding method according to claim 1, wherein the third step selects a decoded word in the previous block when there is no decoded word in the current block. The decoding method according to claim 1, wherein the third step selects a decoded word in the current block when the decoded word in the previous block and the current block is the same. The decoding method according to claim 1, wherein the third step selects a decoded word in the current block when the decoded word in the previous block and the current block is not the same. . The decoding method according to claim 1, wherein the third step generates a decoded word '00' when neither the decoded word in the previous block nor the current block exists. . An apparatus for decoding data encoded by a (1,7) modulation code using a basic decoding table and an additional decoding table of a (1.7) modulation code, wherein the codewords transmitted in serial are converted into blocks of 6-bit units. A serial / parallel converter for shifting and outputting each of the three bits; A decoder which decodes 6-bit data input by being shifted by 3 bits from the serial / parallel converter; A delayer for delaying a decoded word output from the decoder for a predetermined time and outputting the delayed word; A first multiplexer which selects and outputs one of a current decoded word output from the decoder, a previous decoded word output from the delay unit, and data generated from an input terminal of which one side is grounded under the control of the first controller; And a first control unit which receives the current decoded word and the previous decoded word and generates a selection control signal to be supplied to the first multiplexer. The apparatus of claim 8, wherein the decoding unit comprises: a first memory configured to store a decoded word corresponding to the basic decoding table; A second memory for storing a decoded word corresponding to the additional decode table; A second multiplexer for selecting and outputting one of the decoded words outputted from the memories under the control of a second controller; And a second controller controlling the memories and the second multiplexer to select a decoded word output from the second memory when all lower 3 bits of the 6-bit data received from the serial / parallel converter are '0'. A decoder using a (1,7) modulation code, characterized in that the control unit. 9. The method of claim 8, wherein the first control unit generates a selection control signal for selecting a decoded word output from the decoding unit when there is no decoded word from the delay unit (1, 7). Decoder using modulation code. The method of claim 8, wherein the first controller generates a selection control signal for selecting a decoded word output from the delay unit when there is no decoded word output from the decoder (1,7) Decoder using modulated code. 10. The method of claim 8, wherein the second controller generates a selection control signal for selecting a decoded word output from the decoder when the delayer and the decoded word from the decoder are the same (1, 7). Decoder using modulation code. 9. The method of claim 8, wherein the second controller generates a selection control signal for selecting a decoded word from the decoder when the delayed word and the decoded word from the decoder are not the same (1, 7). Decoder using modulation code. 10. The apparatus of claim 8, wherein the second control unit generates a selection control signal for selecting data '00' generated from an input terminal of which one side is grounded when neither the delay word nor the decoded word from the decoding unit exists. A decoder using a (1,7) modulated code, characterized in that.