JP2004220766A - Modulation method, modulation device, demodulation method, demodulation device, information recording medium, information transmitting method and device, - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide such a device that after a data group of continuous binary is converted to input data word in a unit of 4 bits, it can be converted to an output codeword train in a unit of 6 bits satisfying a RLL rule of either of a (1, 7) RLL rule or k=8 or more to 12 or less, also DSV control can be performed without adding a redundant bit to the output codeword train, and a DC component of the output codeword train can be suppressed effectively. <P>SOLUTION: Suppressing a DC component under limitation of k=7 or 8 is performed by using a encoding table in which an input data word in a unit of 4 bits can be converted to an input data word in a unit of 6 bits with (1, k) RLL rule without using redundant bits. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a modulation method, a modulation device, a demodulation method, a demodulation device, an information recording medium, an information transmission method, and an information transmission device. In particular, the present invention relates to a method for converting a digital information signal into (1, k) run-length limited (hereinafter, "( 1, k) RLL), and a digital information signal is recorded on a storage medium such as an optical disk or a magnetic disk by a recording code sequence having any restriction of k = 7 or more and 12 or less. , K) Modulate, demodulate, record, and transmit an information code sequence having a limit of any of k = 7 or more and 12 or less in a run length limited (hereinafter, referred to as “(1, k) RLL”) limit. TECHNICAL FIELD The present invention relates to a modulation method, a modulation device, a demodulation method, a demodulation device, an information recording medium, an information transmission method, and an information transmission device suitable for performing the above.

  2. Description of the Related Art Conventionally, (1,7) RLL has been often used as a recording modulation method for recording a series of digital information signals on a recording medium such as an optical disk or a magnetic disk. However, in the conventional (1,7) RLL, it is difficult to suppress a signal component near a direct current (DC), and a large DC component is generated depending on a bit pattern. For example, a spectrum of an information signal component is generated in a servo signal band. Is expected to cause a problem that adversely affects the servo performance.

  On the other hand, Japanese Patent Application Laid-Open No. 6-195887 discloses a "recording code modulation apparatus" in which a DC component is suppressed by preventing repetition of a specific bit pattern. In Japanese Patent Application Laid-Open No. 10-340543, “encoding device, decoding device, encoding method, and decoding method”, suppression of DC components is performed by inserting redundant bits so as not to disturb the (1, 7) RLL rule. Suggestions have been made for this.

  Alternatively, according to Japanese Patent Application Laid-Open No. 2000-105981, “Data Conversion Method and Apparatus”, the maximum run length is calculated using 8/12 modulation according to the (1,8) RLL rule, and the number of code words is reduced as compared with the (1,7) RLL rule. There is a proposal that a margin is provided for the DC component suppression control.

  According to Japanese Patent Application Laid-Open No. 6-195887, although repetition of a specific pattern can be reduced by means such as bit inversion and randomization, it is difficult to sufficiently suppress a DC component. According to Japanese Patent Laid-Open No. Hei 10-340543, although the suppression of the DC component is larger than that of the former, the recording capacity is reduced due to the insertion of the redundant bits. According to Japanese Patent Application Laid-Open No. 2000-105981, although the DC component can be suppressed without redundant bits, there is a problem that a plurality of 12-bit coding tables are required and the coding rule is complicated.

  The present invention has been made in view of the above problems, and suppresses the DC component under any of the restrictions of k = 7 to 12 under the (1, k) RLL rule without using redundant bits. This is intended to be achieved by using an encoding table capable of converting 4 bits to 6 bits.

  Means for Solving the Problems The present invention comprises the following means 1) to 7).

That is,
1) When converting an input data word in N-times (N is a positive integer) unit of 4 bits into an output codeword in N-times (N is a positive integer) unit of 6 bits, Refer to a plurality of encoding tables including each of the output codewords corresponding to each input data word and encoding table designation information for designating an encoding table used to encode the next input data word. Each of the output codewords is directly and sequentially combined as a binary output codeword sequence, and an output that satisfies any one of 7 or more and 12 or less according to the (1, k) RLL (Run Length Limited) rule. A modulation method for outputting as a codeword,
The plurality of encoding tables include at least a first and a second encoding table, and a first output codeword on the first encoding table corresponding to a predetermined input data word, After the NRZI-modulated signals of the data word and the second output code word on the second encoding table corresponding to the same input data word have opposite polarities, and after outputting a specific output code word, Regardless of which of the first and second output codewords is selected, the selected output codeword is an output codeword that satisfies any one of 7 or more and 12 or less according to the (1, k) RLL rule. ,
A selecting unit for selecting one of the first and second output codewords,
It is detected that the output codeword corresponding to the input data word specified by the coding table specification information is any of the first and second output codewords, and based on the detection result, the first and second output codewords are detected. Output encoding table designation information to specify any of the encoding table to the plurality of encoding tables,
An output code word sequentially output in correspondence with an input data word by using a specified encoding table from among the plurality of encoding tables is stored separately for each polarity of the output code word. DSV (digital sum variation) obtained by sequentially adding a CDS (codeword digital sum) corresponding to an output codeword stored in the output codeword memory means for each output codeword sequentially output from the conversion table. ) Is accumulated, and an output codeword sequence is selected and sequentially output based on the magnitude of the accumulated DSV absolute value.
2) a conversion means for encoding an input data word in N-times (N is a positive integer) unit of 4 bits into an output codeword in N-times (N is a positive integer) unit of 6 bits; Has a plurality of encoding tables for encoding the input data words into the output code words, respectively, and each of the encoding tables has the output code words corresponding to the input data words. And encoding table designation information for designating an encoding table used to encode the next input data word, wherein each of the output code words is sequentially directly combined as a binary output code word sequence. A modulator for outputting as an output codeword satisfying any one of 7 or more and 12 or less in a (1, k) RLL (Run Length Limited) rule,
The plurality of encoding tables include at least first and second encoding tables, and a first output codeword on the first encoding table corresponding to a predetermined input data word; The signals obtained by NRZI-modulating the word and the second output codeword on the second encoding table corresponding to the same input data word have opposite polarities, and after outputting a specific output codeword, Regardless of which of the first and second output codewords is selected, the selected output codeword is an output codeword that satisfies any one of 7 or more and 12 or less in the (1, k) RLL rule. A modulator comprising a selecting means for selecting one of the first and second output codewords, wherein the output codeword corresponding to the input data word specified by the coding table specifying information is the second codeword. 1, any of the second output codewords And an encoding table designating means for outputting encoding table designation information for designating one of the first and second encoding tables to the plurality of encoding tables based on the detection result. An output code word memory for sorting and storing output code words sequentially output in correspondence with an input data word for each polarity of the output code word using an encoding table designated from among the plurality of encoding tables; Means and a CDS (codeword digital sum) corresponding to an output codeword stored in said output codeword memory means are sequentially added for each output codeword sequentially output from a designated encoding table. DSV memory means for storing a DSV (Digital Sum Variation), and the absolute value of the DSV output from the DSV memory means, A modulator for selecting an output codeword sequence sequentially output from the output codeword memory.
3) A demodulation method for demodulating a code word sequence obtained by serializing code words in N-times (N is a positive integer) unit of 6 bits encoded using the modulation method described in 1) into a reproduction data sequence. So,
The codeword sequence is reconstructed into codewords every N times of 6 bits (N is a positive integer), and a subsequent codeword is encoded in any one of the plurality of encoding tables. A demodulation method for demodulating the codeword sequence into a reproduction data sequence based on determination information indicating whether the codeword sequence is followed by a subsequent codeword.
4) A demodulation device that demodulates a code word sequence obtained by serializing code words in N-times (N is a positive integer) unit of 6 bits encoded using the modulation device described in 2) into a reproduction data sequence. So,
Means for reconstructing the codeword string into codewords every N times 6 bits (N is a positive integer), and a method in which a subsequent codeword is encoded in any one of the plurality of encoding tables. A demodulation device, comprising: means for demodulating the code word sequence into a reproduced data sequence based on determination information indicating whether the decoding is performed and a subsequent code word.
5) An information recording medium characterized by recording at least a part of a codeword encoded using the modulation device according to 2).
6) An information transmission method characterized by performing information transmission using a codeword encoded using the modulation method described in 1) as transmission information.
7) An information transmission apparatus, which performs information transmission using a codeword encoded using the modulation apparatus according to 2) as transmission information.

  As described above, according to the present invention, after converting a continuous binary data sequence into an input data word in units of 4 bits, the (1,7) RLL rule or any RLL of k = 8 to 12 is used. It is possible to convert to a 6-bit output codeword string that satisfies the rules and to perform DSV control without adding redundant bits to the output codeword string. There is an advantage that it is possible to provide a modulation device capable of performing the above-mentioned suppression and a demodulation device thereof.

  Hereinafter, an embodiment relating to modulation of the present invention will be described with reference to FIGS. FIG. 1 is a basic configuration diagram of the modulation device of the present invention, FIG. 2 is a block configuration diagram of the modulation device of the present invention, FIG. 3 is a block configuration diagram around the encoding unit shown in FIG. 2, and FIG. FIG. 5 is a flowchart for explaining an encoding operation of the apparatus, FIG. 5 is a flowchart for explaining DSV control for satisfying the RLL (1, 7) rule by the modulator of the present invention, and FIG. 6 is an RLL by the modulator of the present invention. 9 is a flowchart for explaining DSV control for satisfying the (1, 8) rule. FIG. 8 is a diagram showing the contents of four encoding tables “S (k) = 0” to “S (k) = 3” used in the modulation device of the present invention, where S (k) is the state of the table. , D (k) are input data words, and C (k) is an output code word, expressed in decimal and binary. S (k + 1) is a state indicating the next table.

  Now, the types of output codewords in 6-bit units that satisfy the (1,7) RLL or (1,8) RLL restriction are as shown in FIG. As an example of an encoding table based on the codeword type, four encoding tables (encoding table numbers S (k) = “0” to “3”) as shown in FIG. 8 can be configured. S (k) = “0” to S (k) = “3” represent coding table selection numbers respectively assigned to the four coding tables. Further, S (k + 1) in FIG. 8 represents a coding table selection number for selecting a coding table used for performing the next coding. Note that the allocation of the data word D (k) and the code word C (k) can be changed so as not to disturb the coding rule and not to hinder demodulation. For example, the encoding table shown in FIG. 15 has an arrangement in which the data word D (k) and the code word C (k) in the table of FIG. The assignment to the word C (k) can be rearranged so as not to disturb the coding rule, and the present invention is effective even if the embodiment of the present invention is not limited to the configuration of the coding table in FIG.

  Also, while satisfying the DSV control rule according to the present invention, a data word composed of an integer multiple of 4 is converted into a code bit of an integer multiple of 6 so that, for example, an 8-bit data word is assigned to 12 code word bits. The configuration of the encoding table to be converted can be easily analogized from the present invention, and it is clear that the encoding table is included in the present invention.

  First, the modulation device 1 of the present invention will be described with reference to FIG. A digital information signal obtained by converting an image, a sound, and the like to be modulated into a binary sequence by a discretizing means (not shown) is subjected to so-called formatting such as addition of an error correction code and structuring of a sector by a formatting unit 11. A source code sequence for each bit is added to the 4-6 modulator 12.

  The 4-6 modulator 12 performs an encoding process described later using the encoding table 13 shown in FIG. 8 as an example, adds a predetermined synchronizing word, and then performs an NRZI conversion by an NRZI conversion circuit 14 to perform a recording signal. And transmitted to the recording drive circuit 15, recorded on the recording medium 2 or subjected to transmission encoding by the transmission encoding means 31, and transmitted to the transmission medium 3.

  FIG. 2 is a block diagram showing a configuration example for describing the operation of the 4-6 modulator 12 of FIG. 1 in more detail. The input data word (source code) D (k) is applied to a code word option presence / absence detection circuit 121, a coding table address calculation unit 122, and a synchronization word generation unit 123, respectively. The codeword option presence / absence detection circuit 121 detects whether there is a codeword candidate having a different DSV polarity using D (k) and state S (k). An encoding table address operation is performed based on this detection result and D (k), and encoding candidates are set to C (k) 0 and C (k) 1 from a plurality of encoding tables 13, and the former is a code word memory “0”. 124, sends the latter to codeword memory "1" 125.

  A DSV operation memory “0” 126 and a DSV operation memory “1” 127 are connected to the code word memory “0” 124 and the code word memory “1” 125, and code words C (k) 0 and C (k) 1 are stored. Each time it is input to the code word memory “0” 124 and the code word memory “1” 125, the CDS is calculated and the stored DSV value is updated. Here, when the code word option presence / absence detection circuit 121 detects a source code D (k) having an option, the source code D (k) is stored in the DSV memory “0” 126 and the DSV memory “1” 127 by the absolute value comparison unit 128. The absolute values of existing DSVs are compared, and the memory control unit 129 selects a codeword stored in a codeword memory having a small absolute value of the DSV, externally outputs the codeword as an output codeword, and selects an unselected codeword memory. The contents of the memory are replaced with the contents of the selected code word memory and DSV operation memory.

  FIG. 3 is a diagram showing in detail the periphery of the encoding table of FIG. 2, and FIG. 4 is a flowchart showing the details described above in detail. In this description, the case where the code word memory is set to two and the output code word is immediately output when the code word option presence / absence detection circuit 121 detects D (k) having an option has been described. The number of memories is not limited to two. When D (k) having a choice is detected, it is not necessary to output an output code word immediately, and it has several memories and has selectable source code. The present invention is also effective in a method of selecting and outputting a codeword string with the smallest DSV by looking at some of the above. In FIG. 3, a maximum run length setting 130 is a means for outputting a control signal for limiting (1,7) RLL or limiting k to 8 or more to a codeword option presence / absence detection circuit. Details of the operation will be described later. In FIG. 7, the minimum run repetition detection 131 is a means for monitoring the number of repetitions of the shortest inversion, and details of the operation will be described later.

  Next, a case where the 4-bit input data word D (k) is encoded by the (1,7) RLL restriction will be specifically described with reference to FIG. As the input data words D (k), D (k +), "4, 5, 6, 7, 8 (decimal)" is used as an example. In the initial state of encoding, the initial selection number of the encoding table is determined by an operation such as insertion of a synchronization word whose description is omitted. For example, the encoding table S (k) = "0" is selected. When an input data word D (k) = 4 is input to this coding table S (k) = "0", an output code word C (k) = 18 (decimal) is output. The selection number S (k + 1) = "1" is selected. Next, when an input data word D (k) = 5 is input to the selected encoding table S (k) = “1”, an output code word C (k) = 2 (decimal) is output. The next coding table selection number S (k + 1) = "2" is selected. Similarly, when the input data word D (k) = 6 is input to the coding table S (k) = "2", the output code word C (k) = 18 is output, and the coding table selection number S (k + 1) is output. ) = “3” is selected, and when the input data word D (k) = 7 is input to the encoding table S (k) = “3”, the output code word C (k) = 21 is output and the code When the conversion table selection number S (k + 1) = "0" is selected and the input data word D (k) = 8 is input to the coding table S (k) = "0", the output code word C (k) = 21 is output, and the coding table selection number S (k + 1) = "1" is selected.

As a result, "4, 5, 6, 7, 8 (decimal)" is input as the input data word D (k) and "010010, 000010, 010010, 010101, 010101 (binary)" is output as the output codeword C (k). And output sequentially. Therefore, a series of output codeword strings in which the above five output codewords C (k) are directly combined in sequence is:
0100100000100100100101010101101
Thus, an output codeword string that satisfies the limitation of (1,7) RLL can be obtained.

  In this example, the source code having the option does not appear, but as described above, the modulation device shown in FIGS. 1 to 3 uses the encoding table shown in FIG. (1,7) RLL restriction by (k) and S (k) obtained by delaying S (k + 1) output when the immediately preceding codeword is output by one word (4-bit length in source code). Can be obtained by sequentially and directly combining codeword strings satisfying the following.

  Next, the operation of the codeword option presence / absence detection circuit 121 will be described in detail with reference to FIG. FIG. 5 is a flowchart showing the operation performed by the option presence / absence calculation circuit 121 in the case of (1, 7) RLL in FIG. Looking at the condition 1 in step 201, the zero run on the LSB side of the code word C (k-1) that was previously encoded is detected and the result is 4 (Yes in step 201), that is, the code in FIG. In the conversion table, when C (k-1) is 010000 in binary, S (k) = 3, and when D (k) is 0 to 3 (condition 1-1, Yes in step 202), C Select a codeword from the table of S (k) = 3 as (k) 0, select a codeword of S (k) = 1 as C (k) 1, and detect the presence / absence of the detection signal of “there is an option”. Output from the circuit 121 (step 206). When S (k) = 2 and D (k) is 7 or more (condition 1-2, Yes in step 203), a codeword is selected from the table of S (k) = 2 as C (k) 0. , C (k) 1 is selected as the codeword of S (k) = 1, and a detection signal indicating “there is an option” is output from the option presence / absence detection circuit 121 (step 207). If No in Step 201, Step 202, and Step 203, respectively, C (k) 0 and C (k) 1 are both codewords "no choice" selected by D (k) and S (k) (Step 08) The determination is terminated.

  Similarly, in condition 2 (step 204), when the zero run on the LSB side of C (k-1) is 5, or in condition 3 (step 205), the zero run on the LSB side of C (k-1) is 1 or 2 Also at the time of, it is detected whether or not there is an option by the determination according to the flowchart of FIG.

  Looking at the condition 2 in step 204, the zero run on the LSB side of the code word C (k-1) that was previously coded is detected, and if the result is 5 (Yes in step 204), that is, the code in FIG. When C (k-1) is 100,000 in binary in the conversion table, S (k) = 3, and when D (k) is 0 to 1 (condition 2-1; Yes in step 209), C Select a codeword from the table of S (k) = 3 as (k) 0, select a codeword of S (k) = 1 as C (k) 1, and detect the presence / absence of the detection signal of “there is an option”. Output from the circuit 121 (step 210). When S (k) = 2 and D (k) is 10 or more (condition 2-2, Yes in step 211), a codeword is selected from the table of S (k) = 2 as C (k) 0. , C (k) 1 is selected as a codeword of S (k) = 1, and a detection signal indicating “there is an option” is output from the option presence / absence detection circuit 121 (step 212). If No in Steps 204, 209, and 211, respectively, C (k) 0 and C (k) 1 are both codewords “No choice” selected by D (k) and S (k) (Step 208). The determination is terminated.

  Looking at the condition 3 of step 205, if the zero run on the LSB side of the code word C (k-1) that was previously coded is detected and it is 1 or 2 (Yes in step 205), that is, FIG. When C (k-1) is 010010, 010100, 000010, 000100, 001010, 100100, 101010 or 100010 in binary in the encoding table, S (k) = 2 and D (k) is 0 to 1 In the case of (Yes in step 213), a codeword is selected from the table of S (k) = 2 as C (k) 0, and a codeword of S (k) = 0 is selected as C (k) 1. A detection signal indicating "there is an option" is output from the option presence / absence detection circuit 121 (step 214). If No in Steps 205 and 213, respectively, both C (k) 0 and C (k) 1 are Dk) and the codeword selected in S (k) is "no choice" (Step 208), and the process ends. .

  Regarding the condition 4 in step 215, zero run on the LSB side of the code word C (k-1) that has been encoded immediately before is detected, and if it is 1 (Yes in step 215), 10010, 000010, When 001010, 101010, or 100010, S (k) = 2 and D (k) is 12 or 13, ie, 101010 in binary (Yes in step 216), the MSB (most significant) of the next connected codeword If the bit is 1 (Yes in step 217), a codeword of S (k) = 2 is selected as C (k) 0, and a codeword of S (k) = 0 is selected as C (k) 1. Then, a detection signal indicating that "there is an option" is output from the option presence / absence detection circuit 121 (step 218). If No in Steps 215, 216 and 217, respectively, C (k) 0 and C (k) 1 are both codewords “No choice” selected by D (k) and S (k) (Step 208) The determination is terminated.

  By the way, if C (k-1) is 010000 and S (k) = 3 and D (k) is 3 or less, it can be exchanged with a code word of S (k) = 1 It is evident that the sequence of 0s falls into 7 and does not disturb the (1,7) RLL rule, and when C (k-1) is 010000, the next codeword to be taken is S (k) = 2 or 3 is limited by the encoding table 13 and the codewords included in the encoding table 13 with S (k) of 1, 2, 3 are independent of each other. There is no problem during decoding because the same codeword does not exist.

  Similarly, when C (k-1) is 100000, that is, when the zero run on the LSB side is 5, the (1,7) RLL rule is not similarly disturbed, and there is no problem in decoding.

  The codeword whose zero run on the LSB side of C (k−1) is 1 or 2 is the next codeword that takes S (k) = 1 or 2 or 3, and is included in the coding table of S (k) = 0. The same codeword as the codeword included in S (k) = 2 or 3 exists. However, among the code words of S (k) = 0, 000001, which is a code word of D (k) = 0 or 1, is a unique code word that does not exist in another table, and a code of S (k) = 2. Exchange with the word does not cause a problem in decoding.

  Similarly, the codeword whose zero-run on the LSB side of C (k-1) is 1 is the next codeword that takes S (k) = 1 or 2 or 3, and the coding table of S (k) = 0 The same codeword as the codeword included in S (k) = 2 or 3 exists. However, among the codewords of S (k) = 0, 000000, which is a codeword of D (k) = 12 or 13, is a unique codeword that does not exist in another table, and is the most significant codeword of the next codeword. If the bit is 1, k = 7 can be maintained, and there is no problem in decoding even if the code word is exchanged with S (k) = 2.

  As described above, the fact that DSV can be controlled by exchanging codewords in accordance with FIG. 5 can be explained by the fact that the evenness and oddness of 1 included in the exchanged codewords are different. That is, if C (k-1) is 010000, S (k) = 3, and D (k) = 0, C (k) 0 is 101001 and C (k) 1 is 000001. Assuming that the polarity immediately before the NRZI conversion is 1, the former is 001111 and the last bit is 1, so it is 0, while the latter is 111000 and the last bit is 1, so it is 1. FIG. 10 shows this state. a) is the former and b) is the latter. The upper part is C (k-1), C (k), C (k + 1), and the lower part is a codeword after NRZI conversion. As is clear from FIG. 10, by exchanging C (k), the polarity after NRZI conversion changes and the DSV value changes. Therefore, the DC component can be suppressed by selecting a pattern that reduces the DSV.

  Next, a modulation method of a codeword having the (1,8) RLL restriction will be described with reference to FIG. Whether the (1,7) RLL or the (1,8) RLL is determined by the maximum run length setting 130 in FIG. 3 or is determined from the initial setting. Further, as the encoding table in the case of (1, 8) RLL, the same encoding table as (1, 7) RLL in FIG. 8 can be used.

Now, in the case of (1, 8) RLL, the maximum run length is relaxed by one bit longer than (1, 7) RLL, so that the conditions differ from those in FIG. In FIG. 6, in condition 1, when the zero run on the LSB side of C (k-1) is 4 or 5 (in the case of Yes in step 301), the table of S (k) = 3 is selected, and D (k) is selected. Is 0 to 3 (condition 1-1, Yes in step 302), codeword of S (k) = 3 in C (k) 0 and code of S (k) = 1 in C (k) 1 A word can be selected (step 303). Further, when the zero run on the LSB side is 4 or 5 (Yes in step 301), the table of S (k) = 2 is selected and D (k) is 7 or more (condition 1-2, step If Yes in 304), a codeword of S (k) = 2 can be selected for C (k) 0 and a codeword of S (k) = 1 can be selected for C (k) 1 (step 305). If No in Step 301, Step 302, and Step 304, respectively, C (k) 0 and C (k) 1 are both codewords “No choice” selected in D (k) and S (k) (Step 306
) And the determination is terminated.

  Similarly, in condition 2, when the zero run on the LSB side of C (k-1) is 1 (Yes in step 307), if S (k) = 2 is selected, then D (k) = 12 or 13 If (Yes in step 308), a codeword of S (k) = 2 can be selected for C (k) 0 and a codeword of S (k) = 0 can be selected for C (k) 1. (Step 309). If the determinations in Step 307 and Step 308 are No, respectively, both C (k) 0 and C (k) 1 are determined as codewords “no choice” (Step 306) selected by D (k) and S (k). finish.

  In condition 3, when the zero run on the LSB side of C (k-1) is 3 or less (Yes in step 310), when S (k) = 2 and D (k) is 0 or 1 (step 311). In the case of Yes), a codeword of S (k) = 2 can be selected for C (k) 0 and a codeword of S (k) = 0 can be selected for C (k) 1 (step 312). If the determinations in Step 310 and Step 311 are No, respectively, it is determined that both C (k) 0 and C (k) 1 are the codewords “no choice” (Step 306) selected by D (k) and S (k). finish.

  In condition 4, when the zero run on the LSB side of C (k-1) is 2 (Yes in step 313), when S (k) = 2 and D (k) is 12 or 13 (Yes in step 314). Field), if the MSB of the next selected codeword is 1 (Yes in step 315), S (k) = 2 for C (k) 0 and S for C (k) 1 A codeword with (k) = 0 can be selected (step 316). If any of Steps 313, 314, and 315 is No, C (k) 0 and C (k) 1 are both codewords selected with D (k) and S (k) as "no choice" (Step 306). The judgment ends.

  As described above, according to the condition determination in FIG. 6, it is possible to generate a codeword in which the DC component satisfying the (1, 8) RLL rule is suppressed.

  In the case of the encoding of the RLL rule of k = 9, the case where zero run is 6 is added to the judgment of step 301, and when k = 9 is satisfied, steps 303 and 305 are executed. Further, the determination in step 315 becomes unnecessary, and the codeword of S (k) = 2 for C (k) 0 and S (k) = 0 for C (k) 1 in any case of the next codeword. Can be selected.

  In the case of the encoding of the RLL rule of k = 10, the case where the zero run is 6 is added to the judgment of the step 301 in FIG. 6, and further, in the step 313, the case where the zero run is 3 becomes possible. It becomes unnecessary, and the codeword of S (k) = 2 can be selected for C (k) 0 and the codeword of S (k) = 0 can be selected for C (k) 1 in any case of the next codeword. Become.

  If k = 11, furthermore, in step 313, the selection can be made even when the zero run is 4, so that the determination in step 315 becomes unnecessary, and in any case of the next codeword, C (k) 0 is set to S (k) 0. A codeword of (k) = 2 and a codeword of S (k) = 0 can be selected for C (k) 1.

  If k = 12, furthermore, in step 313, the selection can be made even when the zero run is 5, so that the determination in step 315 becomes unnecessary, and in any case of the next codeword, C (k) 0 is set to S (k) 0. A codeword of (k) = 2 and a codeword of S (k) = 0 can be selected for C (k) 1.

  As described above, a modulation method capable of generating a code having a (1,7) RLL limit or any RLL limit of k = 8 or more and 12 or less by using the encoding table according to the present invention, or A modulation device can be realized.

  Based on the DSV control described above, a modulation method or a modulation device for converting a 4-bit data word into a 6-bit code word includes a plurality of selectable bit patterns in advance. For example, an 8-bit data word is converted into a 12-bit code word. It is easy to construct a coding table for converting a code word or a data word consisting of bits of an integral multiple of 4 into a code word consisting of an integer multiple of 6, and is included in the present invention.

  Next, a description will be given of the DSV control method based on the above-described codeword selection with reference to FIGS. In the explanation, the modulation process of (1,7) RLL shown in FIG. 5 is used. However, as shown in FIG. 6, whether any of the RLL-limited code words of k = 8 or more and 12 or less has an option as shown in FIG. By making the determination, the DSV control can be similarly performed.

  First, in FIG. 4, the initial table setting (step 101) can be set by determining the subsequent S (k) such as a synchronization word added to the code word. Next, a 4-bit source code D (k) is input (step 102), and encoding is performed using S (k) and D (k) according to the encoding table in FIG. In this process, the LSB side zero-run length is calculated by looking at C (k-1) that was coded immediately before, and it is determined whether there is a code word option according to the conditions of FIG. 5 (step 103). In FIG. 2 and FIG. 3, C (k-1) is input from the code output means, but it can also be obtained by holding the previous input data and the state S (k).

  If there is no selectable codeword in the encoding table ("No" in step 103), the codeword output from the encoding table is stored in the codeword memory "0" 124 and the codeword memory "1" 125 as C ( k) 0 and C (k) 1 (step 107) are added to the code word memory “0” 124 and the code word memory “1” 125, respectively, to calculate the CDS, and update the DSV memory 126 and the DSV memory 127 ( Step 108).

  If there is a selectable codeword in the encoding table ("Yes" in step 103), a signal indicating the presence of an option is output from the codeword option presence / absence detection circuit 121, and the absolute value of the DSV memories 0 and 1 is output. Is calculated by the absolute value calculation circuit, and a code sequence having a small absolute value is output from the code word memory from the output means (step 104). Thereafter, the contents of the code word memory not selected are replaced with the selected code word sequence, and at the same time, the value not adopted is replaced with the value adopted by the DSV operation memory (step 105). Thereafter, as described in the description of FIGS. 5 and 6, a codeword that can be selected as a codeword candidate is selected from one of the encoding tables determined by S (k) and the other encoding table, and C is selected. (K) 0, and output as C (k) 1 (step 106). After that, the codewords output from the coding table in the codeword memory “0” 124 and the codeword memory “1” 125 are set as C (k) 0 and C (k) 1 (step 107) <codeword candidate C ( k) The CDS is calculated for each of 0 and C (k) 1, the DSV memories “0” and “1” are updated, and the codeword memories “0” and “1” are stored in C (k) 0 and C (k). 1 is added, and the DSV memory 126 and the DSV memory 127 are updated (step 108).

  By performing the above operations until the end of the encoding (step 109), the generation of the code word in which the DC component is suppressed is ended.

  Next, the bit operation according to the present invention when the inversion of the shortest bit continues will be described. Inversion of the shortest bit may make it difficult to perform phase synchronization when the frequency characteristic of the transmission line is low.For such a transmission line, in the present invention, it is possible to prevent continuous shortest bit inversion by means described below. It is possible.

  According to the encoding table of FIG. 8, the continuation of the shortest bit inversion is generated by repetition of 010101 or 101010. The repetition of 010101 occurs when D (k) = 7 continues after S (k) = 0 or S (k) = 3. At this time, after S (k) = 0 and D (k) = 7 by the minimum run repetition count, for example, when D (k + 1) = 7 and D (k + 2) = 7, D (k + 1) = 13 select. Since this codeword is originally a codeword of S (k + 2) = 3, after C (k + 1) = 000000, the codeword of S (k) = 1 is selected by selecting a codeword of S (k) = 1 so as not to disturb the RLL rule. Can be detected and decoded.

  For example, when k = 9 to 12, S (k) = 0, and after D (k) = 7, for example, when D (k + 1) = 7 and D (k + 2) = 7, D (k + 1) = 13 (C (k) = 000000) and outputs S (k + 2) = 1. At this time, since D (k + 2) is 7, C (k + 2) = 4, that is, 00100 is output in binary. At the time of decoding, after detecting 000000, when 000100 is detected, it is recognized that codeword replacement due to the repetition limit of the minimum run has occurred, and both D (k + 1) and D (k + 2) can be decoded normally. . When k = 8, for example, D (k + 2) can be changed to any one of 10 to 15 and similarly decoded.

  Now, in the case of repetition of 101010, when S (k) = 2 and D (k) = 12, the code word is 101010 and S (k + 1) = 2, and when D (k + 1) = 12, the codeword is Words are 101010, S (k + 2) = 2, and D (k + 2) = 12, and 101010 codewords are output. In this case, by changing S (k + 1) to 0, 101010 can be exchanged for 000000, and demodulation can be performed without any problem by the demodulation method described later. As described above, according to the present invention, it is possible to prevent repetition of minimum inversion.

  The above operation will be described again with reference to FIG. The minimum run repetition monitor 131 counts the repetition of D (k) and S (k) in which the minimum inversion repeats while monitoring S (k) and D (k) (minimum run repetition count). This information is sent to the codeword option presence / absence detection circuit, and the repetition of the minimum run is prevented by the above-described means.

  Further, a maximum run length setting 130 is connected to the code word option presence / absence detection circuit, and either the setting of the maximum run, that is, the modulation of (1, 7) RLL, or any one of k = 8 or more and 12 or less is performed. Set whether to perform modulation. This setting can be switched by means such as a system controller (not shown).

Next, a demodulation method and a demodulation device according to the present invention will be described. FIG. 11 shows an embodiment of a demodulation device suitable for the present invention. The bit sequence of the input code word is NRZI demodulated by the NRZI demodulation means 501, the synchronization word is detected by the synchronization detection circuit 502, and the NRZI demodulated signal and the synchronization word are converted by a word clock which is a timing signal for converting into parallel 6 bits. The serial / parallel converter 503 forms a code string C (k) every 6 bits. Thereafter, the codeword C (k-1) input to the word register 504 and delayed by one word is input to the codeword determination information detection device 505, and the determination information described later is calculated and output. The determination information and the input codeword Ck are input to the state calculator 506, and a state S (k) indicating which of the four coding tables has been used for coding is output. An output data word is output from, for example, the decoding table 508 shown in FIG. 12 according to the addresses specified by (k-1) and S (k).

  The determination information is divided into three cases of 0, 1, and 2 as shown in FIG. 12, and indicates which coding table is used to code the next codeword by the zero run length on the LSB side. In other words, C (k-1) is demodulated to D (k-1) by knowing in which coding table the previous codeword C (k-1) and the current codeword are encoded. Is done.

(Equation 1)
if (judgment information == 0) [
if (codeword in the encoding table where C (k) is 0)
S (k) = 0;
elseif (codeword in coding table where C (k) is 1)
S (k) = 1;]
if (judgment information == 1) [
if (codeword in the encoding table where C (k) is 1)
S (k) = 1;
elseif (codeword in the encoding table where C (k) is 2)
S (k) = 2;
elseif (codeword in the encoding table where C (k) is 3 || 1)
S (k) = 3;
elseif (C (k) == 0 && C (k-1) == 32)
S (k) = 3;
elseif (C (k) == 0 && C (k-1) == 42)
S (k) = 2;]
if (judgment information == 2) [
if (codeword || 9 || 5 || 2 in the coding table where C (k) is 3)
S (k) = 3;
elseif (codeword || 10 || 8 in the coding table where C (k) is 2)
S (k) = 2;
elseif (C (k) == 21)
S (k) = 0;]
if (D (k-1) == 2) [
if (C (k) is 4)
D (k-1) is 7;
]
Equation 1 is an operation for obtaining S (k) from C (k) and the determination information, and is described in C language. According to this calculation, S (k) is obtained from the determination information and C (k), C (k-1), and Ck-1 can be demodulated to Dk-1 by the demodulation table of FIG. Note that this calculation includes all demodulation calculations in the case of (1, 7) RLL, in the case of k = 8 to 12, and also in the case of setting a minimum run length limit larger than k = 9. For this reason, the demodulation device is the same and demodulation is normally performed regardless of whether the DSV control method, that is, either of FIG. 5 and FIG. 6, is selected in both (1, 7) RLL and k = 8 to 12.

  For example, when a code word string of 010000 001001 00000001 000101 010001 as shown in FIG. 14 is input to the demodulator shown in FIG. 11, the zero run length on the LSB side of the determination information of C (k−1) = 00000 is four. Therefore, the determination information is 2 as shown in FIG. Further, the next codeword C (k) continues to be 001001 (decimal: 9), which satisfies the first condition determination of Expression 1, and thus it can be seen that S (k) is 3. Therefore, since C (k-1) of the demodulation table in FIG. 13 has S (k) of 3 in the row of 010000, D (k-1) is obtained as 15. That is, D (k-1) corresponding to C (k-1) at time k-1 is decoded from state information (number) S (k) in the encoding table in which C (k) at time k was generated. Because Similarly, since the determination information of 001001 is 0 and the following code word 000001 is in S (k) = 0 of the encoding table, D (k-1) is determined to be 0 by the demodulation table of FIG. Similarly, 000001 is obtained as D (k-1) is 1, and 000101 is obtained as D (k-1) is 2. Note that 001001 is a code word exchanged under the condition 1-1 in FIG. 5 for DSV control, but it is clear from the above description that decoding was successfully performed.

FIG. 3 is a basic configuration diagram of a modulation device according to the present invention. FIG. 2 is a block diagram of a modulation device according to the present invention. FIG. 3 is a block diagram illustrating a configuration around an encoding unit illustrated in FIG. 2. 3 is a flowchart illustrating an encoding operation of the modulation device illustrated in FIG. 2. It is a flowchart which shows DSV control in the case of (1,7) RLL of this invention. It is a flowchart which shows DSV control in the case of (1,8) RLL of this invention. FIG. 6 is a diagram illustrating a 6-bit binary output codeword corresponding to a 4-bit decimal input data word. It is a figure showing each content of four coding tables S (k) = 0-S (k) = 3 used for the modulation device of the present invention. FIG. 3 is a diagram illustrating an encoding process in the modulation device of the present invention. FIG. 5 is a diagram for explaining the operation of the modulation device of the present invention. It is a block diagram of an example of a demodulation device of the present invention. FIG. 7 is a diagram illustrating determination information used in the demodulation device of the present invention. FIG. 3 is a diagram illustrating a demodulation table used in the demodulation device of the present invention. FIG. 3 is a diagram for explaining the operation of the demodulation device of the present invention. It is a figure showing other examples of an encoding table of the present invention.

Explanation of reference numerals

1 .... modulation device,
2. Recording medium,
3. Transmission medium,
11 ... format part,
12 4-6 modulation section,
13: encoding table,
14 ... NRZI conversion circuit,
15: Recording drive circuit,
31 ... transmission code part,
121: codeword option presence / absence detection circuit
122: coding table address calculation unit 123: synchronization word generation unit
126, 127... DSV operation memory,
124, 125 ... code word memory,
128 ... absolute value comparison unit
129... Memory control encoded output unit
501 NRZI demodulation,
502... Synchronization detection circuit
503: Serial / parallel converter,
504: word register,
505 codeword determination information detection device
506 ... state calculator,
507 ... address generation unit,
508: decryption table,

Claims (7)

When converting an input data word of N times 4 bits (N is a positive integer) into an output code word of N times 6 bits (N is a positive integer), Referring to each of the output codewords corresponding to a data word and a plurality of encoding tables including encoding table designation information that designates an encoding table used to encode the next input data word, Each of the output codewords is directly and sequentially connected as a binary output codeword sequence, and an output codeword that satisfies any one of 7 or more and 12 or less according to the (1, k) RLL (Run Length Limited) rule. A modulation method for outputting as
The plurality of encoding tables include at least a first and a second encoding table, and a first output codeword on the first encoding table corresponding to a predetermined input data word, After the NRZI-modulated signals of the data word and the second output code word on the second encoding table corresponding to the same input data word have opposite polarities, and after outputting a specific output code word, Regardless of which of the first and second output codewords is selected, the selected output codeword is an output codeword that satisfies any one of 7 or more and 12 or less according to the (1, k) RLL rule. ,
A selecting unit for selecting one of the first and second output codewords,
It is detected that the output codeword corresponding to the input data word specified by the coding table specification information is any of the first and second output codewords, and based on the detection result, the first and second output codewords are detected. Output encoding table designation information to specify any of the encoding table to the plurality of encoding tables,
An output code word sequentially output in correspondence with an input data word by using a specified encoding table from among the plurality of encoding tables is stored separately for each polarity of the output code word. DSV (digital sum variation) obtained by sequentially adding a CDS (codeword digital sum) corresponding to an output codeword stored in the output codeword memory means for each output codeword sequentially output from the conversion table. ) Is accumulated, and an output codeword sequence is selected and sequentially output based on the magnitude of the accumulated DSV absolute value. A conversion unit that encodes an input data word of N times 4 bits (N is a positive integer) into an output codeword of N times 6 bits (N is a positive integer); A plurality of encoding tables for encoding the input data words into the output code words are provided. Each of the encoding tables includes the output code words corresponding to the input data words, And coding table designating information for designating a coding table used to encode the input data words of the input data words. The output code words are sequentially directly combined as a binary output code word sequence (1). , K) a modulator for outputting as an output codeword satisfying any one of 7 or more and 12 or less in RLL (Run Length Limited) rule,
The plurality of encoding tables include at least first and second encoding tables, and a first output codeword on the first encoding table corresponding to a predetermined input data word; The signals obtained by NRZI-modulating the word and the second output codeword on the second encoding table corresponding to the same input data word have opposite polarities, and after outputting a specific output codeword, Regardless of which of the first and second output codewords is selected, the selected output codeword is an output codeword that satisfies any one of 7 or more and 12 or less in the (1, k) RLL rule. A modulator comprising a selecting means for selecting one of the first and second output codewords, wherein the output codeword corresponding to the input data word specified by the coding table specifying information is the second codeword. 1, any of the second output codewords And an encoding table designating means for outputting encoding table designation information for designating one of the first and second encoding tables to the plurality of encoding tables based on the detection result. An output code word memory for sorting and storing output code words sequentially output in correspondence with an input data word for each polarity of the output code word using an encoding table designated from among the plurality of encoding tables; Means and a CDS (codeword digital sum) corresponding to an output codeword stored in said output codeword memory means are sequentially added for each output codeword sequentially output from a designated encoding table. DSV memory means for storing a DSV (Digital Sum Variation), and the absolute value of the DSV output from the DSV memory means, A modulator for selecting an output codeword sequence sequentially output from the output codeword memory. A demodulation method for demodulating a code word sequence obtained by serializing code words in N-times (N is a positive integer) unit of 6 bits encoded using the modulation method according to claim 1 into a reproduction data sequence. hand,
The codeword sequence is reconstructed into codewords every N times of 6 bits (N is a positive integer), and a subsequent codeword is encoded in any one of the plurality of encoding tables. A demodulation method for demodulating the codeword sequence into a reproduction data sequence based on determination information indicating whether the codeword sequence is followed by a subsequent codeword. A demodulation device for demodulating a code word sequence obtained by serializing code words in N-times (N is a positive integer) unit of 6 bits encoded using the modulation device according to claim 2 into a reproduction data sequence. hand,
Means for reconstructing the codeword string into codewords every N times 6 bits (N is a positive integer), and a method in which a subsequent codeword is encoded in any one of the plurality of encoding tables. A demodulation device, comprising: means for demodulating the code word sequence into a reproduced data sequence based on determination information indicating whether the decoding is performed and a subsequent code word.   An information recording medium characterized by recording at least a part of a codeword encoded using the modulation device according to claim 2.   An information transmission method comprising transmitting information as a transmission information using a codeword encoded using the modulation method according to claim 1. An information transmission device, wherein information transmission is performed using a codeword encoded using the modulation device according to claim 2 as transmission information.

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