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JP2017199705A - Semiconductor element built-in substrate - Google Patents

Semiconductor element built-in substrate Download PDF

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Publication number
JP2017199705A
JP2017199705A JP2016086673A JP2016086673A JP2017199705A JP 2017199705 A JP2017199705 A JP 2017199705A JP 2016086673 A JP2016086673 A JP 2016086673A JP 2016086673 A JP2016086673 A JP 2016086673A JP 2017199705 A JP2017199705 A JP 2017199705A
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semiconductor element
main surface
sealing body
insulating layer
substrate
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義徳 中臣
Yoshinori Nakaomi
義徳 中臣
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Kyocera Corp
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element built-in substrate which efficiently radiates heat generated from a semiconductor element, and allows the semiconductor element to operate with stability.SOLUTION: A semiconductor element built-in substrate A includes: a resin sealing body 11 having a first main surface 11a and a second main surface 11b that face each other and are flat; a semiconductor element 10 which has an electrode terminal formation surface 10b having a plurality of electrode terminals 10a formed thereon and is built in the resin sealing body 11 so that the electrode terminal formation surface 10b is exposed to the first main surface 11a; an insulating layer 12 laminated so as to cover the electrode terminal formation surface 10b and the first main surface 11a; a plurality of via holes 15 which are formed on the insulating layer 12 and use the electrode terminal 10a as the bottom face; and a wiring conductor 13 formed on the surface and the inside of the insulating layer 12 and in the via hole 15, where the semiconductor element built-in substrate includes a metal layer 14 for heat radiation on the surface of the second main surface 11b of the resin sealing body 11.SELECTED DRAWING: Figure 1

Description

本発明は、半導体素子を内蔵する半導体素子内蔵基板に関するものである。   The present invention relates to a semiconductor element built-in substrate that incorporates a semiconductor element.

図３に、従来の半導体素子内蔵基板Ｃの概略断面図を示す。
従来の半導体素子内蔵基板Ｃは、例えば半導体素子２０と、樹脂封止体２１と、樹脂保護層２２と、絶縁層２３と、配線導体２４と、を有している。 FIG. 3 shows a schematic cross-sectional view of a conventional substrate C with a built-in semiconductor element.
A conventional semiconductor element-embedded substrate C includes, for example, a semiconductor element 20, a resin sealing body 21, a resin protective layer 22, an insulating layer 23, and a wiring conductor 24.

半導体素子２０の側面は、樹脂封止体２１に埋設されている。また、半導体素子２０の上面は、厚みが１０〜２０μｍ程度の樹脂保護層２２に被覆されている。樹脂保護層２２は、半導体素子２０を外部環境から保護するとともに、半導体素子内蔵基板Ｃに生じる反りを抑制している。
絶縁層２３は、半導体素子２０の下面および樹脂封止体２１の下面を覆うように形成されている。絶縁層２３は、上層の絶縁層２３ａおよび下層の絶縁層２３ｂで構成されており、各絶縁層２３ａ、２３ｂには複数のビアホール２５が形成されている。各絶縁層２３ａ、２３ｂの表面およびビアホール２５の内部には、配線導体２４が形成されている。ビアホール２５の内部に形成された配線導体２４は、ビア導体２６として機能し各絶縁層２３ａ、２３ｂに形成された配線導体２４間の導通をとっている。上層の絶縁層２３ａに形成されたビア導体２６は、半導体素子２０の電極端子２０ａと接続されている。
また、下層の絶縁層２３ｂに形成された配線導体２４の一部は、回路基板接続パッド２７を形成している。回路基板接続パッド２７には、この半導体素子内蔵基板Ｃが搭載される回路基板の電極が半田を介して接続される。
そして、半導体素子２０と回路基板との間で配線導体２４を介して電気信号の伝送をすることで半導体素子２０が作動する。 The side surface of the semiconductor element 20 is embedded in the resin sealing body 21. The upper surface of the semiconductor element 20 is covered with a resin protective layer 22 having a thickness of about 10 to 20 μm. The resin protective layer 22 protects the semiconductor element 20 from the external environment and suppresses the warp generated in the semiconductor element built-in substrate C.
The insulating layer 23 is formed so as to cover the lower surface of the semiconductor element 20 and the lower surface of the resin sealing body 21. The insulating layer 23 includes an upper insulating layer 23a and a lower insulating layer 23b, and a plurality of via holes 25 are formed in each of the insulating layers 23a and 23b. A wiring conductor 24 is formed on the surface of each insulating layer 23a, 23b and inside the via hole 25. The wiring conductor 24 formed inside the via hole 25 functions as the via conductor 26 and establishes conduction between the wiring conductors 24 formed in the insulating layers 23a and 23b. A via conductor 26 formed in the upper insulating layer 23 a is connected to the electrode terminal 20 a of the semiconductor element 20.
A part of the wiring conductor 24 formed in the lower insulating layer 23 b forms a circuit board connection pad 27. The circuit board connection pads 27 are connected to the electrodes of the circuit board on which the semiconductor element built-in substrate C is mounted via solder.
Then, the semiconductor element 20 operates by transmitting an electrical signal between the semiconductor element 20 and the circuit board via the wiring conductor 24.

しかしながら、従来の半導体素子内蔵基板Ｃにおいては、半導体素子２０の側面および上面が樹脂封止体２１および樹脂保護層２２によって被覆されており、熱伝導性に優れた部材が存在しないため、半導体素子２０の作動によって生じる熱を効率よく放熱することができない。そのため、半導体素子２０が高温になり安定的に作動することができないという問題がある。   However, in the conventional semiconductor element-embedded substrate C, the side surface and the upper surface of the semiconductor element 20 are covered with the resin sealing body 21 and the resin protective layer 22, and there is no member having excellent thermal conductivity. The heat generated by the operation of 20 cannot be radiated efficiently. Therefore, there exists a problem that the semiconductor element 20 becomes high temperature and cannot operate | move stably.

特許第５５６３８１４号公報Japanese Patent No. 5563814

本発明は、半導体素子から生じる熱を効率的に放熱することによって、半導体素子が高温になることを防いで安定的に作動することができる半導体素子内蔵基板を提供することを課題とする。   An object of the present invention is to provide a substrate with a built-in semiconductor element that can stably operate while preventing the semiconductor element from becoming high temperature by efficiently radiating heat generated from the semiconductor element.

本発明における半導体素子内蔵基板は、互いに対向する平坦な第１の主面および第２の主面を有する樹脂封止体と、電極端子が複数形成された電極端子形成面を有しており、第１の主面に電極端子形成面が露出するように樹脂封止体に埋設された半導体素子と、電極端子形成面および第１の主面を被覆するように積層された絶縁層と、絶縁層に複数形成されており電極端子を底面とするビアホールと、絶縁層表面およびビアホール内に形成された配線導体とを備える半導体素子内蔵基板であって、樹脂封止体の第２の主面表面に、放熱用の金属層を具備していることを特徴とするものである。   The substrate with a built-in semiconductor element in the present invention has a resin sealing body having a flat first main surface and a second main surface facing each other, and an electrode terminal forming surface on which a plurality of electrode terminals are formed, A semiconductor element embedded in a resin encapsulant so that the electrode terminal forming surface is exposed on the first main surface, an insulating layer laminated so as to cover the electrode terminal forming surface and the first main surface, and insulation A semiconductor element-embedded substrate comprising a plurality of via holes formed in a layer and having an electrode terminal as a bottom surface, an insulating layer surface and a wiring conductor formed in the via hole, and a second main surface surface of the resin-encapsulated body And a metal layer for heat dissipation.

本発明に係る半導体素子内蔵基板によれば、半導体素子を埋設する樹脂封止体の第２の主面表面に放熱用の金属層が形成されている。
このため、半導体素子から生じる熱を放熱用の金属層を介して外部に効率よく放熱することができる。これにより、半導体素子が高温になることを防いで安定的に作動することが可能な半導体素子内蔵基板を提供することができる。 According to the substrate with a built-in semiconductor element according to the present invention, the metal layer for heat dissipation is formed on the surface of the second main surface of the resin sealing body in which the semiconductor element is embedded.
For this reason, the heat generated from the semiconductor element can be efficiently radiated to the outside through the metal layer for heat dissipation. As a result, it is possible to provide a semiconductor element-embedded substrate capable of stably operating while preventing the semiconductor element from becoming high temperature.

図１は、本発明に係る半導体素子内蔵基板の一例を示す概略断面図である。FIG. 1 is a schematic cross-sectional view showing an example of a semiconductor element built-in substrate according to the present invention. 図２は、本発明に係る半導体素子内蔵基板の異なる一例を説明するための概略断面図である。FIG. 2 is a schematic cross-sectional view for explaining a different example of the semiconductor element-embedded substrate according to the present invention. 図３は、従来の半導体素子内蔵基板の一例を示す概略断面図である。FIG. 3 is a schematic sectional view showing an example of a conventional substrate with a built-in semiconductor element.

まず、本発明に係る半導体素子内蔵基板の一例を、図１を基にして説明する。   First, an example of a semiconductor element built-in substrate according to the present invention will be described with reference to FIG.

図１に示すように、本発明に係る半導体素子内蔵基板Ａは、例えば半導体素子１０と、樹脂封止体１１と、絶縁層１２と、配線導体１３と、放熱用の金属層１４とを有している。   As shown in FIG. 1, a semiconductor element-embedded substrate A according to the present invention includes, for example, a semiconductor element 10, a resin sealing body 11, an insulating layer 12, a wiring conductor 13, and a heat-dissipating metal layer 14. doing.

半導体素子１０は、例えばマイクロプロセッサや半導体メモリ等があげられ、シリコンやゲルマニウムから成る。半導体素子１０は、複数の電極端子１０ａが形成された電極端子形成面１０ｂを有している。   Examples of the semiconductor element 10 include a microprocessor and a semiconductor memory, and are made of silicon or germanium. The semiconductor element 10 has an electrode terminal forming surface 10b on which a plurality of electrode terminals 10a are formed.

樹脂封止体１１は、例えばエポキシ樹脂やポリウレタン樹脂等の熱硬化性樹脂から成る。樹脂封止体１１は、互いに対向する平坦な第１の主面１１ａおよび第２の主面１１ｂとを有している。半導体素子１０は、主面１１ａに電極端子形成面１０ｂが露出する状態で樹脂封止体１１内に埋設されている。樹脂封止体１１は、半導体素子１０を外部環境から保護している。
なお、半導体素子１０の上方に被覆される樹脂封止体１１の厚みは、２〜５μｍ程度であることが好ましい。樹脂封止体１１の厚みが５μｍよりも厚いと、半導体素子１０から生じる熱を放熱用の金属層１４に効率良く伝えることができなくなり放熱性が悪くなる。また、樹脂封止体１１の厚みが２μｍよりも薄いと、放熱用の金属層１４と樹脂封止体１１との接着代が少なくなるため両者の接着強度が悪くなる。 The resin sealing body 11 is made of a thermosetting resin such as an epoxy resin or a polyurethane resin. The resin sealing body 11 has a flat first main surface 11a and a second main surface 11b facing each other. The semiconductor element 10 is embedded in the resin sealing body 11 with the electrode terminal forming surface 10b exposed at the main surface 11a. The resin sealing body 11 protects the semiconductor element 10 from the external environment.
In addition, it is preferable that the thickness of the resin sealing body 11 coat | covered above the semiconductor element 10 is about 2-5 micrometers. When the thickness of the resin sealing body 11 is thicker than 5 μm, heat generated from the semiconductor element 10 cannot be efficiently transmitted to the heat radiating metal layer 14 and heat dissipation becomes worse. On the other hand, if the thickness of the resin sealing body 11 is less than 2 μm, the bonding allowance between the heat dissipating metal layer 14 and the resin sealing body 11 is reduced, so that the adhesive strength between the two becomes worse.

絶縁層１２は、例えばエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂から成る。絶縁層１２は、電極端子形成面１０ｂの表面および第１の主面１１ａを被覆するように形成されている。絶縁層１２は、上下に積層された第１の絶縁層１２ａおよび第２の絶縁層１２ｂで構成されている。
第１および第２の絶縁層１２ａ，１２ｂには、複数のビアホール１５が形成されている。第１および第２の絶縁層１２ａ，１２ｂの表面およびビアホール１５内には、配線導体１３が形成されている。
絶縁層１２の形成は、例えばエポキシ樹脂やビスマレイミドトリアジン樹脂組成物の未硬化物に無機絶縁性フィラーを分散して形成されたフィルムを、被形成面上に真空状態で被覆した状態で熱圧着することで行われる。
ビアホール１５は、例えばレーザー加工やブラスト加工により形成される。 The insulating layer 12 is made of a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. The insulating layer 12 is formed so as to cover the surface of the electrode terminal forming surface 10b and the first main surface 11a. The insulating layer 12 includes a first insulating layer 12a and a second insulating layer 12b that are stacked one above the other.
A plurality of via holes 15 are formed in the first and second insulating layers 12a and 12b. A wiring conductor 13 is formed in the surface of the first and second insulating layers 12 a and 12 b and in the via hole 15.
The insulating layer 12 is formed by, for example, thermocompression bonding with a film formed by dispersing an inorganic insulating filler in an uncured product of an epoxy resin or a bismaleimide triazine resin composition on a surface to be formed in a vacuum state. It is done by doing.
The via hole 15 is formed by, for example, laser processing or blast processing.

配線導体１３は、例えば周知のセミアディティブ法を用いて無電解銅めっきおよび電解銅めっき等の良導電性金属により絶縁層１２の表面および内部、ならびにビアホール１５内に形成されている。ビアホール１５内に形成された配線導体１３は、ビア導体１６として機能し電極端子１０ａと配線導体１３との間、あるいは異層の配線導体１３同士の間の導通をとっている。
絶縁層１２の最表層には、配線導体１３の一部から成る回路基板接続パッド１７が形成されている。回路基板接続パッド１７には、この半導体素子内蔵基板Ａが搭載される回路基板（不図示）の電極が半田を介して接続される。
そして、半導体素子１０と回路基板との間で配線導体１３を介して電気信号の伝送をすることで半導体素子１０が作動する。 The wiring conductor 13 is formed in the surface and the inside of the insulating layer 12 and in the via hole 15 with a highly conductive metal such as electroless copper plating and electrolytic copper plating using a known semi-additive method. The wiring conductor 13 formed in the via hole 15 functions as the via conductor 16 and establishes conduction between the electrode terminal 10a and the wiring conductor 13 or between the wiring conductors 13 in different layers.
On the outermost layer of the insulating layer 12, a circuit board connection pad 17 made of a part of the wiring conductor 13 is formed. An electrode of a circuit board (not shown) on which the semiconductor element built-in substrate A is mounted is connected to the circuit board connection pad 17 via solder.
The semiconductor element 10 operates by transmitting an electrical signal between the semiconductor element 10 and the circuit board via the wiring conductor 13.

放熱用の金属層１４は、例えば銅箔やアルミ箔等の良熱伝導性金属により樹脂封止体１１の第２の主面１１ｂ表面全体に形成されている。
放熱用の金属層１４を樹脂封止体１１の表面に形成するには、例えば成形用の下金型内に銅箔および樹脂封止体１１用の熱硬化性樹脂の順に装填するとともに、上金型内に半導体素子１０を装填して半導体素子１０を熱硬化性樹脂内に埋設するように押圧しながら加熱することで形成される。また、例えば樹脂封止体１１を成形した後に、その表面に熱伝導性に優れた接着剤を介して銅箔を接着しても構わない。
なお、放熱用の金属層１４の表側を、例えばフィン状にパターン形成して表面積を増やしておくと放熱性を向上させることができる。
さらに、放熱用の金属層１４の表面を、例えばエッチング処理や研磨処理を施すことで粗面化を行い表面積を増やすことでも放熱性を向上させることが可能になる。
なお、半導体素子１０上の樹脂封止体１１の厚みは、２〜５μｍ程度であることが好ましい。樹脂封止体１１の厚みが５μｍよりも厚いと、半導体素子１０から生じる熱を放熱用の金属層１４に効率良く伝えることができなくなり放熱性が悪くなる。また、樹脂封止体１１の厚みが２μｍよりも薄いと、放熱用の金属層１４と樹脂封止体１１との接着代が少なくなるため両者の接着強度が悪くなる。 The metal layer 14 for heat dissipation is formed on the entire surface of the second main surface 11b of the resin sealing body 11 with a good heat conductive metal such as copper foil or aluminum foil.
In order to form the heat radiation metal layer 14 on the surface of the resin sealing body 11, for example, a copper foil and a thermosetting resin for the resin sealing body 11 are sequentially loaded in a lower mold for molding, It is formed by loading the semiconductor element 10 in a mold and heating the semiconductor element 10 while pressing so as to be embedded in the thermosetting resin. Further, for example, after molding the resin sealing body 11, a copper foil may be bonded to the surface via an adhesive having excellent thermal conductivity.
In addition, if the surface side of the metal layer 14 for heat radiation is patterned in, for example, a fin shape to increase the surface area, the heat dissipation can be improved.
Furthermore, it is possible to improve the heat dissipation by roughening the surface of the metal layer 14 for heat dissipation by, for example, performing an etching process or a polishing process to increase the surface area.
In addition, it is preferable that the thickness of the resin sealing body 11 on the semiconductor element 10 is about 2-5 micrometers. When the thickness of the resin sealing body 11 is thicker than 5 μm, heat generated from the semiconductor element 10 cannot be efficiently transmitted to the heat radiating metal layer 14 and heat dissipation becomes worse. On the other hand, if the thickness of the resin sealing body 11 is less than 2 μm, the bonding allowance between the heat dissipating metal layer 14 and the resin sealing body 11 is reduced, so that the adhesive strength between the two becomes worse.

このように、本発明に係る半導体素子内蔵基板Ａによれば、半導体素子１０を埋設する樹脂封止体１１の第２の主面１１ｂ表面全面に放熱用の金属層１４が形成されている。
このため、半導体素子１０から生じる熱を放熱用の金属層１４を介して外部に効率よく放熱することができる。これにより、半導体素子１０が高温になることを防いで安定的に作動することが可能な半導体素子内蔵基板Ａを提供することができる。 Thus, according to the semiconductor element-embedded substrate A according to the present invention, the heat radiation metal layer 14 is formed on the entire surface of the second main surface 11b of the resin sealing body 11 in which the semiconductor element 10 is embedded.
For this reason, the heat generated from the semiconductor element 10 can be efficiently radiated to the outside through the metal layer 14 for radiating heat. Thereby, it is possible to provide the semiconductor element-embedded substrate A that can prevent the semiconductor element 10 from becoming high temperature and can operate stably.

なお、本発明は上述の実施形態の一例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能である。例えば上述の実施の形態の一例では、放熱用の金属層１４が最外層に形成されている例を示したが、図２に示すように、放熱用の金属層１４の表面に、反り抑制用の樹脂層１８を形成しても構わない。最上層に反り抑制用の樹脂層１８を形成して、最下層に形成されている絶縁層１２との熱伸縮差を小さくすることで反りを抑制する。
また、例えば上述の実施の形態の一例では、絶縁層１２の最表層面にソルダーレジスト層が被着されていない場合を示したが、ソルダーレジスト層が被着されていても構わない。
さらに、例えば上述の実施の形態の一例では、金属層１４が第２の主面１１ｂ表面全面に形成されている場合を示したが、発熱体である半導体素子１０の上方付近にのみ形成しても構わない。 In addition, this invention is not limited to an example of above-mentioned embodiment, A various change is possible if it is a range which does not deviate from the summary of this invention. For example, in the example of the above-described embodiment, the example in which the heat dissipation metal layer 14 is formed in the outermost layer is shown. However, as shown in FIG. The resin layer 18 may be formed. The warp suppressing resin layer 18 is formed in the uppermost layer, and the warp is suppressed by reducing the thermal expansion / contraction difference with the insulating layer 12 formed in the lowermost layer.
Further, for example, in the example of the above-described embodiment, the case where the solder resist layer is not deposited on the outermost surface of the insulating layer 12 is shown, but the solder resist layer may be deposited.
Further, for example, in the above-described embodiment, the metal layer 14 is formed on the entire surface of the second main surface 11b. However, the metal layer 14 is formed only near the upper portion of the semiconductor element 10 that is a heating element. It doesn't matter.

１０ 半導体素子
１０ａ 電極端子
１０ｂ 電極端子形成面
１１ 樹脂封止体
１１ａ 第１の主面
１１ｂ 第２の主面
１２ 絶縁層
１３ 配線導体
１４ 放熱用の金属層
１５ ビアホール
Ａ 半導体素子内蔵基板 DESCRIPTION OF SYMBOLS 10 Semiconductor element 10a Electrode terminal 10b Electrode terminal formation surface 11 Resin sealing body 11a 1st main surface 11b 2nd main surface 12 Insulating layer 13 Wiring conductor 14 Metal layer 15 for heat dissipation Via hole A Semiconductor element built-in substrate

Claims (1)

互いに対向する平坦な第１の主面および第２の主面を有する樹脂封止体と、
電極端子が複数形成された電極端子形成面を有しており、前記第１の主面に前記電極端子形成面が露出するように前記樹脂封止体に埋設された半導体素子と、
前記電極端子形成面および前記第１の主面を被覆するように積層された絶縁層と、
前記絶縁層に複数形成されており前記電極端子を底面とするビアホールと、
前記絶縁層表面および前記ビアホール内に形成された配線導体と、
を備える半導体素子内蔵基板であって、
前記樹脂封止体の第２の主面表面に、放熱用の金属層を具備していることを特徴とする半導体素子内蔵基板。 A resin sealing body having a flat first main surface and a second main surface facing each other;
A semiconductor element having an electrode terminal forming surface in which a plurality of electrode terminals are formed, embedded in the resin sealing body so that the electrode terminal forming surface is exposed on the first main surface;
An insulating layer laminated to cover the electrode terminal forming surface and the first main surface;
A plurality of via holes formed in the insulating layer and having the electrode terminal as a bottom surface;
A wiring conductor formed in the insulating layer surface and the via hole;
A semiconductor element built-in substrate comprising:
A semiconductor element-embedded substrate comprising a metal layer for heat dissipation on a surface of a second main surface of the resin-encapsulated body.
JP2016086673A 2016-04-25 2016-04-25 Semiconductor element built-in substrate Pending JP2017199705A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7574632B2 (en) 2020-12-10 2024-10-29 Ｔｏｐｐａｎホールディングス株式会社 Substrate unit, method of manufacturing substrate unit, and method of manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7574632B2 (en) 2020-12-10 2024-10-29 Ｔｏｐｐａｎホールディングス株式会社 Substrate unit, method of manufacturing substrate unit, and method of manufacturing semiconductor device

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