JP7574632B2 - Substrate unit, method of manufacturing substrate unit, and method of manufacturing semiconductor device - Google Patents

Description

The present invention relates to a substrate unit, a method for manufacturing a substrate unit, and a method for manufacturing a semiconductor device.

As semiconductor devices have become faster and more highly integrated in recent years, there is a demand for FC-BGA (Flip Chip-Ball Grid Array) boards to have narrower pitches for the connection terminals with semiconductor elements and finer wiring within the board. On the other hand, there is a demand for the connection between the FC-BGA board and the motherboard to be made with connection terminals with roughly the same pitch as before.

Several measures are being considered to accommodate the narrower pitch of the connecting terminals with semiconductor elements and the finer wiring within FC-BGA substrates.

One of these methods involves creating a substrate (silicon interposer) for bonding semiconductor elements that has fine wiring formed on a silicon substrate, and then bonding this to an FC-BGA substrate.

Patent Document 1 also discloses a method of forming fine wiring on an FC-BGA substrate by planarizing the surface of the FC-BGA substrate using CMP (Chemical Mechanical Polishing) or the like without using a silicon interposer.

Furthermore, Patent Document 2 discloses a method of forming a fine wiring layer on a support, mounting this on an FC-BGA substrate, and then peeling off the support substrate to form a narrow-pitch wiring substrate.

JP 2014-225671 A International Publication No. 2018/047861

Silicon interposers are manufactured using silicon wafers with equipment used in front-end semiconductor manufacturing processes. Silicon wafers are limited in shape and size, and only a small number of interposers can be manufactured from a single wafer. In addition, the manufacturing equipment is expensive, so the interposers are also expensive. In addition, because silicon wafers are semiconductors, there is the problem that their transmission characteristics deteriorate.

In addition, in the method of flattening the surface of the FC-BGA substrate and forming a fine wiring layer on top of it, the degradation of transmission characteristics seen in silicon interposers is small, but the manufacturing yield of the FC-BGA substrate itself and the difficulty of forming the fine wiring on the FC-BGA substrate are high, so the manufacturing yield of the fine wiring formation is an issue. Furthermore, there are also issues in mounting semiconductor elements due to warping and distortion of the FC-BGA substrate.

On the other hand, the method of forming a fine wiring layer on a support and mounting this on an FC-BGA substrate has the following problems. Namely, when the fine wiring layer formed on the support substrate is mounted on the FC-BGA substrate and then the support substrate is peeled off, the sealing resin material used when mounting the fine wiring layer on the FC-BGA substrate wets up to the support substrate, preventing the support substrate from being peeled off. Also, the force generated when peeling off the support substrate and the stress stored inside cause the entire fine wiring layer to warp, causing problems when mounting semiconductor elements.

Another method is to form a fine wiring layer on a support substrate, mount and seal a semiconductor element on the fine wiring layer, and then peel the fine wiring layer from the support substrate and mount the peeled fine wiring layer with the semiconductor element on an FC-BGA substrate. With this method, the semiconductor element is mounted on the fine wiring layer held by the support substrate, making it possible to mount the semiconductor element with minimal deformation. However, because the fine wiring layer is formed on one side of the support, there is a problem that warping occurs due to the heat history when forming the wiring layer. In particular, there is a problem that semiconductor elements mounted on the fine wiring layer are prone to mounting defects even when there is only a slight warping, because the distance between the terminals is short.

The present invention has been developed in consideration of the above problems, and aims to provide a substrate unit that is less prone to deformation and can be manufactured stably, a method for manufacturing a substrate unit, and a method for manufacturing a semiconductor device.

Problems and advantages other than those mentioned above are explained in the following embodiments of the invention.

In order to solve the above problems, one of the representative substrate units of the present invention is a substrate unit including a support and a plurality of first wiring substrates mounted on the support via a release layer,
an electrode for bonding at least one semiconductor element is provided on a first surface of the first wiring board;
an electrode for joining the first wiring board to the second wiring board is provided on the second surface of the first wiring board;
A warp suppressing layer is formed below the support.

Furthermore, one of the representative methods for producing a substrate unit according to the present invention is to
forming a release layer on an upper surface of the support;
forming a resin layer above the release layer;
forming a warp suppressing layer on the lower surface of the support;
forming an opening in the resin layer;
forming a seed layer over the resin layer and the opening;
forming an electrolytic plating layer above the seed layer;
a step of polishing the electrolytic plating layer and the seed layer until the resin layer is exposed, and forming an electrode for bonding to a second wiring board;
a step of repeatedly forming a resin layer and a conductor layer on the upper surface of the exposed resin layer and the electrode to obtain a multilayer wiring;
forming an electrode for bonding a semiconductor element to the outermost surface of the multilayer wiring;
Includes.

Furthermore, one of the representative methods for manufacturing a semiconductor device according to the present invention includes the steps of:
a step of bonding a semiconductor element to a first wiring substrate;
a step of sealing a gap between the first wiring board and the semiconductor element with a first sealing resin;
sealing the side surfaces of the first wiring board and the semiconductor element with a second sealing resin;
peeling the first wiring substrate from the support;
obtaining an assembly in which a semiconductor element is bonded to a first wiring substrate;
a step of dividing the assembly into individual first wiring substrates; and a step of bonding the first wiring substrate to a second wiring substrate.
sealing a gap between the first wiring board and the second wiring board with a third sealing resin;
Includes.

According to the present invention, it is possible to manufacture a board unit that is less prone to warping, and a semiconductor element can be mounted with less warping.
Problems and advantages other than those described above will be described in the following embodiments.

13 is a diagram showing a state in which a release layer and a first wiring substrate are formed above the support body, and a warp suppressing layer is formed below the support body. FIG. 1 is a plan view showing a state in which a plurality of first wiring substrates are placed above a support body; 1 is a cross-sectional view showing a state in which a release layer and an insulating resin layer are formed above a support body, and a warp suppressing layer is formed below the support body. 4A to 4C are cross-sectional views showing a step of forming an insulating resin layer and a conductor layer. 10 is a cross-sectional view showing a process of forming an insulating resin layer in a via portion and then forming a conductor layer. FIG. 10 is a cross-sectional view showing a step of removing the resist pattern and etching away unnecessary seed layer. FIG. FIG. 2 is a cross-sectional view showing a state in which multi-layer wiring is formed. 4 is a cross-sectional view showing a state in which an electrode for bonding to a semiconductor element has been formed. FIG. 10 is a cross-sectional view showing a state in which a surface treatment layer is formed and a first wiring substrate is completed on a support body. FIG. 5A to 5C are cross-sectional views showing a process of mounting a semiconductor element on a first wiring board. 10A to 10C are cross-sectional views showing a step of removing the release layer. 5A to 5C are process diagrams showing the formation of solder joints on the first wiring board. 1 is a cross-sectional view showing a state in which a first wiring board carrying a semiconductor element is mounted on an FC-BGA board. 1 is a cross-sectional view showing an example of a semiconductor device of the present invention. FIG. 11 is a cross-sectional view showing an example of a comparative example.

Below, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are given the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., differ from the actual ones. Therefore, the specific thickness and dimensions should be determined with reference to the following explanation. In addition, it goes without saying that the drawings include parts with different dimensional relationships and ratios.

The embodiments shown below are merely examples of devices and methods for embodying the technical ideas of the present invention, and the technical ideas of the present invention do not specify the materials, shapes, structures, arrangements, etc. of the components as described below. The technical ideas of the present invention can be modified in various ways within the technical scope defined by the claims.

<Embodiments of the present invention>
Hereinafter, an example of a manufacturing process for a wiring board using a support according to an embodiment of the present invention will be described with reference to the drawings.
In the present disclosure, a "support" refers to an object having a surface.
Additionally, the term "upper surface" refers to the surface in the normal direction of a surface or layer, and the term "lower surface" refers to the reverse surface in the normal direction of a surface or layer.
Additionally, "upper" refers to the vertically upward direction when the surface or layer is placed horizontally.
Additionally, "below" refers to the direction vertically below when the surface or layer is placed horizontally.
Moreover, the term "planar shape" refers to the shape when a surface or layer is viewed from above.

First, as shown in Figure 1, an example will be described in which a support 1, which is a rectangular plate-like member, is used. Figure 1 is a cross-sectional view showing a state in which a release layer 2 is formed on the upper surface of the support 1, a plurality of first wiring substrates 12 are formed on the upper surface of the release layer 2, and a warp suppression layer 3 is formed on the lower surface of the support 1.

In addition, in this embodiment, as shown in FIG. 2, a plurality of first wiring boards 12 are placed above the support body 1 to form a board unit 12A.

In this embodiment, the support 1 is described as a panel, which is a rectangular plate-like member, but the support 1 may also be, for example, a circular wafer.

Because light may be irradiated through the support 1 to the peeling layer 2, it is advantageous for the support 1 to be light-transmitting, and a rectangular glass plate, for example, may be used. Rectangular glass is suitable for large sizes, and glass has excellent flatness and high rigidity, making it suitable for forming fine patterns on the support.

In addition, glass has a small CTE (coefficient of thermal expansion) and is resistant to distortion, making it excellent for ensuring pattern placement accuracy and flatness. When glass is used as the support 1, it is desirable for the glass to be thick in order to suppress the occurrence of warping during the manufacturing process, and the thickness is, for example, 0.7 mm or more, preferably 1.1 mm or more.

Furthermore, the CTE of the glass is preferably 3 ppm or more and 15 ppm or less, and is more preferably about 9 ppm from the viewpoint of compatibility with the CTE of the FC-BGA substrate (second wiring substrate) 12 and the semiconductor element 11.

Types of glass that can be used include, for example, quartz glass, borosilicate glass, alkali-free glass, soda glass, or sapphire glass.

On the other hand, if the support 1 does not need to be optically transparent when peeling it off, such as when the peeling layer 2 is made of a resin that foams when heated, the support 1 can be made of a material with less distortion, such as metal or ceramics.

The peeling layer 2 may be, for example, a resin that absorbs light such as UV light and generates heat or changes in quality to become peelable, or a resin that foams when heated to become peelable.

Specifically, the release layer 2 can be selected from organic resins such as epoxy resin, polyimide resin, polyurethane resin, silicone resin, polyester resin, oxetane resin, maleimide resin, and acrylic resin, and inorganic layers such as amorphous silicon, gallium nitride, and metal oxide layers. Furthermore, the release layer 2 may contain additives such as photodecomposition promoters, light absorbers, sensitizers, and fillers.

Furthermore, the release layer 2 may be composed of multiple layers. For example, a protective layer may be provided on the release layer 2 for the purpose of protecting the multilayer wiring layer formed on the support 1 in a later process, or a layer for improving adhesion to the support 1 may be provided under the release layer 2. Furthermore, a laser light reflecting layer or a metal layer may be provided between the release layer 2 and the multilayer wiring layer, and the configuration is not limited to this embodiment.

When a resin that can be peeled off by light such as laser light is used as the peeling layer 2, if the support 1 is translucent, the direction in which light is irradiated onto the peeling layer 2 may be the side opposite to the side on which the peeling layer 2 is provided, i.e., the side on which the warp suppression layer 3 is formed.

The warp suppression layer 3 may be, for example, a resin that transmits light such as laser light. Specifically, the warp suppression layer 3 may be made of an organic resin such as an epoxy resin, a polyimide resin, a polybenzoxazole resin, or a benzocyclobutene resin. The warp suppression layer 3 may be made of the same resin as the insulating resin of the first wiring board 12, and may be photosensitive.

The thickness of the warp suppression layer 3 is preferably 5 μm or more and 50 μm or less. If it is 5 μm or less, there is a risk that the warp suppression effect will not be obtained. If it is 50 μm or more, the warp suppression effect will be excessive, and warp in the opposite direction will occur. In addition, it is preferable that the thickness of the warp suppression layer 3 is thinner than that of the first wiring board. If the warp suppression layer 3 is thicker than the first wiring board 12, the warp suppression effect will be excessive, and warp in the opposite direction (convex toward the first wiring board 12) will occur.

In the following, an embodiment of the present invention will be described using an example in which the warp suppression layer 3 is made of a resin that transmits IR (infrared) laser light, the support 1 is made of glass, and the peeling layer 2 is made of a resin that absorbs IR laser light and becomes peelable.

Next, an example of a manufacturing process for a first wiring substrate 12 on a support 1 according to one embodiment of the present invention will be described with reference to Figures 3 to 8.

First, as shown in FIG. 3(a), a release layer 2 is formed on the upper surface of the support 1.

Next, as shown in FIG. 3(b), an insulating resin layer 4 is formed on the upper surface of the release layer 2, and a warp suppression layer 3 is formed on the lower surface of the support 1.

In this embodiment, the insulating resin layer is formed, for example, by spin-coating a photosensitive epoxy resin. Photosensitive epoxy resin can be cured at a relatively low temperature, shrinks little due to curing after formation, and is excellent for subsequent fine pattern formation.

When using a liquid photosensitive resin, the method of forming the photosensitive resin can be selected from slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating. When using a film-like photosensitive resin, lamination, vacuum lamination, vacuum pressing, and the like can be applied. For the insulating resin layer, it is also possible to use, for example, photosensitive polyimide resin, photosensitive benzocyclobutene resin, photosensitive epoxy resin and its modified product, and photosensitive polybenzoxazole resin.

When a liquid resin is used, the warp suppression layer 3 can be formed by a method selected from slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating. When a film-like resin is used, lamination, vacuum lamination, vacuum pressing, and the like can be applied. The warp suppression layer 3 may be photosensitive, and for example, photosensitive polyimide resin, photosensitive benzocyclobutene resin, photosensitive epoxy resin and its modified product, and photosensitive polybenzoxazole resin can be used.

The warp suppression layer 3 can be made of the same resin as the insulating resin layer 4. By using the same resin as the insulating resin layer 4, processing can be carried out in a single process.

The order in which the insulating resin layer 4 and the warp suppression layer 3 are formed does not matter. Furthermore, it is also possible to form the release layer 2 and the insulating resin layer 4 after forming the warp suppression layer 3 on the lower surface of the support 1.

Furthermore, it is possible to use a resin different from that of the insulating resin layer 4 for the warp suppression layer 3. For example, by using a resin with a higher Young's modulus and a larger CTE than the insulating resin layer 4, it is possible to obtain the warp suppression effect even if the warp suppression layer 3 is made thin.

The warp suppression layer 3 may contain a resin different from that of the insulating resin layer 4 of the first wiring board 12. When the warp suppression layer 3 contains a resin different from that of the insulating resin layer 4, the number of resins that can be selected increases, and the degree of freedom in design increases. For example, it is possible to use a photosensitive epoxy resin for the insulating resin layer 4 of the first wiring board 12, and a non-photosensitive, thermosetting polyimide resin for the warp suppression layer 3.

It is desirable that the Young's modulus × thickness × CTE of the warp suppression layer 3 is 0.9 to 1.1 times the Young's modulus × thickness × CTE of the insulating resin (insulating resin layer 4) of the first wiring board. If the Young's modulus × thickness × CTE of the warp suppression layer 3 is less than 0.9 times the Young's modulus × thickness × CTE of the insulating resin of the first wiring board, the warp suppression effect may not be obtained. If the Young's modulus × thickness × CTE of the warp suppression layer 3 is more than 1.1 times the Young's modulus × thickness × CTE of the insulating resin of the first wiring board, the warp suppression effect may be excessive, and warping in the opposite direction may occur.

Young's modulus reflects the elastic properties of a material and is a value that indicates how difficult a material is to deform. It is also called the longitudinal elastic modulus or modulus of longitudinal elasticity. Young's modulus can be obtained by measurement using a universal material testing machine, thin film hardness meter, dynamic viscoelasticity measuring device, etc. It is desirable to use values for the Young's modulus of the warp suppression layer 3 and the Young's modulus of the insulating resin layer 4 using the same measurement method and temperature.

CTE is the rate of change in length per unit temperature change, and is also called the coefficient of thermal expansion or linear expansion. CTE is obtained by measurement using a thermomechanical analyzer or the like. It is also possible to use the average CTE in a certain temperature range as the CTE. It is desirable to use values at the same temperature or temperature range and to use the same measurement method for the CTE of the warp suppression layer 3 and the CTE of the insulating resin layer 4.

In the following, in one embodiment of the present invention, an example will be described in which the warp suppression layer 3 is made of the same resin as the insulating resin layer 4 and is formed to a thickness of 15 μm.

Next, as shown in FIG. 3(c), openings are provided in the insulating resin layer by photolithography. The openings may be subjected to plasma treatment in order to remove residues from development. The thickness of the insulating resin layer 4 is set according to the thickness of the conductor layer to be formed in the openings, and in one embodiment of the present invention, it is set to 7 μm, for example. The shape of the openings in plan view is set according to the pitch and shape of the bonding electrodes of the FC-BGA substrate, and in one embodiment of the present invention, it is set to an opening shape of φ80 μm, and the pitch is set to 150 μm, for example.

Next, the process for manufacturing the first wiring board 12 above the surface of the support body 1 will be described with reference to Figures 4 to 8. Note that Figures 4 to 8 use enlarged views of a portion of the central region of the support body 1 to explain an example of the process for forming multilayer wiring and the process for forming electrodes for bonding of the first wiring board of the present invention.

In FIG. 4(a), as explained in FIG. 3(c), a release layer 2 and an insulating resin layer 4 are formed above the surface of the support 1, and a warp suppression layer 3 is formed below the support 1.

4B, a seed layer 5 is formed on the release layer 2 in a vacuum. The seed layer 5 acts as a power supply layer for electrolytic plating in forming wiring. The seed layer 5 is formed by, for example, a sputtering method or a CVD method, and may be made of, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, _Ru , Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO, IZO, AZO, ZnO, PZT, TiN, _Cu3N4 , or a combination of these.

In this embodiment, taking into consideration electrical properties, ease of manufacture, and cost, a titanium layer and then a copper layer are formed in sequence by sputtering. The total thickness of the titanium and copper layers is preferably 1 μm or less as a power supply layer for electrolytic plating. In one embodiment of the present invention, Ti: 50 nm, Cu: 300 nm are used.

Next, as shown in FIG. 4(c), a conductor layer 6 is formed above the seed layer 5 by electrolytic plating. This conductor layer 6 will later become an electrode for bonding to the FC-BGA substrate 13. Types of electrolytic plating include electrolytic nickel plating, electrolytic copper plating, electrolytic chromium plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, and electrolytic iridium plating, but electrolytic copper plating is preferable because it is simple, inexpensive, and has good electrical conductivity.

The thickness of the electrolytic copper plating is desirably 1 μm or more, and 30 μm or less from the viewpoint of productivity, considering that the conductor layer 6 serves as an electrode for joining to the FC-BGA substrate 13 and is soldered. In one embodiment of the present invention, the openings of the insulating resin layer 4 are electrolytically plated with Cu to a thickness of 9 μm, and the upper part of the insulating resin layer 4 is electrolytically plated with Cu to a thickness of 2 μm.

Next, as shown in FIG. 4(d), the copper layer is polished by CMP (chemical mechanical polishing) or the like to remove the conductor layer 6 and the seed layer 5. In one embodiment of the present invention, the Cu: 2 μm of the conductor layer 6 on top of the insulating resin layer 4 and the seed layer 5 are removed by polishing. The conductor layer 6 remaining after polishing becomes an electrode for bonding to the FC-BGA substrate 13. In other words, in this embodiment, an electrode for bonding to the FC-BGA substrate 13 is formed by the damascene method.

Next, the wiring layer is formed. In one embodiment of the present invention, the wiring layer is formed by a semi-additive process (SAP). First, as shown in FIG. 5A(a), an insulating resin layer 4 is formed on the upper surface of the flat surface formed in FIG. 4(d) in the same manner as described in FIG. 4(a). The thickness of the insulating resin layer 4 is set according to the thickness of the conductor layer to be formed in the opening, and in one embodiment of the present invention, it is set to, for example, 2 μm.

The opening in the insulating resin layer 4 is formed so as to be bonded to the conductor layer 6, and in one embodiment of the present invention, it is formed as an opening with a diameter of, for example, 10 μm. This opening has the shape of a via portion that connects the upper and lower layers of the multilayer wiring.

Next, as shown in FIG. 5A(b), a seed layer 5 is formed in a vacuum in the same manner as described in FIG. 4(b).

Next, as shown in FIG. 5A(c), a resist pattern 7 is formed on the upper surface of the seed layer 5. After that, as shown in FIG. 5A(d), a conductor layer 6 is formed by electrolytic plating. The conductor layer 6 becomes the via portion and the wiring portion.

Types of electrolytic plating include electrolytic nickel plating, electrolytic copper plating, electrolytic chromium plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, and electrolytic iridium plating, but electrolytic copper plating is preferred because it is simple, inexpensive, and has good electrical conductivity.

The thickness of the electrolytic copper plating is desirably 0.5 μm or more from the viewpoint of electrical resistance of the wiring portion, and 30 μm or less from the viewpoint of productivity. In one embodiment of the present invention, Cu: 4 μm is formed in the opening of the insulating resin layer 4, and Cu: 2 μm is formed on the upper part of the insulating resin layer 4.

Then, the resist pattern 7 is removed as shown in FIG. 5B(e). Then, the unnecessary seed layer 5 is etched away as shown in FIG. 5B(f).

Then, by repeating the steps of FIG. 5A and FIG. 5B, a multi-layer wiring structure can be formed above the peeling layer 2. The example of FIG. 6 shows an example in which two wiring layers are formed.

If the warping of the substrate unit increases due to the multi-layering process, it is possible to increase the thickness of the warp suppression layer 3 as appropriate.

Next, as shown in FIG. 7, a conductor layer 6 is formed to serve as an electrode for bonding to the semiconductor element 11, and a substrate unit can be formed. The method for forming the bonding electrode is the same as the method for forming the wiring layer described above, but the thickness of the electrolytic copper plating differs between the bonding electrode and the wiring layer. It is desirable that the thickness of the electrolytic copper plating of the bonding electrode is 1 μm or more from the viewpoint of solder bonding, and 30 μm or less from the viewpoint of productivity. In one embodiment of the present invention, Cu: 9 μm is formed in the opening of the insulating resin layer 4, and Cu: 7 μm is formed on the upper part of the insulating resin layer 4.

Next, as shown in FIG. 8, in order to prevent oxidation of the surface of the conductor layer 6 and improve the wettability of the solder bumps, the substrate unit may be provided with a surface treatment layer 8. In an embodiment of the present invention, an electrolytic Ni/SnAg plating film is formed as the surface treatment layer 8. Note that an OSP (Organic Soiderability Preservative surface treatment with water-soluble preflux) film may be formed on the surface treatment layer 8. In addition, surface treatments such as Sn, SnAg, Ni/Sn, Ni/SnAg, Ni/Cu/Sn, Ni/Cu/SnAg, Ni/Au, and Ni/Pd/Au may be selected as appropriate for the purpose of electrolytic plating, and Ni/Au, Ni/Pd/Au, and Sn may be selected as electroless plating.

As a result, as shown in FIG. 1, the first wiring board 12 is completed on the support body, and a board unit 12A can be obtained in which multiple first wiring boards 12 are attached to the support body.

The wiring layer can be formed by the SAP (Semi Additive Process) method shown in Figures 5 to 8, or by the Damascene method. In the case of the Damascene method, after laminating an insulating resin layer, a pattern is formed by photolithography, and a seed layer is formed, followed by electrolytic copper plating. After electrolytic copper plating, a planarization process can be performed by CMP (Chemical Mechanical Polishing). The number of layers of the wiring layer is at least one, and may be set appropriately depending on the line width of the first wiring board.

Next, an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to Figures 9 to 13, which comprises a process for mounting a semiconductor element, a process for removing the support and the release layer, and a process for mounting to an FC-BGA substrate. Figures 9 to 13 are cross-sectional views limited to the area of the first wiring board 12 after singulation, in order to explain the details of the multiple first wiring boards placed above the support 1.

First, the mounting process of the semiconductor element 11 shown in Figure 9(a) will be described. In Figure 9(a), 9 is an electrode for mounting the semiconductor element, 10 is an electrode for bonding with the FC-BGA substrate, 12 is a first wiring substrate, and 14 is a solder joint between the semiconductor element and the first wiring substrate.

The semiconductor element 11 is mounted on the first wiring board 12 using mount and reflow, TCB (Thermal Compression Bonding), etc. For TCB, the TC-CUF (Thermal Compression Capillary Underfill) method, in which the first sealing resin 16 is injected by capillary action after soldering, a film-like bonding material (NCF), or a non-conductive paste (NCP), in which a liquid resin is placed before bonding and fills the space during bonding, may be used.

In the present invention, TC-CUF is used to inject the first sealing resin 16 after solder bonding as shown in FIG. 9(b), using capillary action. The mounting method of the semiconductor element 11 may be changed as appropriate, taking into consideration the size of the semiconductor element 11 and the equipment used for mounting. However, if the bonding pitch between the first wiring board 12 and the semiconductor element 11 is fine, it is preferable to select one of the TCB methods.

Next, as shown in FIG. 9(c), the semiconductor element 11 is sealed with a second sealing resin 17 to protect its side surface. The material used for the second sealing resin 17 is in the form of granules, liquid, or tablets, and is made of one of epoxy resin, silicon resin, acrylic resin, urethane resin, polyester resin, and oxetane resin, or a mixture of two or more of these resins, to which silica, titanium oxide, aluminum oxide, magnesium oxide, zinc oxide, or the like is added as a filler, and is formed by compression molding or transfer molding. The shape, composition, and forming method of the resin may be appropriately set according to the manner in which the first wiring board 12 is placed on the support 1. In the present invention, a liquid epoxy resin is used, and the resin is formed by compression molding.

Next, as shown in FIG. 9(d), the second sealing resin 17 is removed from the top surface of the semiconductor element 11 with respect to the first wiring board 12 sealed with the second sealing resin 17. If the second sealing resin 17 remains on the semiconductor element 11, warping may occur due to the influence of the CTE of the second sealing resin 17, and in some cases, peeling may occur at the interface between the first wiring board 12 and the second sealing resin 17. CMP, grinding, etc. can be used to remove the second sealing resin 17 from the semiconductor element 11. In the present invention, the second sealing resin 17 from the semiconductor element 11 is removed by grinding.

Next, the process of separating the first wiring board and the semiconductor element from the support 1 will be described with reference to FIG. 10. Note that in FIG. 10, the support 1 and the first wiring board 12 to which the semiconductor element after singulation shown in FIG. 9 is bonded are shown upside down.

When the peeling layer 2 can be peeled off by irradiation with laser light 19, since the support 1 is translucent, as shown in FIG. 10(a), the warp suppression layer 3 is irradiated with laser light 19 from the warp suppression layer 3 side. The laser light 19 passes through the warp suppression layer 3 and the support 1 and is irradiated to the peeling layer 2, making it possible to remove the support 1 as shown in FIG. 10(b). In one embodiment of the present invention, IR laser light of 1064 nm is used as the laser light 19. In one embodiment of the present invention, the support 1 is glass and translucent, and the resins used in the warp suppression layer 3, such as epoxy resin, polyimide resin, polybenzoxazole resin, and benzocyclobutene resin, have the property of transmitting IR laser, so the laser light passes through the warp suppression layer and the support and is irradiated to the peeling layer.

10(c), the release layer 2 is reliably removed by dry etching, solvent cleaning, ultrasonic cleaning, or the like to expose the electrodes 10 for bonding to the FC-BGA substrate 13. When dry etching is used, etching is performed using a gas containing at least one of the following gases: _O2 , Ar, _CF4, etc. When solvent cleaning is used, a solvent such as acetone, toluene, MEK, or methanol is used. When ultrasonic cleaning is used, removal is performed at an oscillation frequency in the range of 28 kHz to 1 MHz. The release layer 2 may be removed by a combination of one or more of these removal methods.

Next, solder is formed on the electrodes 10 for joining the first wiring board 12 to the FC-BGA board 13 shown in Figure 11. The solder is formed by forming an OSP (Organic Solderability Preservative, surface treatment with a water-soluble preflux) film on the electrode 10 for bonding to the FC-BGA substrate 13, or by electroless plating of Ni/Au, Ni/Pd/Au, or Sn, then printing the flux, mounting a solder ball, and then performing reflow; or by forming Sn, SnAg, Ni/Sn, Ni/SnAg, Ni/Cu/Sn, Ni/Cu/SnAg, or Sn by electrolytic plating, then printing the flux, and then mounting a solder ball; or by forming Sn, SnAg, Ni/Sn, Ni/SnAg, Ni/Cu/Sn, or Ni/Cu/SnAg by electrolytic plating, then performing reflow; or by directly printing a solder paste and performing reflow. In an embodiment of the present invention, Ni/Pd/Au is formed by electroless plating, then flux printing is performed, solder balls are mounted, and reflow is performed. This forms solder joints 15 between the first wiring board and the FC-BGA board, completing an assembly of the first wiring board 12 with the semiconductor element 11 fixed with the first sealing resin and the second sealing resin.

Next, the first wiring board 12 as an assembly after the balls are mounted is diced into pieces of size according to the shape of the support or wafer. Examples of dicing methods include blade dicing, laser dicing, and plasma dicing, but the method may be set as appropriate. In the present invention, blade dicing is used to diced into pieces of size.

Next, as shown in FIG. 12, a first wiring board 12 carrying an individual semiconductor element 11 is mounted on the FC-BGA board 13. The first wiring board 12 carrying the semiconductor element 11 is mounted on the FC-BGA board 13 using mount & reflow, TCB, or the like.

In this embodiment, a first wiring board 12 carrying a semiconductor element 11 is mounted on an FC-BGA substrate 13, and the FC-BGA substrate 13 and the first wiring board 12 carrying the semiconductor element 11 are soldered together using a mount and reflow method, and a third sealing resin 18 is injected into the gap between the FC-BGA substrate 13 and the first wiring board 12 by capillary action. As a result, a semiconductor device 20 of the present invention can be obtained, as shown in FIG. 13.

Although one embodiment of the present invention has been exemplified above, the present invention is not limited to the above embodiment, and it goes without saying that other layers and structures can be formed as desired for the purpose of improving other required physical properties such as rigidity, strength, and impact resistance, taking into consideration the use as a wiring board, as long as the technical concept of the embodiment of the present invention is not deviated from.

<Action and effect>
Next, the effects of using the above-described configuration of the substrate unit and the manufacturing method thereof will be described.

According to one aspect of the present invention, a method for forming a release layer and a fine wiring layer on a support, mounting and sealing a semiconductor element, and then peeling off the support substrate and mounting the semiconductor element on an FC-BGA substrate includes the steps of:
This makes it possible to suppress warping of the substrate unit and mount the semiconductor element with minimal warping.

Comparative Example
A configuration in which a substrate unit is manufactured without forming a warp suppression layer 3 below the support body will be described as a comparative example with reference to Fig. 14. Fig. 14 is a cross-sectional view showing a state in which a release layer 2 is formed on the upper surface of the support body 1, and a plurality of first wiring substrates 12 are formed on the upper surface of the release layer 2. The warp suppression layer 3 is not formed on the lower surface of the support body 1.

At this time, since the warp suppression layer 3 is not formed, warping may occur in the substrate unit 12B. Warping of the substrate unit 12B may cause mounting defects of the semiconductor element. Recent high-performance semiconductor elements have a large area, and semiconductor elements with a large area are more likely to cause mounting defects.

<Confirmation of action and effect>
To confirm the effect of this embodiment, a simulation model was created of the substrate unit 12A of the example and the substrate unit 12B of the comparative example. The size of the substrate unit was 300 mm square in both the example and the comparative example. A material with a Young's modulus of 1.5 GPa and a CTE of 65 ppm was used for the insulating resin of the first wiring substrate. The thickness of the insulating resin layer of the first wiring substrate was 17 μm in both the example and the comparative example. In the example, a warp suppressing layer 3 of 15 μm was formed on the lower surface of the support using the same material as the insulating resin of the first wiring substrate.

In the simulation model of the embodiment, the first wiring board was positioned above the support, and a downward convex warp with a height of 50 μm was calculated. On the other hand, in the simulation model of the comparative example, the first wiring board was positioned above the support, and a downward convex warp with a height of 400 μm was calculated. The effect of reducing warp was confirmed by forming the warp suppression layer 3.

The above-mentioned embodiment is merely an example, and other specific details of the structure can of course be modified as appropriate.

The present invention can be used in substrate units used to mount semiconductor elements on FC-BGA substrates.

1 Support 2 Release layer 3 Warp suppression layer 4 Insulating resin layer 5 Seed layer 6 Conductive layer 7 Resist pattern 8 Surface treatment layer 9 Electrode for mounting semiconductor element 10 Electrode for joining with FC-BGA substrate 11 Semiconductor element 12 First wiring substrate 12A Substrate unit of the present invention 12B Substrate unit of comparative example 13 FC-BGA substrate (second wiring substrate)
14: Solder joint between semiconductor element and first wiring board 15: Solder joint between first wiring board and FC-BGA board 16: First sealing resin 17: Second sealing resin 18: Third sealing resin 19: Laser light 20: Semiconductor device

Claims (13)

a substrate unit including a support and a plurality of first wiring substrates mounted on the support via a release layer,
an electrode for bonding at least one semiconductor element is provided on a first surface of the first wiring board;
an electrode for joining the first wiring board to a second wiring board is provided on a second surface of the first wiring board;
A substrate unit comprising a warp suppressing layer formed below the support body. The substrate unit according to claim 1, characterized in that the warp suppression layer is made of resin. The substrate unit according to claim 1 or 2, characterized in that the thickness of the warp suppression layer is 5 μm or more and 50 μm or less. The substrate unit according to any one of claims 1 to 3, characterized in that the warp suppression layer contains the same resin as the insulating resin of the first wiring substrate. The substrate unit according to any one of claims 1 to 4, characterized in that the thickness of the warp suppression layer is thinner than the thickness of the first wiring substrate. The substrate unit according to any one of claims 1 to 3, characterized in that the warp suppression layer contains a resin different from the insulating resin of the first wiring substrate. The substrate unit according to any one of claims 1, 2, 3, and 6, characterized in that the Young's modulus x thickness x CTE of the warp suppression layer is 0.9 to 1.1 times the Young's modulus x thickness x CTE of the insulating resin of the first wiring substrate. The substrate unit according to any one of claims 1 to 7, characterized in that the support is made of glass. The substrate unit according to claim 3, characterized in that the resin of the warp suppression layer is one or a mixture of two or more resins selected from epoxy resin, polyimide resin, polybenzoxazole resin, and benzocyclobutene resin. A method for manufacturing a substrate unit in which a plurality of first wiring substrates are placed above a support, comprising the steps of:
forming a release layer on an upper surface of the support;
forming a resin layer above the release layer;
forming a warp suppressing layer on the lower surface of the support;
forming an opening in the resin layer;
forming a seed layer over the resin layer and the opening;
forming an electrolytic plating layer above the seed layer;
a step of polishing the electrolytic plating layer and the seed layer until the resin layer is exposed, and forming an electrode for bonding to a second wiring board;
a step of repeatedly forming a resin layer and a conductor layer on the exposed upper surfaces of the resin layer and the electrodes to obtain a multilayer wiring;
forming an electrode for bonding a semiconductor element to an outermost surface of the multilayer wiring;
A method for manufacturing a substrate unit, comprising: A method for manufacturing a semiconductor device using the substrate unit according to any one of claims 1 to 9,
bonding the semiconductor element to the first wiring substrate;
sealing a gap between the first wiring substrate and the semiconductor element with a first sealing resin;
sealing the first wiring substrate and the side surfaces of the semiconductor element with a second sealing resin;
peeling the first wiring substrate from the support;
obtaining an assembly in which the semiconductor element is bonded to the first wiring substrate;
a step of dividing the assembly into individual first wiring substrates; and a step of bonding the first wiring substrate to the second wiring substrate.
sealing a gap between the first wiring substrate and the second wiring substrate with a third sealing resin;
2. A method for manufacturing a semiconductor device comprising the steps of: In the step of peeling off the first wiring substrate from the support,
12. The method for manufacturing a semiconductor device according to claim 11, further comprising the step of irradiating the warp suppression layer with laser light. The method for manufacturing a semiconductor device according to claim 12, characterized in that the laser light is an IR laser light.

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