JP2005123388A - ボンディング構造及びボンディング方法、並びに半導体装置及びその製造方法 - Google Patents
ボンディング構造及びボンディング方法、並びに半導体装置及びその製造方法 Download PDFInfo
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- JP2005123388A JP2005123388A JP2003356433A JP2003356433A JP2005123388A JP 2005123388 A JP2005123388 A JP 2005123388A JP 2003356433 A JP2003356433 A JP 2003356433A JP 2003356433 A JP2003356433 A JP 2003356433A JP 2005123388 A JP2005123388 A JP 2005123388A
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- Wire Bonding (AREA)
Abstract
【解決手段】 第1ボンド部に接続後の金属ワイヤ2を引き出して第2ボンド部に接続する際に、金属ワイヤ2をキャピラリーの一方の下端線1aで押し付けてICチップ4の電極パッド3に仮圧着してから、キャピラリー1の他方の下端縁1aで金属ワイヤ2を折り重なるように折り返し、この折り返し部20において仮圧着部6aと同じ位置に本圧着6bすることにより、折り返し部20における金属ワイヤ2の厚みが増すため、この厚みによってキャピラリー1の押圧力が吸収され、電極パッド3の下部等にダメージを与えることもなく、接合強度が向上する。
【選択図】 図1
Description
前記第1の導電層に前記導線を接続する工程と、
前記導線を前記第2の導電層上に導びき、前記導線を折り重ねるように折り返す工程 と、
少なくともこの折り返し部分にて前記導線を前記第2の導電層に接続する工程と
を有することを特徴とする、ボンディング方法(以下、本発明のボンディング方法と称する。)に係るものである。
図1及び図2は、本実施の形態のボンディング構造を示し、従来例として示した図14に対応するプロセスの概略図である。なお、理解容易のために接続する部分を電極パッド同士として説明するが、それ以外のものでもよく、例えば、電極パッドとリードフレーム、または基板上の導電パターンとの間の接続等何でもよい。後述する他の実施の形態も同様である。
図3及び図4は本実施の形態のボンディング構造を示し、実施の形態1に対応するプロセスの概略図である。
図5〜図8は本実施の形態のボンディング方法を示す概略図である。上記した実施の形態では、ワイヤボンディング後に金属ワイヤを切断していたが、これを切断しないで中継ボンドした例であり、いずれも上記した実施の形態1又は2のボンディング構造を適用し、同一のICチップ上又はプリント基板とICチップ間において、電極パッド3ヶ所を中継ボンドして結線した例である。
3、14…電極パッド、4…ICチップ、5…貫通孔、6…圧接部、6a…仮圧着部、
6b…本圧着部、7…圧痕、8…金属バンプ、9…ボール、10…プリント基板、
11…ボールボンド、12…ウェッジボンド、13…折り返しボンド、
13A…中継ボンド、15…層間膜、16…パッシベーション膜、17…クランパー、
19…モールド樹脂、20…折り返し部、25…押圧部、P…圧力
Claims (26)
- 第1の導電層と第2の導電層との間を導線で接続したボンディング構造において、前記第1の導電層に前記導線が接続されると共に、前記第2の導電層上で前記導線が折り重なるように折り返された状態で、少なくともこの折り返し部分にて前記導線が前記第2の導電層に接続されていることを特徴とする、ボンディング構造。
- 前記導線が前記第2の導電層に仮圧着され、前記折り返し部分にて前記第2の導電層に本圧着されている、請求項1に記載したボンディング構造。
- 前記仮圧着と前記本圧着とが同一位置又は異なる位置で行われている、請求項2に記載したボンディング構造。
- 前記第2の導電層への接続状態で前記導線が切断されている、請求項1に記載したボンディング構造。
- 前記第2の導電層への接続後にこの接続部分を中継して、前記導線が第3の導電層上に導びかれてこの第3の導電層に接続されている、請求項1に記載したボンディング構造。
- 前記第3の導電層上において、前記導線が折り重なるように折り返された状態で接続されている、請求項5に記載したボンディング構造。
- 前記第1の導電層及び前記第2の導電層が共に半導体チップ上の電極である、請求項1に記載したボンディング構造。
- 前記第1の導電層が実装基板上の電極又はこの実装基板に実装された半導体チップ上の電極であり、前記第2の導電層が前記半導体チップ上の電極又は前記実装基板上の電極である、請求項1に記載したボンディング構造。
- 前記半導体チップの複数個が実装基板上に並置又は積層されている、請求項7又は8に記載したボンディング構造。
- 前記実装基板上の前記第1の導電層に前記導線が接続され、この導線が前記半導体チップ上の前記第2の導電層に接続され、更にこの接続部分から前記実装基板上の導電層に接続されている、請求項8に記載したボンディング構造。
- 前記導線がボンディングワイヤであり、前記第1の導線層上でボールボンディングされている、請求項7又は8に記載したボンディング構造。
- システム・イン・パッケージ(SiP)又はシステム・オン・チップ(SoC)に適用される、請求項1に記載したボンディング構造。
- 第1の導電層と第2の導電層との間を導線で接続するボンディング方法において、
前記第1の導電層に前記導線を接続する工程と、
前記導線を前記第2の導電層上に導びき、前記導線を折り重ねるように折り返す工程 と、
少なくともこの折り返し部分にて前記導線を前記第2の導電層に接続する工程と
を有することを特徴とする、ボンディング方法。 - 前記導線を前記第2の導電層に仮圧着し、前記折り返し部分にて前記第2の導電層に本圧着する、請求項13に記載したボンディング方法。
- 前記仮圧着と前記本圧着とを同一位置又は異なる位置で行う、請求項14に記載したボンディング方法。
- 前記第2の導電層への接続状態で前記導線を切断する、請求項13に記載したボンディング方法。
- 前記第2の導電層への接続後にこの接続部分を中継して、前記導線を第3の導電層上に導びいてこの第3の導電層に接続する、請求項13に記載したボンディング方法。
- 前記第3の導電層上において、前記導線を折り重ねるように折り返した状態で接続する、請求項17に記載したボンディング方法。
- 前記第1の導電層及び前記第2の導電層を共に半導体チップ上の電極とする、請求項13に記載したボンディング方法。
- 前記第1の導電層を実装基板上の電極又はこの実装基板に実装された半導体チップ上の電極とし、前記第2の導電層を前記半導体チップ上の電極又は前記実装基板上の電極とする、請求項13に記載したボンディング方法。
- 前記半導体チップの複数個を前記実装基板上に並置又は積層する、請求項19又は20に記載したボンディング方法。
- 前記実装基板上の前記第1の導電層に前記導線を接続し、この導線を前記半導体チップ上の前記第2の導電層に接続し、更にこの接続部分から前記実装基板上の導電層に接続する、請求項20に記載したボンディング方法。
- 前記導線がボンディングワイヤであり、前記第1の導線層上でボールボンディングする、請求項19又は20に記載したボンディング方法。
- システム・イン・パッケージ(SiP)又はシステム・オン・チップ(SoC)に適用する、請求項13に記載したボンディング方法。
- 請求項1〜12のいずれか1項に記載したボンディング構造を有する半導体装置。
- 請求項13〜24のいずれか1項に記載したボンディング方法を用いる半導体装置の製造方法。
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