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EP4143882A1 - Procédé de fabrication de non-et 3d avec un alliage de nickel ou de cobalt - Google Patents

Procédé de fabrication de non-et 3d avec un alliage de nickel ou de cobalt

Info

Publication number
EP4143882A1
EP4143882A1 EP21721551.6A EP21721551A EP4143882A1 EP 4143882 A1 EP4143882 A1 EP 4143882A1 EP 21721551 A EP21721551 A EP 21721551A EP 4143882 A1 EP4143882 A1 EP 4143882A1
Authority
EP
European Patent Office
Prior art keywords
metal
nickel
cavities
agent
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP21721551.6A
Other languages
German (de)
English (en)
Inventor
Dominique Suhr
Vincent Mevellec
Mikaïlou THIAM
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aveni SA
Original Assignee
Aveni SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aveni SA filed Critical Aveni SA
Publication of EP4143882A1 publication Critical patent/EP4143882A1/fr
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601—Process or apparatus
    • C23C18/1603—Process or apparatus coating on selected surface areas
    • C23C18/1607—Process or apparatus coating on selected surface areas by direct patterning
    • C23C18/1608—Process or apparatus coating on selected surface areas by direct patterning from pretreatment step, i.e. selective pre-treatment
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601—Process or apparatus
    • C23C18/1603—Process or apparatus coating on selected surface areas
    • C23C18/1607—Process or apparatus coating on selected surface areas by direct patterning
    • C23C18/1612—Process or apparatus coating on selected surface areas by direct patterning through irradiation means
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601—Process or apparatus
    • C23C18/1633—Process of electroless plating
    • C23C18/1646—Characteristics of the product obtained
    • C23C18/165—Multilayered product
    • C23C18/1653—Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/18—Pretreatment of the material to be coated
    • C23C18/1851—Pretreatment of the material to be coated of surfaces of non-metallic or semiconducting in organic material
    • C23C18/1872—Pretreatment of the material to be coated of surfaces of non-metallic or semiconducting in organic material by chemical pretreatment
    • C23C18/1875—Pretreatment of the material to be coated of surfaces of non-metallic or semiconducting in organic material by chemical pretreatment only one step pretreatment
    • C23C18/1879—Use of metal, e.g. activation, sensitisation with noble metals
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/31—Coating with metals
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/31—Coating with metals
    • C23C18/32—Coating with nickel, cobalt or mixtures thereof with phosphorus or boron
    • C23C18/34—Coating with nickel, cobalt or mixtures thereof with phosphorus or boron using reducing agents
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/31—Coating with metals
    • C23C18/32—Coating with nickel, cobalt or mixtures thereof with phosphorus or boron
    • C23C18/34—Coating with nickel, cobalt or mixtures thereof with phosphorus or boron using reducing agents
    • C23C18/36—Coating with nickel, cobalt or mixtures thereof with phosphorus or boron using reducing agents using hypophosphites
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/38—Electroplating: Baths therefor from solutions of copper

Definitions

  • the present invention relates to the field of semiconductors, in particular to three- dimensional devices such as for example three-dimensional vertical NAND memories.
  • 3D NAND memory devices consist of a semiconductor substrate on which is arranged a stack of alternating layers of conductive material, called "word lines", which are metallic in nature, and layers of insulating material made of an inorganic dielectric. On the sides of the device, the stack may be etched in a "staircase" pattern, with the length of the layers and the number of layers decreasing from one stage to the next in the upward direction.
  • the conductor/insulator stack is perforated with polysilicon semiconductor channels over its entire height.
  • a liner - consisting of a tunneling dielectric, usually Si0 2 , a charge storage material such as silicon nitride, and an inorganic oxide blocking dielectric - is interposed between each semiconductor channel and the conductor/insulator stack to create a three-dimensional array of memory cells, each cell being located at the intersection of the channel and a word line.
  • word lines are created by simultaneously filling several rows of long, thin horizontal cavities separated by insulating layers, the most commonly used conductive material being tungsten.
  • Tungsten is usually deposited in two steps: an atomic layer deposition (ALD) step to create a thin cling layer, followed by a chemical vapor deposition (PECVD) step to completely fill the cavities.
  • ALD atomic layer deposition
  • PECVD chemical vapor deposition
  • the further down the stack one goes the more difficult it becomes to fill them completely.
  • This problem is amplified when the word lines to be fabricated are thinner and the cavity opening is smaller.
  • material voids are formed in the tungsten deposits, which leads to conductivity losses and memory malfunctions.
  • This filling technology has shown its limits, especially for stacks comprising 96 or 128 word lines.
  • the invention responds to these various needs by replacing metals such as tungsten used in the prior art to fabricate 3D NAND devices, with a nickel or cobalt alloy containing an element selected from boron, phosphorus, tungsten or a mixture thereof.
  • the invention also responds to these various needs by providing a process for fabricating 3D NAND memory in which the step of deposition of the conductive metal at the stage of creating word lines, bit lines or contacts between semiconductor channels and bit lines, uses a wet process, whereas it is obtained exclusively by a dry process in the prior art.
  • the step of deposition of the conductive metal is carried out in two steps: a first step consisting in surface activation of an inorganic oxide with a noble metal, followed by a second step consisting in deposition of a metal on the activated inorganic oxide surface by bringing said surface into contact, in the absence of polarization, with an electroless solution comprising metal ions and a reducing agent of metal ions.
  • This process consists in depositing a nickel and boron alloy by an electroless process (without electrical polarization of the substrate).
  • the process of the invention has the specific feature of producing a metal deposit via a wet process using an aqueous electrolyte, and not via a dry process as is the case in the prior art.
  • the process of the invention makes it possible to fill structures with a high number of lines. The particular filling kinetics observed in this process allows a metal growth rate adapted to these new dimensions. This result is obtained in particular by the nature of the chemical species entering the composition of the electrolyte.
  • the process of the invention makes it possible to deposit a metal layer directly on an inorganic dielectric material.
  • the process of the invention also makes it possible to avoid the deposition of a barrier layer, generally of titanium nitride or tantalum nitride, more commonly of titanium nitride.
  • a barrier layer generally of titanium nitride or tantalum nitride, more commonly of titanium nitride.
  • the absence of a barrier material provides two advantages: eliminating a step in the process without reducing the conductivity of the metal lines.
  • the inventors found that the nickel-boron alloy does not diffuse into the dielectric.
  • the nickel- boron alloy used as a conductor instead of tungsten has not only barrier properties, but also higher conductivity than tungsten.
  • the invention therefore provides a method for fabricating a 3D NAND memory comprising at least one process of selective metallization of an inorganic oxide surface in the solvent phase, the metallization being carried out by depositing an alloy of nickel or cobalt with an element selected from boron, phosphorus and tungsten, said metallization process comprising
  • Alloy means a solid solution in which the element is homogeneously dispersed in nickel or cobalt.
  • the alloy deposition step can advantageously be performed by subjecting the inorganic oxide surface to ultrasound.
  • the element selected from boron, phosphorus and tungsten preferably represents between 1 and 10 atomic % in the alloy.
  • the metal deposit preferably consists of an alloy of nickel with at least one element selected from boron, phosphorus and tungsten, wherein the element may be between 1 atomic % and 10 atomic %.
  • the metal consists of a nickel-boron alloy containing 6 atomic % boron.
  • the inorganic oxide with which the electroless solution is brought into contact may be Si0 2 or Al 2 0 3 .
  • the nickel or cobalt alloy deposit may be formed at various stages of the 3D NAND memory fabrication process. For example, the alloy is deposited to form a word line, to form a contact between a polysilicon channel and a bit line, or to form the barrier layer of a bit line.
  • the noble metal can be ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), gold (Au) or silver (Ag).
  • the noble metal used to activate the inorganic oxide surface is palladium.
  • Another object of the invention is a 3D NAND device comprising an alloy of nickel or cobalt with at least one element selected from boron, phosphorus, and tungsten, which device may be fabricated by any of the methods described above.
  • the present application also describes a process for metallizing a semiconductor substrate, said substrate comprising at least one horizontal cavity opening onto a vertical cavity, the horizontal cavity having a smaller opening size than the vertical cavity, said cavities defining a surface comprising at least one area of an inorganic oxide, said metallization process comprising a step of selectively activating the inorganic oxide surface, followed by a step of depositing a metal on the activated inorganic oxide surface by bringing said surface into contact, in the absence of polarization, with an electroless solution comprising metal ions, a reductant of such ions, a suppressor adapted to the horizontal cavity and a suppressor adapted to the vertical cavity.
  • the invention also provides an electrolyte for filling cavities with an opening size of less than 1 micron or even 100 nm.
  • the invention also provides an electrolyte for the fabrication of a 3D NAND memory.
  • This electrolyte makes it possible to create metal deposits on substrates with very different topographies in terms of both size and relief. It is therefore not necessary to use a different metallization technique depending on the starting substrate to be covered: this simplifies the fabrication process of the memory device.
  • the electrolyte allows for a complex substrate comprising several cavities having different dimensions - in particular different widths (or dimensions) at the opening - a simultaneous filling of all the cavities, with a single solution comprising metal ions and a reducing agent of metal ions to deposit a metal in the cavities. This process makes it possible to obtain a metal deposit without material defects on a surface with a very irregular topographic relief.
  • the invention leads to dielectric/metal multilayer structures with excellent interlayer adhesion.
  • the electrolyte and the metallization process of the invention also make it possible to form metal deposits of homogeneous quality on complex geometries.
  • the conductivity of the network of conductive lines in the device is improved due to the elimination - between the conductive metals and the dielectrics - of barrier layers which are necessary in the prior art to ensure proper operation of the device.
  • Figure 1 shows a schematic portion of a 3D NAND memory according to the prior art.
  • FIG. 2A Figure 2A shows a substrate used to implement a metallization process of the prior art or a metallization process of according to the invention to create word lines.
  • Figure 2B shows a step of etching the substrate of Figure 2A.
  • Figure 2C shows the substrate covered with the nickel or cobalt alloy obtained by carrying out the metallization process according to the invention.
  • Figure 2D shows nickel or cobalt alloy word lines of a 3D NAND device obtained by implementing the metallization process according to the invention.
  • Figure 3 shows a cross-section along the axis B-B' of Figure 1 of a 3D NAND device of the prior art.
  • Figure 4A shows a substrate to be metallized with a nickel or cobalt alloy by the process of the invention.
  • Figure 4B shows the substrate of Figure 4A which has been metallized according to the process of the invention to obtain a deposit of nickel or cobalt alloy filling the cavities to form word lines.
  • Figure 5 shows the substrate of Figure 4A which has been metallized according to the process of the invention to obtain a deposit of nickel or cobalt alloy covering the walls of the cavities without filling them.
  • Figure 6 shows a substrate used to fabricate peripheral contacts according to a process of the invention or according to a process of the prior art.
  • Figure 7 shows the substrate of Figure 6 that has been etched upstream of a metallization.
  • Figure 8 shows the substrate of Figure 7 metallized according to the process of the invention with a nickel or cobalt alloy.
  • Figure 9 shows the substrate of Figure 7 metallized with a barrier material and tungsten according to a process of the prior art.
  • Figure 10 shows a substrate used to fabricate contacts between semiconductor channels and bit lines according to a process of the invention or a process of the prior art.
  • Figure 11 shows the substrate of Figure 10 which has been etched to define cavities to be filled with metal according to a process of the invention or a process of the prior art.
  • Figure 12 shows the substrate of Figure 11 metallized with a nickel or cobalt alloy according to the process of the invention.
  • Figure 13 shows the substrate of Figure 11 metallized with a barrier material and tungsten according to a process of the prior art.
  • FIG. 14 shows a schematic detail of a 3D NAND device comprising bit lines based on a nickel or cobalt alloy obtained according to the process of the invention.
  • Figure 15 shows a schematic detail of a 3D NAND device comprising copper-based bit lines according to the prior art.
  • Figure 16 shows the absence of bowing of a metallized silicon substrate obtained according to the process of the invention in comparison with a metallized silicon substrate of the prior art.
  • Figure 17 shows the EELS profile of a nickel-boron alloy obtained according to the process of the invention.
  • a first object of the invention is a method for fabricating a 3D NAND memory comprising a process of selectively metallizing an inorganic oxide surface in the solvent phase with an alloy of nickel or cobalt with an element selected from boron, phosphorus and tungsten or a mixture thereof, said metallization process comprising
  • the fabrication method of the invention may be part of a more global integration scheme of a 3D NAND memory in which the conductive and dielectric materials are assembled and deposited according to particular geometries making it possible to create functional elements including word lines, contacts between polysilicon channels and bit lines, peripheral contacts between word lines and source lines, and bit lines.
  • the nickel or cobalt alloy may be used in the composition of various functional elements and deposited at various stages of the 3D NAND memory integration scheme.
  • the nickel or cobalt alloy deposit is included in the composition of a word line of the 3D NAND memory.
  • the alloy deposition can thus be obtained by a solvent phase metallization process of a semiconductor substrate intended for the fabrication of a 3D NAND memory, said substrate defining a horizontal plane and having at least two series of horizontal cavities opening onto a vertical cavity, said cavities defining a surface comprising at least one area of an inorganic oxide, said metallization process comprising
  • the electroless solution may further contain at least one first suppressor adapted to the horizontal cavities and at least one second suppressor adapted to the vertical cavity.
  • the first suppressor may be an aliphatic polyamine with a number-average molecular weight of less than 500 g/mol, for example dipropylene triamine.
  • the second suppressor may be a polyethyleneimine of number-average molecular weight greater than or equal to 500 g/mol.
  • the reducing agent may be hypophosphorous acid, and the electroless solution may contain at least two reducing agents, a first reducing agent being hypophosphorous acid, and a second reducing agent being dimethylamino borane.
  • the concentration of metal ions is between 10 3 M and 1 M and the concentration of the first suppressant ranges from 5 mg/I to 100 mg/I.
  • the horizontal cavities have, for example, an average diameter at the opening ranging from 10 nm to 50 nm and a depth ranging from 30 nm to 80 nm.
  • the inorganic oxide consists of Si0 2 and/or Al 2 0 3 .
  • the invention also provides a process for fabricating a 3D NAND memory comprising
  • a step of depositing a metal on the activated inorganic oxide surface by bringing said surface into contact, in the absence of polarization, with an electroless solution comprising metal ions, at least one reducing agent of metal ions, at least one first aliphatic polyamine with a molecular weight ranging from 500 g/mol to 25 000 g/mol and at least one second aliphatic polyamine with a molecular weight lower than that of the first polyamine.
  • the invention provides a process for the solvent phase and electroless metallization of a semiconductor substrate comprising cavities whose average width at the opening is less than 1 micron, said cavities defining a surface comprising at least one area of an insulating material, said metallization process comprising
  • step - a step of activating the surface of the insulating material by bringing the surface into contact with an activation solution comprising at least one palladium complex, at least one bifunctional binder, and at least one solvent, followed by
  • metal ions such as Ni(II) or Co(II) ions, hypophosphorous acid and dipropylenetriamine.
  • the ratio of the molar concentration between the metal ions and the dipropylene triamine is preferably greater than 10:1.
  • the width at the opening of the cavities is preferably less than 500 nm, for example less than a value selected from the group consisting of 400 nm, 300 nm, 200 nm, 100 nm and 50 nm.
  • the process of the invention in all of its particular aspects and embodiments comprises a step of activating a surface of an inorganic dielectric material on which a metal is then deposited.
  • the dielectric material may be an inorganic oxide, preferably selected from silicon dioxide (Si0 2 ), alumina (Al 2 0 ), hafnium oxide, zirconium oxide and silicates thereof.
  • the substrate comprises cavities whose available surface area comprises insulating areas, all of which insulating areas consist of silicon oxide and/or aluminum oxide. All of the insulating areas have silicon oxide surfaces or aluminum oxide surfaces. Alternatively, some of the insulating areas have silicon oxide surfaces while the other part of the insulating areas have aluminum oxide surfaces.
  • the surface of the dielectric material in particular the inorganic oxide, may be activated in the solvent phase in a step prior to being covered by the metal deposited by electroless methods in the solvent phase.
  • Surface activation may be achieved, for example, by grafting a noble metal such as palladium according to the teaching of documents FR 2 950 063-A1 or FR 2 950 634-A1.
  • a noble metal such as palladium according to the teaching of documents FR 2 950 063-A1 or FR 2 950 634-A1.
  • the principle of grafting is to bring palladium in the form of a complex in solution and in the presence of a bifunctional ligand.
  • the nature of the ligand used depends on the nature of the dielectric to be activated.
  • the surface activation of the insulating layer can also be performed by depositing nanoparticles of a metal, such as nickel boron nanoparticles as described in WO 2010/001054.
  • the surface activation is carried out by means of an activation solution containing a solvent, a palladium complex used as an activator, and a bifunctional binder such as an organosilane compound fulfilling the function of adhesion promoter.
  • the activator may consist of one or more palladium complex(es) such as (NH 4 ) 2 (PdCU); Pd(NH 3 ) 4 or the complexes of formula (I). wherein:
  • R1 and R2 are identical and represent H; CH 2 CH 2 NH 2 ; CH 2 CH 2 OH; or R1 represents H and R2 represents CH 2 CH 2 NH 2 ; or R1 represents CH 2 CH 2 NH 2 and R2 represents CH 2 CH 2 NHCH 2 CH 2 NH 2 ; or R1 represents H and R2 represents CH 2 CH 2 NHCH 2 CH 2 NHCH 2 CH 2 NH 2
  • - X is a ligand selected from the group consisting of Cl ; Br ⁇ ; G; H 2 0, N0 3 ⁇ ; CH 3 S0 3 ; CF 3 S0 3 ⁇ ;
  • this solution comprises the aforementioned activator in a concentration of 10 6 M to 10 ⁇ 2 M, preferably 10 5 M to 10 3 M, more preferably 5.10 s M to 5.10 4 M.
  • the adhesion promoter consisting of one (or more) organosilane compound(s) within the activation solution ensures the adhesion between the metal top layer and the inorganic oxide.
  • the organosilane compound has the general formula (Va):
  • X represents a functional group selected from the group consisting of thiol, pyridyl, epoxy (oxacyclopropanyl), glycidyl, primary amine and capable of reacting with simple palladium compounds or of formula (I);
  • - L represents a spacer arm selected from the group consisting of CH 2 ; CH 2 CH 2 ; CH 2 CH 2 CH 2 -;
  • - R represents a group selected from the group consisting of CH 3 , CH 3 CH 2 , CH 3 CH 2 CH 2 ,
  • - n is an integer equal to 2 or 3.
  • the organosilane compound may also have the formula (Vb)
  • L represents a spacer arm selected from the group consisting of
  • - R represents a group selected from the group consisting of CH 3 , CH 3 CH 2 , CH 3 CH 2 CH 2 , (CH 3 ) 2 CH.
  • Compounds of formulas (Va) or (Vb) are for example selected from the following compounds: (3-Aminopropyl)triethoxysilane; (3-Aminopropyl)trimethoxysilane; m-
  • X represents an NH 2 group and L represents CH 2 CH 2 CH 2 - and R represents CH 3 (compound named (3-aminopropyl)-trimethoxy-silane or APTMS); or L represents CH 2 CH 2 CH 2 - and R represents CH 3 CH 2 (a compound named (3-aminopropyl)-triethoxy-silane or APTES); or L represents CH 2 CH 2 NHCH 2 CH 2 and R represents CH 3 (a compound named [3- (2-aminoethyl)aminopropyl] trimethoxy-silane or DATMS or DAMO).
  • X represents SH; L represents CH 2 CH 2 CH 2 - and R represents CH 2 -CH 3 (compound named (3- Mercaptopropyl)trimethoxysilane or MPTES); or X represents C 6 H 5 N; L represents CH 2 CH 2 - and R represents CH 2 -CH 3 (compound named 2 -(4-Pyridylethyl )triethoxysi la ne or PETES); or X represents CHCH 2 0; L represents CH 2 CH 2 CH 2 and R represents CH 3 (compound named (3- Glycidoxypropyl)trimethoxysilane or EPTMS) or X represents Cl; L represents CH 2 CH 2 CH 2 and R represents CH 3 (compound named 3-Chloropropyltrimethoxysilane or CPTMS).
  • a particularly preferred organosilane compound in the context of the present invention is (3-aminopropyl)-trimethoxy silane (APTMS).
  • the concentration of the organosilane compound is between 10 ⁇ 5 M and 10 1 M, preferably between 10 ⁇ 4 M and 10 ⁇ 2 M, more preferably between 5.10 4 M and 5.10 3 M.
  • the aforementioned activation solution comprises a very small amount of water.
  • the water may be present in a concentration of less than 1%, preferably less than 0.5% and even more preferably less than 0.2% by volume.
  • the solvent of the solution must be capable of solubilizing the activator and the binder defined above.
  • This solvent system may consist of one or more solvent(s) selected from the group consisting of N-methylpyrrolidinone (NMP), dimethylsulfoxide (DMSO), alcohols, ethylene glycol ethers such as, for example, monoethyl -d iethylene glycol (EDEG), propylene glycol ethers, dioxane and toluene.
  • NMP N-methylpyrrolidinone
  • DMSO dimethylsulfoxide
  • alcohols ethylene glycol ethers
  • EDEG monoethyl -d iethylene glycol
  • propylene glycol ethers dioxane and toluene.
  • the solvent system advantageously consists of a mixture of a solvent capable of solubilizing the palladium compounds in combination with a solvent such as an ethylene glycol ether or a propylene glycol ether.
  • a particularly preferred solvent system in the context of the present invention is dimethylsulfoxide (DMSO) alone or a mixture of dimethylsulfoxide (DMSO) and diethylene glycol monoethyl ether (EDEG). These compounds may be used in a volume ratio of between 1:200 and 1:5, preferably about 1:10.
  • the surface of an insulating substrate comprising silicon dioxide or aluminum oxide may be activated with a palladium complex such as a palladium-diethylene triamine complex, using aminopropyl-trimethoxy-silane as a bifunctional organic binder.
  • a palladium complex such as a palladium-diethylene triamine complex, using aminopropyl-trimethoxy-silane as a bifunctional organic binder.
  • the process of the invention includes a step of metallizing the inorganic oxide substrate. This step is carried out after the step of activating the substrate with a bifunctional palladium/ligand complex system, or by deposition of metal nanoparticles.
  • a metal selected from the noble and transition metals, as well as their alloys, will be used. Palladium is a particular example of the invention.
  • the metal ions are for example nickel (II) ions or cobalt (II) ions.
  • the metal may be alloyed with at least one other element selected from phosphorus and boron.
  • a particular embodiment of the invention uses nickel alloyed with boron.
  • the coating of the surface is carried out by bringing this surface into contact with a liquid, preferably aqueous, solution containing:
  • At least one metal salt preferably in a concentration of between 10 3 M and 1 M;
  • an agent having a suppressive effect for vertical cavities preferably in a concentration of between 0.5 ppm and 100 ppm
  • an agent or mixture of agents having a suppressive effect for horizontal cavities preferably in a concentration of between 0.5 ppm and 100 ppm.
  • the electrolyte optionally contains at least one stabilizing agent of metal ions, preferably in an amount between 10 ⁇ 3 M and 1 M.
  • the contact of the electroless solution with the surface is carried out, for example, under conditions that allow the formation of a metal film having a thickness of at least 5 nanometers, for example, under conditions that allow the formation of a metal film having a thickness of at least 30 nanometers, preferably between 30 nanometers and 100 nanometers, more preferably between 30 nanometers and 200 nanometers.
  • the thickness of the film is at least equal to the depth of the cavities, preferably between 30 nanometers and 100 nanometers.
  • the metal film advantageously has a thickness at least equal to the depth of the horizontal cavities and less than half the diameter of the vertical cavity, so that the latter is not completely filled.
  • the metal salt of the aforementioned metal is preferably water-soluble and selected from the group consisting of acetate, acetylacetonate, hexafluorophosphate, nitrate, perchlorate, sulfate or tetrafluoroborate of said metal.
  • a preferred metal salt in the context of the present invention is nickel sulfate hexa hydrate.
  • the aforementioned reducing agents may be selected from phosphorus derivatives and borane derivatives.
  • a phosphorus derivative may be hypophosphorous acid or a salt thereof, while a borane derivative may be selected from dimethylaminoborane, pyridine borane, morpholene borane or terbutylamine borane.
  • a preferred mixture of reducing agents in the context of the present invention comprises a borane derivative such as in particular dimethylamino borane (DMAB) and a phosphorus derivative such as in particular hypophosphorous acid.
  • the nature and amount of the stabilizing agent, when present, are selected to complex the metal ions in the solution.
  • the electroless solution contains complexes of a metal ion and a ligand, also called stabilizing agent.
  • the stabilizing agent of metal ions may be selected from the group consisting of ethylene diamine, citric acid, acetic acid, succinic acid, malonic acid, amino acetic acid, malic acid or an alkali metal salt of these compounds.
  • a preferred stabilizing agent in the context of the present invention is citric acid, and forms complexes with the metal ions in the solution.
  • the aqueous electroless solution may include an agent to adjust the pH to a value between 6 and 11.
  • the pH of the solution be selected such that not all of the amine functions of these amines are protonated.
  • the pH of the aqueous solution will preferably be in the range of from 8 to 10. In particular, it may be in the range of from 9.0 to 9.5.
  • a pH adjusting agent may be selected from aminoethanol, N- methyl aminoethanol and N,N-dimethyl aminoethanol.
  • a preferred pH adjusting agent is N- methyl aminoethanol.
  • the electroless solution contains a poly(ethyleneimine) homopolymer or copolymer, which can perform the function of a suppressor capable of adsorbing to the nickel or cobalt alloy, and in particular is selectively adapted to vertical cavities.
  • "Selectively adapted” means a suppressor which is not adapted to horizontal cavities.
  • An agent having a suppressive effect for vertical cavities may also be selected from polymers and copolymers derived from chitosans, poly(allyl amines), poly(vinyl amines), poly(vinyl pyridines), poly(a m i no-styrene), poly(L-lysine), and acidic (or protonated) forms of these polymers.
  • a linear poly(ethyleneimine) with a number-average molecular weight Mn of from 500 g/mol to 25 000 g/mol which comprises -(CH 2 -CH 2 -NH)- units or a branched polyethyleneimine with a number-average molecular weight Mn of from 500 g/mol to 70 000 g/mol which comprises primary amine, secondary amine and tertiary amine units is selected.
  • the poly(ethyleneimine) may be a poly(ethyleneimine) with CAS number 25987-06- 8, having for example a number-average molecular weight Mn between 500 and 700 g/mol with product code 408719 sold by the company Sigma-Aldrich, or a poly(ethyleneimine) with CAS number 9002-98-6, having for example a number-average molecular weight Mn between 500 and 700 g/mol with product code 02371 sold by the company Polysciences, Inc.
  • a preferred agent having a suppressive effect on vertical cavities is a branched poly(ethyleneimine) with a mass Mn of about 600 g/mol.
  • Aliphatic polyamines having a molecular weight of less than 500 g/mol may be used in the electroless solution. They can fulfil the function of a suppressor capable of adsorbing to the nickel or cobalt alloy, and in particular selectively adapted to horizontal cavities, or selectively adapted to cavities with an average size at their opening of less than 100 nm. "Selectively adapted” means a suppressor which is not adapted to cavities having an average dimension at their opening greater than 100 nm.
  • An agent, or mixture of agents, having a suppressive effect for horizontal cavities may be selected from the aliphatic polyamines listed above. Mention may be made of ethylenediamine, diethylenetriamine, triethylenetetramine, dipropylenetriamine, 1,3- diaminopropane, 2-(Aminomethyl)-2-methyl-l,3-propanediamine, N,N,N,N-Tetramethyl-1,3- butanediamine.
  • a particular agent with a suppressive effect for horizontal cavities is dipropylene triamine.
  • the substrate may be brought into contact with the electroless solution by dipping in the solution described above, at a temperature of between 40°C and 90°C, preferably 70°C, for a period of 30 s to 20 min, depending on the desired thickness of the layer.
  • this layer may be annealed at a temperature of between 200°C and 400°C, preferably at 250°C, for a period of between 1 min and 30 min, preferably about 10 min, under an inert or reducing atmosphere (4% hydrogen in nitrogen).
  • the step of depositing the alloy metal layer may be performed under different conditions.
  • the substrate to be coated may be rotated.
  • a recirculation of the electroless solution may be imposed in the reactor.
  • the substrate may be brought into contact with the electroless solution by spray wetting the solution at high pressure.
  • Other means may be used in a complementary manner, for example by agitating the substrate and/or the solution with ultrasound or ultrasound guns. In any case, the contacting may be done under vacuum.
  • a method for fabricating a 3D NAND memory according to the invention may include, in addition to the selective metallization process, other steps necessary to provide a memory device that is functional. Alternatively, the method of the invention may comprise steps additional to those described above, to provide a portion of the memory device only.
  • a first example of a 3D NAND memory obtained according to the method of the invention comprises a semiconductor substrate defining a horizontal plane, at least one semiconductor channel disposed along a vertical axis, and several word lines comprising the nickel or cobalt alloy.
  • the method for fabricating such a memory may include, in addition to the metallization process, at least one other step.
  • the method of the invention may comprise, prior to the steps of activation and electroless deposition of the nickel or cobalt alloy, the following steps:
  • a sacrificial material such as SiN or polysilicon
  • the vertical cavity may have an average opening diameter ranging from 80 nm to 150 nm, and a depth greater than 1 micron, and the horizontal cavities may have an average width along a vertical axis less than the average opening diameter of the vertical cavity.
  • the method of the invention provides a particularly advantageous alternative for the fabrication of 3D NAND comprising more than 90 word lines of tungsten or other physically deposited metal.
  • a substrate used for the fabrication of such 3D NAND that is brought into contact with the electroless solution (also referred to as electrolyte) described above may comprise a layer count greater than or equal to a value selected from the group consisting of 32, 48, 64, 96, 128, 192, 256, preferably 96 or 128.
  • the vertical cavities have in particular an average diameter at the opening of less than 1 micron, for example ranging from 50 nm to 150 nm, and a depth of more than 1 micron
  • the horizontal cavities have an average width along a vertical axis of less than 100 nanometers and an average depth along a horizontal axis of less than 100 nanometers.
  • the nickel or cobalt alloy deposit forms at least a portion of the electrical contacts between the different functional conductive elements of the 3D NAND device. These contacts may be located between the bit lines and the semiconductor channels (referred to as “contacts” in the present description). These contacts may also be located between the power supply lines and the word lines (referred to as “peripheral contacts” in the present description).
  • the 3D NAND memory obtained according to the method of the invention comprises a semiconductor substrate defining a horizontal plane, at least one semiconductor channel arranged along a vertical axis, and at least one bit line comprising a nickel or cobalt alloy deposited according to the metallization process of the invention.
  • the fabrication method according to the invention may comprise, in addition to the metallization process, at least one other step.
  • the method of the invention may comprise, prior to the steps of activation and electroless deposition of the nickel or cobalt alloy, a step of depositing a layer of a dielectric material followed by a step of etching cavities in the dielectric material by photolithography. The walls of the cavities of a dielectric nature are then activated by the noble metal and metallized with the nickel or boron alloy as described above.
  • a 3D NAND memory according to the prior art, reproduced in Figure 1 comprises:
  • the polysilicon channel 5 and the copper bit line 406 being electrically connected by a tungsten metal contact 305b, the polysilicon channel 5 and the word line 23 being separated by an ONO charge storage area, and the copper bit line 406 being separated from the metal contact 305b by a copper diffusion barrier material 404 generally comprising tantalum nitride or titanium nitride the metal contact 305b being separated from the polysilicon channel 5 by a layer of barrier material 304a generally comprising tantalum nitride or titanium nitride, and the word line 23 being separated from the silicon dioxide 1 by a layer of barrier material 21 generally comprising tantalum nitride or titanium nitride.
  • a substrate is provided which is etched to form horizontal cavities, which cavities are then metallized with the nickel or cobalt alloy.
  • the substrate in Figure 2A comprises a semiconductor base 4 and a semiconductor channel 5 (only part of which is shown).
  • Two layer stacks that are parallel to the substrate 4 alternate layers of a sacrificial material 1 such as silicon nitride and layers of insulating material 2 such as Si0 2 and are separated by a vertical cavity 30.
  • the sacrificial layer 1 located at the bottom is separated from the semiconductor channel 5 by a dielectric ring 6a, and separated from the base 4 by a dielectric coating 6b.
  • a so-called "ONO" charge storage area separates the semiconductor channel 5 and the layer stack.
  • the ONO area comprises a charge storage material 8 isolated from the semiconductor channel 5 and the stack by an insulating area comprising a blocking dielectric layer 7 and a tunneling dielectric layer 9.
  • the blocking dielectric layer 7 may comprise a single layer of dielectric material or a set of layers of dielectric material.
  • the blocking dielectric layer 7 comprises aluminum oxide, silicon oxide, silicon oxynitride or a combination thereof.
  • the thickness of the dielectric layer 7 may range from 1 nm to 20 nm.
  • the charge storage area 8 may be a continuous layer or a set of discrete portions. In Figure 2A, the charge storage area 8 is shown as a continuous layer comprising a dielectric charge trapping material, such as silicon nitride.
  • the sacrificial material layers 1 may be laterally recessed from the sidewalls of the insulating layers 2, and the charge storage layer 8 may be in the form of a plurality of spaced apart portions.
  • the charge storage layer 8 may be formed of a single material or comprise a stack of several charge storage materials.
  • the thickness of the charge storage layer 8 may be in a range of 2 nm to 20 nm. It may be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD).
  • the charge storage layer 8 may contain a metal such as ruthenium, a metal silicide such as nickel silicide and/or a semiconductor material.
  • the tunneling dielectric layer 9 comprises at least one dielectric material such as silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride.
  • the tunneling dielectric layer 9 may comprise a silicon dioxide/silicon oxynitride/silicon dioxide stack.
  • the thickness of the tunneling dielectric layer 9 may range from 2 nm to 20 nm.
  • the sacrificial material 1 of the substrate of Figure 2A is etched to obtain a structure shown in Figure 2B.
  • Selective etching of volumes of sacrificial material 1 is performed to create cavities 3.
  • the etching process in the case where the sacrificial material layers 1 comprise silicon nitride, may be performed by wet etching by immersing the structure in a tank comprising phosphoric acid.
  • the cavities 3 are horizontal cavities.
  • a horizontal cavity in the sense of the invention is a cavity having a smaller dimension located in the plane of Figure 2B, and a larger dimension in a plane perpendicular thereto.
  • the ratio of the largest dimension to the smallest dimension of the cavity 3 is greater than 1 and may be as high as 10 or even 100.
  • Each cavity 3 is bounded by an upper horizontal surface of an underlying insulating layer 2, a lower horizontal surface of an underlying insulating layer 2, and a lateral vertical surface of a dielectric material, preferably the material of the blocking dielectric layer 7.
  • the cavities 3 are filled by an electroless process with the nickel or cobalt alloy, to create the word lines of the monolithic three-dimensional NAND device.
  • the metallic deposit 20 of nickel or cobalt alloy which fills the horizontal cavities 3 and covers the insulating material 2, may be seen.
  • the metal deposit was obtained in two steps by successively bringing the substrate of Figure 2B into contact with an activation solution containing a noble metal to obtain an activated silicon dioxide surface, and then bringing the activated surface into contact with an electrolyte as described above, in the absence of electrical polarization.
  • the deposited metal 20 fills the entire volume of the horizontal cavities 3, and may also cover all or part of the side walls of the insulating layers 2.
  • the structure, which is obtained after etching the excess metal 20 located outside the cavities 3 and covering the dielectric blocks 2, is shown in Figure 2D.
  • This structure comprises word lines 20a of nickel or cobalt alloy.
  • Figure 3 illustrates the intermediate structure obtained with a process of the prior art for fabricating tungsten word lines 23 in a 3D NAND memory.
  • This structure was obtained from a substrate identical to that shown in Figure 2B comprising cavities 3 and insulating layers 2 defining a free dielectric surface comprising a surface of the blocking dielectric layer 7, the bottom and walls of the cavities 3 and the flush surface of the dielectric layers 2.
  • a tungsten diffusion barrier layer 21 is deposited on the dielectric surface by a CVD or ALD process: it comprises a metal nitride such as TiN or TaN.
  • An example of a barrier layer of the prior art consists of a stack of three successive layers: titanium nitride/tungsten/titanium nitride, each of the three layers can have a thickness ranging from 1 nm to 3 nm.
  • the hollow volumes of the barrier-covered cavities are filled with tungsten by CVD or ALD to form a metal deposit 23.
  • material voids 22 are observed in the metal layers, the frequency of which is inversely proportional to the size at the opening of the cavities 3.
  • a variant of the process of the invention shown in Figures 4A, 4B and 5 consists in metallizing, not silicon dioxide, but aluminum oxide (Al 2 0 3 ).
  • a thin layer of alumina may be interposed between the insulating layers 2 and the nickel or cobalt alloy 20 in the final device. Its thickness may range from 1 nm to 15 nm, for example between 2 and 6 nm.
  • the process then includes a further step of depositing, on the surface defined by the cavities 3 and by the protruding insulating layers 2 of a substrate conforming to that of Figure 2B, a thin alumina layer 10 to obtain a pattern conforming to Figure 4A.
  • the surface of the alumina layer 10 is then brought into contact with an activation solution containing a noble metal to obtain an activated alumina surface, which in turn is brought into contact with an electrolyte as described above, in the absence of electrical polarization, to cause deposition of the nickel or cobalt alloy.
  • the result of this process is a substrate as shown in Figure 4B or Figure 5.
  • the device of the invention is obtained by activating, using an aqueous solution containing a noble metal such as palladium, a surface of the insulating layers 2 and/or the thin alumina layer 10.
  • This activation is followed by immersion of the structure comprising the cavities 3 in a solution containing nickel ions and a reducing agent of the nickel ions, preferably a borane, and more preferably dimethylamino borane, to deposit a nickel -boron alloy as a metal on the bottom and walls of the cavities 3.
  • the alloy may completely fill the cavities and form a deposit 20b ( Figure 4B) or cover the walls and bottom of the cavities without completely filling them to form a deposit 20c ( Figure 5).
  • Figures 4A and 4B illustrate an embodiment of the invention for forming a nickel-boron alloy deposit 20b from a silicon substrate comprising i) a vertical cavity 30 having an opening of about 100 nm and a height of about 4 micrometers, ii) horizontal cavities 3 having a height of 30 nm (dimension c) and a depth of 50 nm (dimension a), and protruding portions of silicon dioxide corresponding to insulating layers 2.
  • the surface of the horizontal cavities 3 and the silicon dioxide was covered with an alumina layer 10 having a thickness of about 5 nm (dimension b).
  • the nickel-boron alloy deposit 20b fills the horizontal cavities 3 and covers the alumina layer 10.
  • the nickel-boron alloy deposit 20c is in the form of a thin layer covering the entire surface of the alumina layer 10 and does not fill the horizontal cavities 3.
  • a layer of a barrier material may be interposed between the blocking dielectric 7 and the nickel or cobalt alloy 20, or between the alumina layer 10 and the nickel or cobalt alloy 20b in the embodiments of the invention illustrated in Figures 2, 4 and 5.
  • this embodiment of the invention is not preferred, as the process of the invention has the advantage that this step may be avoided.
  • barrier materials such as metal nitrides have poorer conductivity than metals, and the addition of a barrier layer reduces the cavity space available for filling with metal.
  • depositing a barrier layer makes it possible to create conductive lines of at least equal or even higher conductivity than the lines of the prior art.
  • depositing a barrier material implies the performance of an additional step in the 3D NAND fabrication process.
  • a layer of a barrier material may therefore be interposed between the surface of the blocking dielectric layer 7 shown in Figure 2B and the nickel or cobalt alloy layers 20a, in an intermediate step between the step of forming the cavities 3 and the step of depositing the nickel or cobalt alloy 20 shown in Figure 2C, in accordance with a process known to the person skilled in the art.
  • a layer of a diffusion barrier material known to the skilled person may be interposed between the surface of the alumina layer 10 shown in Figure 4B and the metal layers 20b.
  • the barrier material may be deposited in one or more steps.
  • the barrier layer may be a single layer of a metal nitride, or a stack of multiple layers of different materials, including at least one layer of metal nitride.
  • the metal nitride may be TiN, TaN or WN.
  • a continuous layer of tantalum nitride or titanium nitride with a thickness of 1 nm to 6 nm is deposited.
  • a second example of a method for fabricating 3D NAND memory according to the invention consists in creating peripheral contacts comprising a nickel or cobalt alloy.
  • This embodiment is illustrated by Figures 6 to 8.
  • This variant of the invention by implementing the metallization process of the invention consists in creating vertical lines connecting the word lines to the power supply lines, these vertical lines comprising a nickel or cobalt alloy.
  • Figures 6 to 8 illustrate the second example of the fabrication method of the invention by which a 3D NAND memory is obtained comprising a semiconductor substrate defining a horizontal plane, a stack of layers deposited on the semiconductor substrate alternating insulating layers 1 and word lines 24, vertical semiconductor channels 5, and peripheral contacts 203 connecting power supply conductor lines and the word lines.
  • the nickel or cobalt alloy deposit forms at least a portion of the peripheral contacts 203, i.e., the contacts located at the periphery 200 of the device with the center of the device occupied by the vertical semiconductor channels 5.
  • the peripheral contacts 203 connect the word lines 24 to conductive power supply lines not shown.
  • a substrate such as that shown in Figure 6 comprising a horizontal stack of insulating layers 1 and word lines 24, and vertical semiconductor channels 5 surrounded by an ONO assembly may be fabricated or procured.
  • the substrate may be of the prior art and include the tungsten-based word lines 24.
  • the substrate may be obtained by a method comprising the metallization process of the invention, the word lines 24 comprising a nickel or cobalt alloy.
  • the stack of insulating layers 1 and word lines 24 is covered on its upper part with an insulating covering layer la (which may be made of silicon dioxide) and, on its lateral part, with a dielectric block lb which covers all the steps of the staircase-like stack.
  • the dielectric block lb may be made of silicon dioxide, optionally doped with an element such as boron, phosphorus or fluorine.
  • the covering layer la and the dielectric block lb are coplanar and covered with a contact dielectric layer lc.
  • Two areas may be defined: a central area 100 comprising the vertical semiconductor channels 5, and a peripheral area 200 comprising the word lines 24 and the dielectric block lb.
  • Two categories of contacts may be created on this substrate: a first series of contacts located on the central area 100 which are in the form of blocks arranged on the upper part of the semiconductor channels 5, and a second series of contacts located on the peripheral area 200 which are in the form of vertical lines intended to connect the word lines 24 to a power source not shown in Figure 6 and located on the upper part of the substrate.
  • a photolithography mask 201 is deposited on the substrate shown in Figure 6 so as to etch contact cavities 202 in the dielectric block lb.
  • the etching is performed with etching solutions having a high selectivity for the metal constituting the word lines 24 so as to stop the etching once the etching solution comes into contact with the word lines 24.
  • This etching step leads to the formation of vertical contact cavities 202 which increase in depth from the top to the bottom of the dielectric block lb, i.e., from the top to the case of the staircase stack.
  • the substrate After removing the polymer that has been deposited by photolithography and cleaning the substrate, the substrate is brought into contact with an activation solution to selectively graft a noble metal to the walls of the contact cavities 202 constituting a dielectric surface of the dielectric block lb that has been etched.
  • the dielectric surface that has been activated by the noble metal is then brought into contact with the electroless solution containing nickel ions or cobalt ions to form a nickel or cobalt alloy deposit according to the process of the invention.
  • Chemical-mechanical polishing removes the excess alloy deposited outside the contact cavities 202, and provides the peripheral contacts 203 made of a nickel or cobalt alloy as shown in Figure 8.
  • vertical contact cavities 202 are etched by photolithography on a previously described substrate similar to that of Figures 6 and 7, except that it includes tungsten word lines 23.
  • the surface of the etched substrate is covered with a T ⁇ N or TaN barrier layer 204, and then the cavities are filled with tungsten.
  • the excess metal deposited outside the vertical contact cavities 202 is then removed by chemical- mechanical polishing to obtain peripheral tungsten contacts 205.
  • the process of the invention advantageously makes it possible to dispense with the step of depositing a barrier layer 204 of TiN or TaN which must be interposed between the tungsten and the dielectric lb.
  • Figures 10 to 12 illustrate a third example of an embodiment of the process of the invention which makes it possible to obtain a 3D NAND memory with contacts between semiconductor channels and bit lines, which comprise a nickel or cobalt alloy.
  • a substrate shown in Figure 10 comprising a horizontal stack of insulating layers 1 and word lines 25 is fabricated or procured.
  • the substrate may be of the prior art and include tungsten word lines 25, and tungsten-based peripheral contacts 206.
  • the word lines and peripheral contacts are tungsten
  • a titanium nitride or tantalum nitride barrier layer is interposed between the tungsten and the dielectric of block lb and dielectric layers la.
  • the substrate may comprise either word lines 25 comprising a nickel or cobalt alloy, or vertical peripheral contacts 206 comprising a nickel or cobalt alloy, or both, the nickel or cobalt alloy having been formed by implementation of a previously described metallization process.
  • the contact dielectric layer lc is covered by another dielectric layer Id.
  • a photolithography mask 301 has been deposited on the substrate shown in Figure 10 so as to etch contact cavities 302a and 302b into the dielectric layer Id.
  • the etching is performed with etching solutions having a high selectivity for the metal of the peripheral contacts 206 and the semiconductor channel 5.
  • the substrate is brought into contact with an activation solution to selectively graft a noble metal onto the walls of the contact cavities 302a and 302b and a surface of the layer Id, which form a dielectric surface.
  • the dielectric surface that has been activated by the noble metal is then brought into contact with the electroless solution containing nickel ions or cobalt ions to form a nickel or cobalt alloy deposit according to the process of the invention.
  • Chemical- mechanical polishing removes the excess alloy deposited outside the contact cavities 302a and 302b, and results, as shown in Figure 12, in peripheral contacts 303a in the form of blocks on top of the peripheral contacts 206, and contacts 303b in the form of blocks on top of the semiconductor channels 5, the contacts 303a and 303b comprising a nickel or cobalt alloy.
  • the contacts 303a so fabricated will connect the peripheral contacts 206 and the power supply lines to be formed later, while the contacts 303b will connect the semiconductor channels 5 to bit lines to be formed in a later step.
  • the surface of the etched substrate is covered with a barrier layer 304a and 304b of tantalum nitride or titanium nitride, and then the cavities having walls covered with the barrier material are filled with tungsten. Excess metal deposited outside the contact cavities is then removed by chemical-mechanical polishing to obtain peripheral tungsten contacts 305a and tungsten contacts 305b.
  • the process of the invention advantageously makes it possible to dispense with the step of depositing a barrier layer 304a, 304b which must be interposed between the tungsten and the dielectric materials of elements lc and Id.
  • Figure 14 represents a structure obtained according to the process of the invention comprising bit lines 403 based on a nickel or cobalt alloy.
  • a dielectric le is deposited which is etched by photolithography to form cavities, the bottom of which reaches the upper surface of the contacts 306, which may be made of tungsten or which may be made of a nickel or cobalt alloy, depending on the starting substrate used.
  • the portion of the etched substrate leaving the dielectric material le flush is activated by the noble metal and then brought into contact with the electroless solution containing nickel ions or cobalt ions to form nickel or cobalt alloy based bit lines 403 according to the process of the invention.
  • a substrate according to Figure 13 is covered with a layer of dielectric material le which is etched by photolithography to form cavities that reach the upper surface of tungsten contacts 305b.
  • the walls of the cavities that are flush with the dielectric material le are covered with a thin layer of barrier material 404 and then with a thin layer of copper 405.
  • the volume of the remaining cavities is then filled with copper 406.
  • the process of the invention makes it possible to dispense with the steps of depositing a barrier layer 404 and a copper seed layer 405.
  • An electrolyte according to the invention is an electrolyte for fabricating a 3D NAND memory device comprising:
  • metal ions being nickel ions or cobalt ions, and being preferably in a concentration of between 10 3 M and 1 M;
  • At least one polyamine agent preferably in an amount of between 1 to 100 mg/I.
  • the electrolyte comprises two reducing agents.
  • the two reducing agents can be hypophosphorous acid and dimethylamino-borane.
  • EP 2 705 172 A1 It has already been proposed in EP 2 705 172 A1 to deposit a nickel-boron alloy in vertical wells whose diameter at the opening is of the order of 1 to 5 microns and whose depth can reach about 30 microns.
  • this prior art electrolyte does not allow for the simultaneous filling of structures of different geometries such as those used to fabricate 3D NAND.
  • an electrolyte according to EP 2 705 172 A1 does not make it possible to obtain a conformal deposit at the bottom of structures whose opening may be as small as 100 nm and whose depth may be as large as 4 microns.
  • the DMAB reducing agent of the prior art is not fast enough to initiate reduction at the bottom and sides of the well and stages. Surprisingly, the inventors have found that adding a second reducing agent can accelerate the growth of the alloy in structures that are difficult to access and achieve conformal deposition without affecting the quality of the alloy.
  • the electrolyte can comprise two polyamine agents, a first polyamine agent and a second polyamine agent that are preferably aliphatic polyamines.
  • a first polyamine agent concentration can be between 0.5 ppm and 100 ppm and a second polyamine agent concentration can be between 0.5 ppm and 100 ppm.
  • the first polyamine agent preferably has a molecular weight that is lower than that of the second polyamine.
  • the molecular weight of the second polyamine agent can range from 500 g/mol to 25 000 g/mol, and the molecular weight of the first polyamine agent can be in a range that is between 50 g/mol and 500 g/mol, 50 g/mol and 500 g/mol being excluded values.
  • a particular electrolyte comprises:
  • the first reducing agent and the second reducing agent may be selected from the reducing agents described above.
  • the present application also discloses an electrolyte for fabricating a 3D NAND memory device, said electrolyte comprising:
  • At least one metal salt preferably in a concentration of between 10 ⁇ 3 M and 1 M;
  • At least one reducing agent for the metal salt preferably in an amount of between 10 4 M and 1 M;
  • the present application discloses an electrolyte for coating a surface of a dielectric material, said electrolyte comprising:
  • At least one metal salt preferably in a concentration of between 10 ⁇ 3 M and 1 M;
  • the mixture preferably representing an amount of between 10 ⁇ 4 M and 1 M;
  • At least two agents capable of adsorbing on a metal oxide in particular a first agent having a suppressor effect and preferably being in a concentration of between 0.5 ppm and 100 ppm, and a second agent having a suppressor effect, preferably being in a concentration of between 0.5 ppm and 100 ppm.
  • the present application further discloses an electrolyte for fabricating a 3D NAND memory device comprising:
  • At least one metal salt preferably in a concentration of between 10 3 M and 1 M;
  • At least two agents capable of adsorbing on a metal oxide in particular a first agent optionally having a suppressor effect and preferably being in a concentration of between 0.5 ppm and 100 ppm, and a second agent optionally having a suppressor effect, preferably being in a concentration of between 0.5 ppm and 100 ppm.
  • the first agent may be dipropylene triamine and the second agent may be polyethyleneimine.
  • the electrolyte may comprise two reducing agents, the two reducing agents being hypophosphorous acid and dimethylamino borane.
  • a particular electrolyte of the invention comprises between 10 ⁇ 2 M and 1 M nickel ions, between 1CT 4 M and 1 M DMAB, between 10 and 100 mg/I H 2 P0 3 , between 1 and 5 mg/I of a PEI, from 1 to 100 mg/I, preferably from 1 to 10 mg/I, of dipropylene triamine.
  • the first reducing agent is preferably dimethylamino borane, and the second reducing agent is preferably hypophosphorous acid.
  • the first polyamine and the second polyamine may be selected from the polyamines described above.
  • the first polyamine is a polyethyleneimine with a molecular weight ranging from 500 g/mol to 25 000 g/mol
  • the second aliphatic polyamine may be dipropylene triamine.
  • the electrolyte comprises:
  • At least one reducing agent of nickel ions in an amount of between 400 mM and 550 mM;
  • a stabilizing agent preferably citric acid in an amount sufficient to complex the nickel ions
  • poly(ethyleneimine) having a number-average molecular weight Mn of about 600 g/mol, in an amount of from 1 mg/I to 5 mg/I,
  • an aliphatic polyamine having a molecular weight of less than 500 g/mol in an amount of from 1 mg/I to 100 mg/I
  • an agent for adjusting the pH to a value of from 9.0 to 9.5 an agent for adjusting the pH to a value of from 9.0 to 9.5.
  • two reducing agents may be used, including dimethylaminoborane in a concentration of 450 mM to 500 mM, and hypophosphorous acid in an amount of 10 mg/I to 100 mg/I.
  • the electrolyte is prepared upstream of the metallization step, and if it is necessary to store certain ingredients that make up the electrolyte, it is preferable to prepare and store at least two distinct solutions that are mixed just before the electroless solution is brought into contact with the substrate.
  • a first solution containing the metal ion and a second solution containing the reducing agent may be prepared and optionally stored, the two solutions together comprising all of the compounds in the electrolyte composition.
  • the second solution containing the reducing agent also contains the polyamine or polyamines when there are several of them.
  • the metal ions and the reducing agent are preferably packaged separately for presence within the electroless solution, just prior to contacting the substrate.
  • the electrolyte of the invention is preferably prepared extemporaneously by mixing the two solutions mentioned above.
  • a third object of the invention is a 3D NAND device in which the metal used in the fabrication of the word lines essentially comprises an alloy of nickel with at least one element selected from boron, phosphorus and tungsten, the element being able to represent between 1 and 10 atomic %.
  • all the semiconductor channels are vertical (vertical channel) and the gates of the memory cells are horizontal (horizontal gate): each channel is thus surrounded by a vertical stack of several memory cells, and the control gates (also called word lines) are in the form of horizontal lines.
  • the memory cells surround the channel and are in a so-called gate-all-around (GAA) configuration.
  • GAA gate-all-around
  • control gates are deposited last (gate last or gate replacement) which requires the use of sacrificial nickel silicide, the latter being replaced by the control gate (thin metal layer) then a metal filling.
  • metal gates are deposited first (gate first).
  • the 3D NAND device is a 3D V-NAND memory.
  • the NAND device of the invention in particular in the case of 3D V-NAND, may comprise, in the gate dielectric, a material of high dielectric constant such as alumina instead of silicon dioxide, to optimize the charge transfers.
  • the device may be fabricated according to various processes known to the skilled person in which at least one tungsten deposition step is replaced by a nickel deposition step in accordance with the process of the invention described above.
  • Example 1 Creation of word lines with a nickel-boron alloy
  • the substrate used is a silicon coupon of 4 cm x 4 cm side and 750 pm thickness, having vertical cavities with an opening of about 100 nm and height of about 4 micrometers, and horizontal cavities of 30 nm height and 50 nm depth, all covered with a layer of alumina (Al 2 0 3 ) having a thickness of about 5 nm.
  • a) Cleaning of the surface of the cavities The coupon is cleaned according to the chemical nature of the substrate. After this cleaning step, the coupon is rinsed thoroughly with deionized water, immersed in a beaker filled with deionized water and subjected to ultrasound (40 kHz) for 2 minutes. The coupon is then removed from the beaker, rinsed thoroughly with deionized water and dried in an oven at 100°C for 10 minutes.
  • the coupon prepared in step al) is immersed in the beaker comprising the activation solution prepared in bl) and the whole is subjected to a rapid vacuum sufficient to evacuate the air enclosed in the cavities of the structure.
  • the beaker is introduced into a desiccator, itself connected to a vane pump, and the whole is subjected to a vacuum for about 2 minutes.
  • the liquid mixture containing the coupon is heated to 65°C for 20 minutes.
  • the coupon is removed from the solution, rinsed thoroughly with deionized water, and immersed in a beaker filled with deionized water and subjected to ultrasound (40 kHz) for 30 seconds.
  • the coupon is then removed from the beaker and rinsed thoroughly with deionized water.
  • a nickel-boron alloy layer was deposited on the surface of the substrate treated in step b) by first immersing it in a beaker of deionized water.
  • the beaker is rapidly evacuated to a vacuum sufficient to remove the air trapped in the cavities of the structure.
  • the beaker is introduced into a desiccator, itself connected to a vane pump, and the whole is subjected to a vacuum for about 2 minutes.
  • the coupon is quickly dipped in the electroless solution prepared beforehand and heated to 65°C, for a period of 30 seconds to 9 minutes, depending on the desired final thickness and the size of the treated structures. A shiny grey metallic coating can then be observed on the coupon.
  • the coupon is removed from the solution, rinsed thoroughly with deionized water, immersed in a beaker filled with deionized water and subjected to ultrasound (40 kHz) for 30 seconds.
  • the coupon is then removed from the beaker, rinsed thoroughly with deionized water and dried under a stream of nitrogen.
  • the coupon is subjected to Rapid Thermal Annealing (RTA) at 250°C for ten minutes in a reducing atmosphere (4% hydrogen in nitrogen).
  • RTA Rapid Thermal Annealing
  • the operation may be performed with a tube furnace or a hot plate.
  • the coupon obtained at the end of step c2) is subjected to a new thermal annealing at 800°C for one minute in a reducing atmosphere (4% hydrogen in nitrogen) to simulate the transformations that it could undergo during all the fabrication steps of an industrial 3D NAND memory.
  • the EELS profile shows that the nickel -boron alloy does not diffuse into the Si0 2 .
  • the metal deposited according to the process of the invention makes it possible to eliminate the step of depositing a barrier layer of a few nanometers that it is necessary to interpose between the dielectric and the metal filling the cavities to fabricate the 3D NAND memories of the prior art. f) Evaluation of wafer bowing induced bv metal film
  • the bowing generated by a 50 nm NiB deposit annealed at 400°C for 2 hours does not disturb the flatness of the wafer.
  • the stress exerted by the NiB layer is evaluated at 825 MPa, while it is greater than 2 GPa for a tungsten-CVD W layer of equivalent thickness. This is illustrated in Figure 16.
  • Example 2 Deposition of a thin layer of nickel-boron alloy on the walls of cavities intended to form word lines
  • Example 1 was replicated except that in step cl) the 55 ppm of hypophosphorous acid was not added.
  • the horizontal cavities are covered with a thin layer of NiB alloy, and a schematic of the resulting substrate may be as shown in Figure 6.
  • Example 3 Creation of contacts between bit lines and oolvsilicon channels with a nickel-boron alloy
  • the objective of this example is to activate a substrate coated with a mixed structure of silica (Si0 2 ) and polysilicon (pSi) from a solution containing a silane and a palladium complex to fill a "contact" structure located between "bit lines” and "channels" of a NAND substrate with a NiB-type alloy.
  • the substrate used in this example consisted of a silicon coupon with a 4x4 cm side and a 750 pm thickness, covered with a structured silicon oxide layer with vias (wells) with an opening of about 100 nm and a height of about 300 nm.
  • the bottom of the cavities is recessed and in direct contact with polysilicon (pSi). These structures mimic the contacts in a NAND device.
  • pSi polysilicon
  • the coupon is soaked in a solution SCI at 70°C and ultrasonicated (40 kHz) for 10 minutes. After this cleaning step, the coupon is rinsed thoroughly with deionized water, immersed in a beaker filled with deionized water and subjected to ultrasound (40 kHz) for 2 minutes. The coupon is then removed from the beaker, rinsed thoroughly with deionized water and dried in an oven at 100°C for 10 minutes.
  • the coupon prepared in step a) is immersed in the beaker comprising the activation solution prepared in bl) and the whole is subjected to a rapid vacuum sufficient to evacuate the air enclosed in the cavities of the structure.
  • the beaker is introduced into a desiccator, itself connected to a vane pump, and the whole is subjected to a vacuum for about 2 minutes.
  • the liquid mixture containing the coupon is heated to 65°C for 10 minutes.
  • the coupon is removed from the solution, rinsed thoroughly with deionized water, and immersed in a beaker filled with deionized water and subjected to ultrasound (40 kHz) for 30 seconds.
  • the coupon is then removed from the beaker, rinsed thoroughly with deionized water and dried under a stream of nitrogen.
  • a nickel-boron alloy layer was deposited on the surface of the substrate treated in step b) by first immersing it in a beaker of deionized water.
  • the beaker is rapidly evacuated to a vacuum sufficient to remove the air trapped in the cavities of the structure.
  • the beaker is introduced into a desiccator, itself connected to a vane pump, and the whole is subjected to a vacuum for about 2 minutes.
  • the coupon is quickly dipped in the electroless solution prepared earlier (cl) and heated to 65°C, for a period of 2 to 9 minutes, depending on the final thickness desired and the size of the structures treated.
  • the solution is subjected to 3 second pulses of 40 kHz ultrasound in sweep mode every 15 seconds for 2 minutes.
  • the coupon is removed from the solution, rinsed thoroughly with deionized water, and immersed in a beaker filled with deionized water and subjected to ultrasound (40 kHz) for 30 seconds.
  • the coupon is then removed from the beaker, rinsed thoroughly with deionized water and dried under a stream of nitrogen.
  • the coupon is subjected to Rapid Thermal Annealing (RTA) at 400°C for ten minutes in a reducing atmosphere (4% hydrogen in nitrogen).
  • RTA Rapid Thermal Annealing
  • the operation may be performed with a tube furnace or a hot plate.
  • step c2 After thermal annealing of the coupon obtained at the end of step c2), it is observed that all the vias are homogeneously filled with a nickel-boron alloy.
  • the adhesion measured according to standard ASTM 3359 is 16/16. This electroless solution therefore works both for creating word lines, as in Examples 1 and 2, and for creating contacts underneath the bit lines.
  • Example 4 Creating bit lines with a nickel-boron alloy
  • the objective of this example is to activate a substrate coated with a mixed structure of silica (Si0 2 ) and NiB alloy from a solution containing a silane and a palladium complex to fill a bit line structure above the NiB contacts of a NAND substrate with a NiB alloy, the contacts having been fabricated, for example, according to Example 3.
  • the substrate used in this example consisted of a 4x4 cm square and 750 pm thick silicon coupon, covered with a structured silicon oxide layer having vias (wells) with an opening of about 300 nm and a height of about 500 nm.
  • the bottom of the cavities is recessed and in direct contact with the NiB alloy or tungsten of the "contact" part of the NAND structure.
  • the coupon prepared in step a) is immersed in the beaker comprising the activation solution prepared in bl) and the whole is subjected to a rapid vacuum sufficient to evacuate the air enclosed in the cavities of the structure.
  • the beaker is introduced into a desiccator, itself connected to a vane pump, and the whole is subjected to a vacuum for about 2 minutes.
  • the liquid mixture containing the coupon is heated to 65°C for 10 minutes.
  • the coupon is removed from the solution, rinsed thoroughly with deionized water, and immersed in a beaker filled with deionized water and subjected to ultrasound (40 kHz) for 30 seconds.
  • the coupon is then removed from the beaker, rinsed thoroughly with deionized water and dried under a stream of nitrogen.
  • a nickel-boron alloy layer was deposited on the surface of the substrate treated in step b) by first immersing it in a beaker of deionized water.
  • the beaker is rapidly evacuated to a vacuum sufficient to remove the air trapped in the cavities of the structure.
  • the beaker is introduced into a desiccator, itself connected to a vane pump, and the whole is subjected to a vacuum for about 2 minutes.
  • the coupon is quickly dipped in the electroless solution prepared earlier (cl) and heated to 65°C, for a period of 2 to 9 minutes, depending on the final thickness desired and the size of the structures treated.
  • the solution is subjected to 3 second pulses of 40 kHz ultrasound in sweep mode every 15 seconds for 2 minutes.
  • the coupon is removed from the solution, rinsed thoroughly with deionized water, and immersed in a beaker filled with deionized water and subjected to ultrasound (40 kHz) for 30 seconds.
  • the coupon is then removed from the beaker, rinsed thoroughly with deionized water and dried under a stream of nitrogen.
  • the coupon is subjected to Rapid Thermal Annealing (RTA) at 400°C for ten minutes in a reducing atmosphere (4% hydrogen in nitrogen).
  • RTA Rapid Thermal Annealing
  • the operation may be performed with a tube furnace or a hot plate.
  • step c2 After thermal annealing of the coupon obtained at the end of step c2), it is observed that all the vias are homogeneously filled with a nickel-boron alloy of one thickness.
  • the adhesion measured according to standard ASTM 3359 is 16/16.
  • Example 5 Creation of bit lines with a nickel-boron alloy and copper
  • the substrate is identical to Example 4.
  • the substrate is treated in the same way as in Example 4 part a)
  • Activation of the cavity surface bl) Preparation of the activation solution: The solution is identical to that prepared in b) in Example 4. b2) Activation treatment of the substrate surface:
  • the surface treatment is identical to that performed in b2) in Example 4.
  • the surface treatment is identical to that carried out in c2) in Example 4. However, the process is carried out incompletely, by decreasing the process time or adjusting the concentrations of the additives according to the knowledge of the skilled person, so that the bit lines of the NiB alloy are not completely filled. The remaining cavities are filled with copper in the following steps.
  • the concentration of Cu 2+ is equal to 15 g/L obtained from CuS0 4 (H 2 0) 5 .
  • Ethylene diamine is present in stoichiometric proportion with copper by a factor of 2.
  • d2) Equipment
  • an electrodeposition equipment consisting of two parts: the cell intended to contain the electrodeposition solution equipped with a fluid recirculation system to control the hydrodynamics of the system, and a rotating electrode equipped with a sample holder adapted to the size of the coupons used (4 cm x 4 cm).
  • the electrodeposition cell had two electrodes:
  • the reference is connected to the anode.
  • the substrates obtained in c) do not undergo any particular treatment if they are fresh.
  • the coupon prepared in step c) is optionally immersed first in a beaker of deionized water.
  • the beaker is rapidly evacuated to a vacuum sufficient to remove the air trapped in the cavities of the structure.
  • the beaker is introduced into a desiccator, itself connected to a vane pump, and the whole is subjected to a vacuum for about 2 minutes.
  • the coupon is quickly mounted in the deposition cell which is soaked in the solution prepared in dl) This assembly then undergoes an electrical process with a cold inlet.
  • the cathode was biased in a galvano-pulsed mode in a current range of 5 mA (or 2 mA/cm 2 ) to 50 mA (or 20 mA/cm 2 ), for example 20 mA (or 8 mA/cm 2 ) with a pulse duration between 5 and 1000 ms in cathodic bias, and between 5 and 1000 ms in zero bias between two cathodic pulses.
  • This step was carried out under a rotation of 60 rpm for 10 minutes.
  • the contact between the electrolyte and the substrate is made before the power-up with a delay of 30 seconds.
  • the coupon was removed from the solution, rinsed thoroughly with deionized water, and immersed in a beaker filled with deionized water and subjected to ultrasound (40 kHz) for 30 seconds.
  • the coupon is then removed from the beaker, rinsed thoroughly with deionized water and dried under a stream of nitrogen.
  • the coupon is subjected to Rapid Thermal Annealing (RTA) at 250°C for ten minutes in a reducing atmosphere (4% hydrogen in nitrogen).
  • RTA Rapid Thermal Annealing
  • the operation may be performed with a tube furnace or a hot plate.

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Abstract

L'invention concerne un procédé de métallisation d'un substrat semi-conducteur destiné en particulier à la fabrication d'une mémoire NON-ET 3D. Ce procédé de métallisation comprend une étape d'activation de la surface d'un matériau diélectrique avec un métal noble tel que le palladium, suivie d'une étape de dépôt d'un alliage de nickel ou de cobalt par un procédé anélectrolytique à l'aide d'une solution comprenant des ions métalliques.
EP21721551.6A 2020-04-29 2021-04-28 Procédé de fabrication de non-et 3d avec un alliage de nickel ou de cobalt Pending EP4143882A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR2004260A FR3109840B1 (fr) 2020-04-29 2020-04-29 Procédé de métallisation d’un substrat semi-conducteur, électrolyte et méthode de fabrication de 3D-NAND
FR2100492A FR3109839A1 (fr) 2020-04-29 2021-01-19 Méthode de fabrication de 3D-NAND mettant en œuvre un alliage de nickel ou de cobalt
PCT/EP2021/061174 WO2021219744A1 (fr) 2020-04-29 2021-04-28 Procédé de fabrication de non-et 3d avec un alliage de nickel ou de cobalt

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EP4143882A1 true EP4143882A1 (fr) 2023-03-08

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KR (1) KR20210150415A (fr)
CN (1) CN116134980A (fr)
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WO (1) WO2021219744A1 (fr)

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TW202403100A (zh) 2022-03-30 2024-01-16 法商亞凡尼公司 用於製造半導體裝置之以鎳或鈷合金進行金屬化的方法

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JP4401912B2 (ja) * 2003-10-17 2010-01-20 学校法人早稲田大学 半導体多層配線板の形成方法
TW200707640A (en) * 2005-03-18 2007-02-16 Applied Materials Inc Contact metallization scheme using a barrier layer over a silicide layer
FR2933425B1 (fr) 2008-07-01 2010-09-10 Alchimer Procede de preparation d'un film isolant electrique et application pour la metallisation de vias traversants
KR101495799B1 (ko) * 2009-02-16 2015-03-03 삼성전자주식회사 비휘발성 메모리 장치 및 그 제조 방법
FR2950062B1 (fr) 2009-09-11 2012-08-03 Alchimer Solution et procede d'activation de la surface d'un substrat semi-conducteur
FR2950633B1 (fr) 2009-09-30 2011-11-25 Alchimer Solution et procede d'activation de la surface oxydee d'un substrat semi-conducteur.
FR2974818B1 (fr) 2011-05-05 2013-05-24 Alchimer Procede de depot de couches metalliques a base de nickel ou de cobalt sur un substrat solide semi-conducteur ; kit pour la mise en oeuvre de ce procede
RU2013158459A (ru) * 2011-06-01 2015-07-20 Басф Се Композиция для электроосаждения металла, содержащая добавку для заполнения снизу вверх переходных отверстий в кремнии и межсоединительных элементов
US11171050B2 (en) * 2017-03-09 2021-11-09 Tokyo Electron Limited Method for manufacturing a contact pad, method for manufacturing a semiconductor device using same, and semiconductor device
CN110289265B (zh) * 2019-06-28 2020-04-10 长江存储科技有限责任公司 3d nand存储器的形成方法

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FR3109840B1 (fr) 2022-05-13
KR20210150415A (ko) 2021-12-10
TW202208680A (zh) 2022-03-01
WO2021219744A1 (fr) 2021-11-04
CN116134980A (zh) 2023-05-16
FR3109840A1 (fr) 2021-11-05

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