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DE69410526D1 - Synchrone Halbleiterspeicheranordnung mit einer Eingangsschaltung zur Herstellung eines konstanten Hauptsteuersignals, um einem Zeitgeber zu erlauben, Steuersignale zu verriegeln - Google Patents

Synchrone Halbleiterspeicheranordnung mit einer Eingangsschaltung zur Herstellung eines konstanten Hauptsteuersignals, um einem Zeitgeber zu erlauben, Steuersignale zu verriegeln

Info

Publication number
DE69410526D1
DE69410526D1 DE69410526T DE69410526T DE69410526D1 DE 69410526 D1 DE69410526 D1 DE 69410526D1 DE 69410526 T DE69410526 T DE 69410526T DE 69410526 T DE69410526 T DE 69410526T DE 69410526 D1 DE69410526 D1 DE 69410526D1
Authority
DE
Germany
Prior art keywords
timer
producing
allow
memory device
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69410526T
Other languages
English (en)
Other versions
DE69410526T2 (de
Inventor
Takashi Obara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69410526D1 publication Critical patent/DE69410526D1/de
Application granted granted Critical
Publication of DE69410526T2 publication Critical patent/DE69410526T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
DE69410526T 1993-04-02 1994-03-30 Synchrone Halbleiterspeicheranordnung mit einer Eingangsschaltung zur Herstellung eines konstanten Hauptsteuersignals, um einem Zeitgeber zu erlauben, Steuersignale zu verriegeln Expired - Lifetime DE69410526T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5077237A JP2605576B2 (ja) 1993-04-02 1993-04-02 同期型半導体メモリ

Publications (2)

Publication Number Publication Date
DE69410526D1 true DE69410526D1 (de) 1998-07-02
DE69410526T2 DE69410526T2 (de) 1999-01-28

Family

ID=13628264

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69410526T Expired - Lifetime DE69410526T2 (de) 1993-04-02 1994-03-30 Synchrone Halbleiterspeicheranordnung mit einer Eingangsschaltung zur Herstellung eines konstanten Hauptsteuersignals, um einem Zeitgeber zu erlauben, Steuersignale zu verriegeln

Country Status (5)

Country Link
US (1) US5444667A (de)
EP (1) EP0623931B1 (de)
JP (1) JP2605576B2 (de)
KR (1) KR0132645B1 (de)
DE (1) DE69410526T2 (de)

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JP3157681B2 (ja) * 1994-06-27 2001-04-16 日本電気株式会社 論理データ入力ラッチ回路
JP3592386B2 (ja) * 1994-11-22 2004-11-24 株式会社ルネサステクノロジ 同期型半導体記憶装置
JPH08195077A (ja) * 1995-01-17 1996-07-30 Internatl Business Mach Corp <Ibm> Ｄｒａｍの転送方式
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US5550783A (en) * 1995-04-19 1996-08-27 Alliance Semiconductor Corporation Phase shift correction circuit for monolithic random access memory
US5600605A (en) * 1995-06-07 1997-02-04 Micron Technology, Inc. Auto-activate on synchronous dynamic random access memory
US5615169A (en) * 1995-08-31 1997-03-25 Monolithic System Technology, Inc. Method and structure for controlling internal operations of a DRAM array
US6810449B1 (en) 1995-10-19 2004-10-26 Rambus, Inc. Protocol for communication with dynamic memory
US5748914A (en) * 1995-10-19 1998-05-05 Rambus, Inc. Protocol for communication with dynamic memory
US6470405B2 (en) 1995-10-19 2002-10-22 Rambus Inc. Protocol for communication with dynamic memory
US6035369A (en) 1995-10-19 2000-03-07 Rambus Inc. Method and apparatus for providing a memory with write enable information
JPH09148907A (ja) * 1995-11-22 1997-06-06 Nec Corp 同期式半導体論理装置
US5715476A (en) * 1995-12-29 1998-02-03 Intel Corporation Method and apparatus for controlling linear and toggle mode burst access sequences using toggle mode increment logic
JP3986578B2 (ja) * 1996-01-17 2007-10-03 三菱電機株式会社 同期型半導体記憶装置
US5749086A (en) * 1996-02-29 1998-05-05 Micron Technology, Inc. Simplified clocked DRAM with a fast command input
US5838631A (en) * 1996-04-19 1998-11-17 Integrated Device Technology, Inc. Fully synchronous pipelined ram
KR100218734B1 (ko) * 1996-05-06 1999-09-01 김영환 싱크로노스 메모리의 내부펄스 신호발생 방법 및 그장치
US6209071B1 (en) 1996-05-07 2001-03-27 Rambus Inc. Asynchronous request/synchronous data dynamic random access memory
JPH1021684A (ja) * 1996-07-05 1998-01-23 Mitsubishi Electric Corp 同期型半導体記憶装置
KR100212142B1 (ko) * 1996-09-12 1999-08-02 윤종용 매크로 명령기능을 가진 동기식 반도체 메모리장치와 매크로 명령의 저장 및 실행방법
US5940608A (en) 1997-02-11 1999-08-17 Micron Technology, Inc. Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal
US6912680B1 (en) 1997-02-11 2005-06-28 Micron Technology, Inc. Memory system with dynamic timing correction
US5920518A (en) * 1997-02-11 1999-07-06 Micron Technology, Inc. Synchronous clock generator including delay-locked loop
WO1998036417A1 (en) * 1997-02-13 1998-08-20 United Memories Inc. Clock doubler and minimum duty cycle generator for sdrams
US5946244A (en) 1997-03-05 1999-08-31 Micron Technology, Inc. Delay-locked loop with binary-coupled capacitor
US6173432B1 (en) 1997-06-20 2001-01-09 Micron Technology, Inc. Method and apparatus for generating a sequence of clock signals
US6266379B1 (en) 1997-06-20 2001-07-24 Massachusetts Institute Of Technology Digital transmitter with equalization
US6101197A (en) 1997-09-18 2000-08-08 Micron Technology, Inc. Method and apparatus for adjusting the timing of signals over fine and coarse ranges
US6401167B1 (en) 1997-10-10 2002-06-04 Rambus Incorporated High performance cost optimized memory
US6263448B1 (en) 1997-10-10 2001-07-17 Rambus Inc. Power control system for synchronous memory device
WO1999019805A1 (en) 1997-10-10 1999-04-22 Rambus Incorporated Method and apparatus for two step memory write operations
TW400635B (en) * 1998-02-03 2000-08-01 Fujitsu Ltd Semiconductor device reconciling different timing signals
US6269451B1 (en) 1998-02-27 2001-07-31 Micron Technology, Inc. Method and apparatus for adjusting data timing by delaying clock signal
JP3125749B2 (ja) * 1998-06-11 2001-01-22 日本電気株式会社 同期型半導体メモリ
US6338127B1 (en) 1998-08-28 2002-01-08 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same
US6349399B1 (en) 1998-09-03 2002-02-19 Micron Technology, Inc. Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
US6279090B1 (en) 1998-09-03 2001-08-21 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device
JP3725715B2 (ja) 1998-11-27 2005-12-14 株式会社東芝 クロック同期システム
US6430696B1 (en) 1998-11-30 2002-08-06 Micron Technology, Inc. Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same
US6185711B1 (en) * 1998-12-03 2001-02-06 Sun Microsystems, Inc. Methods and apparatus for synchronizing asynchronous test structures and eliminating clock skew considerations
US6374360B1 (en) 1998-12-11 2002-04-16 Micron Technology, Inc. Method and apparatus for bit-to-bit timing correction of a high speed memory bus
KR100287184B1 (ko) * 1999-02-23 2001-04-16 윤종용 동기식 디램 반도체 장치의 내부 클럭 지연 회로 및 그 지연 방법
US6470060B1 (en) 1999-03-01 2002-10-22 Micron Technology, Inc. Method and apparatus for generating a phase dependent control signal
JP4201490B2 (ja) * 2000-04-28 2008-12-24 富士通マイクロエレクトロニクス株式会社 自動プリチャージ機能を有するメモリ回路及び自動内部コマンド機能を有する集積回路装置
KR100499626B1 (ko) * 2000-12-18 2005-07-07 주식회사 하이닉스반도체 반도체 메모리 장치
US8391039B2 (en) 2001-04-24 2013-03-05 Rambus Inc. Memory module with termination component
US6675272B2 (en) 2001-04-24 2004-01-06 Rambus Inc. Method and apparatus for coordinating memory operations among diversely-located memory components
US6801989B2 (en) 2001-06-28 2004-10-05 Micron Technology, Inc. Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same
CN100456387C (zh) * 2002-04-15 2009-01-28 富士通微电子株式会社 半导体存储器
US7168027B2 (en) 2003-06-12 2007-01-23 Micron Technology, Inc. Dynamic synchronization of data capture on an optical or other high speed communications link
US7301831B2 (en) 2004-09-15 2007-11-27 Rambus Inc. Memory systems with variable delays for write data signals
US7379382B2 (en) * 2005-10-28 2008-05-27 Micron Technology, Inc. System and method for controlling timing of output signals
KR100666182B1 (ko) * 2006-01-02 2007-01-09 삼성전자주식회사 이웃하는 워드라인들이 비연속적으로 어드레싱되는 반도체메모리 장치 및 워드라인 어드레싱 방법

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JPS61110396A (ja) * 1984-11-05 1986-05-28 Fujitsu Ltd 半導体記憶装置
US5018111A (en) * 1988-12-27 1991-05-21 Intel Corporation Timing circuit for memory employing reset function
TW198135B (de) * 1990-11-20 1993-01-11 Oki Electric Ind Co Ltd
JPH1119986A (ja) * 1997-07-07 1999-01-26 Sekisui Chem Co Ltd 射出成形品の製造方法

Also Published As

Publication number Publication date
EP0623931A3 (de) 1994-12-14
EP0623931B1 (de) 1998-05-27
JPH06290583A (ja) 1994-10-18
EP0623931A2 (de) 1994-11-09
DE69410526T2 (de) 1999-01-28
US5444667A (en) 1995-08-22
KR0132645B1 (ko) 1998-04-16
JP2605576B2 (ja) 1997-04-30

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Legal Events

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8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

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Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

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