CN1694227A - 包括半导体存储器元件的半导体器件及其制造方法 - Google Patents
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Abstract
一种晶片,在该晶片中通过以格状图案排列的渠道在晶片的面上限定了多个矩形区域,且在各个矩形区域中设置半导体存储器元件,沿着渠道切割该晶片,以将矩形区域分割成单个的区域,由此形成多个半导体器件。在沿着渠道分割晶片之前,在晶片的背面形成具有0.20μm或更小的、尤其是0.05至0.20μm厚度的应变层。通过研磨部件研磨半导体器件的背面来形成该应变层,通过用粘接材料粘接具有4μm或更小粒径的金刚石磨粒形成所述研磨部件。
Description
技术领域
本发明涉及一种包括半导体存储器元件如DRAM(动态随机存取存储器)或快闪存储器的半导体器件以及制造该半导体器件的方法。
现有技术
在半导体器件的制造中,如本领域技术人员中众所周知的,通过以半导体晶片表面上的格状图案排列的渠道(street)来限定多个矩形区域,并在所述多个矩形区域的每一个中设置了半导体元件。然后,研磨晶片的背面以降低晶片的厚度。接着,沿着所述渠道切割晶片,从而将所述多个矩形区域分成单个的区域,由此形成半导体器件。在研磨之前称为划片的方式中,沿着渠道没有将晶片完全切割开,但在晶片中沿着渠道形成了所需深度的沟槽,并接着研磨晶片的背面以使晶片的厚度与沟槽的深度一致,从而将矩形区域单独地分隔开以制造半导体器件。
近来,半导体器件已变得紧凑且轻便。因此,往往需要使半导体器件的厚度为100μm或更小,并且更进一步为50μm或更小。当研磨半导体晶片的背面时,由于研磨而在半导体器件的背面产生了应变层。这种应变层降低了半导体器件的横向破裂抵抗力(transverserupture resistance)。如果半导体器件达到这样小的厚度,则如果留下未改变的上述应变层,则将使半导体器件的横向破裂抵抗力不够大。因此,如果要使半导体器件的厚度那样薄,则通常对研磨了的半导体晶片的背面进行抛光或刻蚀,由此在将半导体晶片分成单个的矩形区域之前去除应变层。通过以上操作,避免了半导体器件过低的横向破裂抵抗力。
发明人的研究已经显示出,在包括存储元件如DRAM或快闪存储器的半导体器件的情况下,如果在研磨了半导体晶片的背面之后,通过抛光或刻蚀去除该应变层,则会使存储器元件的功能变差。该原因还不完全清楚,但发明人认为,一旦去除了该应变层,则消除了由该应变层引起的吸沉效应(gettering sink effect),结果诸如重金属等的杂质将返回到半导体晶片表面附近。
发明内容
因此,本发明的第一个目的在于改进包括存储器元件的半导体器件,由此,即使半导体器件的厚度足够小,也会有足够的横向破裂抵抗力,而没有使存储器功能恶化。
本发明的第二个目的在于提供一种包括存储器元件的半导体器件的制造方法,即使半导体器件的厚度足够小,该半导体器件也具有足够的横向破裂抵抗力,而没有使存储器功能恶化。
发明人坚持不懈地进行研究和实验,且发现如果有意在半导体器件的背面中提供比常规应变层薄很多的应变层,则会获得足够的横向破裂抵抗力,而不使存储器元件的功能恶化。
即,根据本发明的第一方面,作为实现了上述第一目的的包括半导体存储器元件的半导体器件,提供了一种包括半导体存储器元件的半导体器件,其中在半导体器件的背面上形成具有0.20μm或更小厚度的应变层。
应变层的厚度优选为0.05μm或更厚。优选通过研磨部件研磨半导体器件的背面来产生应变层,通过用粘接材料粘接具有4μm或更小粒径的金刚石磨粒形成所述研磨部件。
根据本发明的第二方面,作为实现了上述第二目的的半导体器件的制造方法,提供了一种半导体器件的制造方法,包括分割晶片,其中通过以格状图案排列的渠道在晶片的表面上限定多个矩形区域,且在各个矩形区域中设置一个半导体存储器元件,沿着渠道来将所述矩形区域分隔成单个的区域,由此形成多个半导体器件,该方法还包括沿着渠道分割晶片之前,在晶片的背面上形成具有0.20μm或更小厚度的应变层。
应变层的厚度优选为0.05μm或更厚。优选通过研磨部件研磨半导体器件的背面来形成该应变层,通过用粘接材料粘接具有4μm或更小粒径的金刚石磨粒形成所述研磨部件。
附图简述
图1是示出应用了根据本发明制造方法的一个优选实施例的晶片的典型实例的透视图;
图2是示出在本发明制造方法的优选实施例中研磨了晶片背面的状态的示意图;
图3是示出根据本发明的半导体器件的一个优选实施例的局部剖面图。
优选实施例
图1示出应用了根据本发明制造方法的优选实施例的晶片。整个用数字2表示的晶片由硅形成,且除了定向平面4之外都是圆形的。在晶片2的面6上,通过以格状图案排列的渠道8来限定多个矩形区域10。在各个矩形区域10中形成包括存储器元件如DRAM或快闪存储器的半导体元件。由于这种晶片2就其本质来说在本领域技术人员中是公知的,所以在此省略了其详细说明。
在本发明中,重要的是研磨晶片2的背面12,由此在晶片2的背面上形成所需厚度的应变层。为了说明的需要参考图2,其示出了研磨晶片2的背面12的方式。在研磨晶片2的背面12之前,将合适的保护板14粘贴到晶片2的面6上。使晶片2面朝下,并放置在卡盘装置16上,晶片2具有粘贴到其面6的合适的保护板14。卡盘装置16具有基本水平的上表面,且在该上表面中形成了许多吸力孔(未示出),该卡盘装置16绕着其基本上垂直延伸的中心轴旋转。将晶片2放置在卡盘装置16的上表面上,并使吸力孔与真空源(未示出)相通,由此将晶片2吸引到卡盘装置16的上表面上。使研磨装置18作用在晶片2的背面12上。研磨装置18包括支撑盘22,支撑盘22固定到基本上垂直延伸的旋转轴20上。在圆周方向上将多个弓形研磨部件24间隔地固定到支撑盘22下表面的外围边缘部分。代替所述多个弓形研磨部件24,可以将以螺旋管形(toroidal)形式连续延伸的单个研磨部件固定到支撑盘22上。在研磨晶片2的背面12时,旋转卡盘装置16,并且同时旋转研磨装置18。将研磨装置18的研磨部件24压在晶片2的背面12上,并在水平方向上相对卡盘装置16来移动研磨装置18。当以这种方式研磨晶片2的背面12,从而将晶片2的厚度减小到所需值时,由于研磨而在晶片2的背面12中形成了微裂纹,且这种微裂纹构成应变层26(图3)。在图3中,以直立的状态绘出了从其表面6剥离了保护板14的晶片2,且用交叉影线表示在背面12中形成的由微裂纹构成的应变层26。
在本发明中,重要的是在晶片2的背面12上形成具有0.20μm或更小厚度t的应变层26,优选其厚度为0.05至0.20μm。为了形成这种非常薄的应变层26,根据发明人的经验,可推荐使用通过合适的粘接材料如陶瓷粘合剂(vitrified bond)或树脂粘合剂粘接具有4μm或更小粒径的金刚石颗粒所形成的研磨部件24。通过在透射电镜下观察晶片2的背面12,可以测量由微裂纹构成的应变层26的厚度t。
通过上述方式研磨晶片2的背面12,从而形成所需厚度的应变层26。然后,沿着渠道8分隔晶片2,由此完成由各个矩形区域10构成的半导体器件。为了沿着渠道8分隔开晶片2,通过其本身众所周知的划片机沿着渠道8足以切割晶片2。
如果需要的话,在研磨晶片2的背面12之前,能够从晶片2的面6沿着渠道8将晶片2切割到预定深度,由此沿着渠道8在晶片2的面6中形成沟槽,且接着研磨晶片2的背面12,由此将晶片2的厚度减小到沟槽的深度。通过该工序,可以单独地分隔开矩形区域10。
实例
提供如图1所示形状的硅晶片准备使用。晶片的直径为8英寸,且其厚度为725μm。在晶片的表面上,限定了750个矩形区域。每个矩形区域测量为5×8mm,且在每个矩形区域中形成DRAM。以如图2所示的方式研磨这种晶片2的背面,以使晶片2的厚度减小到150μm。使用的研磨部件是由通过陶瓷粘合剂粘接的、具有4μm或更小粒径的金刚石颗粒形成的。接着,沿着渠道切割晶片,以制造包括单独分隔开的矩形区域的半导体器件。通过透射电镜观察半导体器件的背面显示出,在半导体器件的背面中形成了具有0.15μm至0.19μm厚度且由微裂纹构成的应变层。测量了半导体器件的横向破裂抵抗力。将结果示于表1中。通过球横向破裂方法(ball transverserupture method)测量了半导体器件的横向破裂抵抗力,该方法包括在圆柱形夹具上放置半导体器件,并将球压在该半导体器件的中心。此外,要求DRAM的制造商来测试半导体器件的存储功能。将测试的结果示于表1中。
比较例1
除了所述研磨部件由具有4至6μm粒径的金刚石颗粒形成之外,以与上述实例相同的方式制造了半导体器件。通过透射电镜观察该半导体器件的背面。发现,在半导体器件的背面中形成了具有接近0.50至1.00μm厚度且由微裂纹构成的应变层。测量了半导体器件的横向破裂抵抗力。将结果示于表1中。此外,要求DRAM的制造商来测试半导体器件的存储功能。将测试的结果示于表1中。
比较例2
除了在研磨了晶片的背面之后,利用由DISCO公司出售的商品名称为“DRY POLISH”的抛光工具将晶片的背面抛光超过1.20μm的厚度外,以与比较例1相同的方式制造半导体器件。当通过透射电镜观察半导体器件的背面时,发现在半导体器件的背面中基本上不存在应变层。测量了半导体器件的横向破裂抵抗力。将结果示于表1中。此外,要求DRAM制造商来测试半导体器件的存储功能。将测试的结果示于表1中。
表1
应变层的厚度(μm) | 横向破裂抵抗力(MPa) | 存储功能下降 | |
实例 | 0.15-0.19 | 910 | 否 |
比较例1 | 0.50-1.00 | 620 | 否 |
比较例2 | 零 | 920 | 是 |
Claims (6)
1、一种包括半导体存储器元件的半导体器件,其中在该半导体器件的背面上已经形成了具有0.20μm或更小厚度的应变层。
2、根据权利要求1所述的包括半导体存储器元件的半导体器件,其中所述应变层的厚度为0.05μm或更厚。
3、根据权利要求1所述的包括半导体存储器元件的半导体器件,其中通过研磨部件研磨该半导体器件的背面已经产生了所述应变层,通过用粘接材料粘接具有4μm或更小粒径的金刚石磨粒形成所述研磨部件。
4、一种半导体器件的制造方法,包括分割晶片,其中通过以格状图案排列的渠道在该晶片的表面上限定多个矩形区域,且在每个矩形区域中设置一个半导体存储器元件,沿着所述渠道来将所述矩形区域分成单个的区域,由此形成多个半导体器件,
还包括在沿着所述渠道分割该晶片之前,在该晶片的背面上形成具有0.20μm或更小厚度的应变层。
5、根据权利要求4所述的半导体器件的制造方法,其中所述应变层的厚度为0.05μm或更厚。
6、根据权利要求4所述的半导体器件的制造方法,还包括通过研磨部件研磨该半导体器件的背面来形成所述应变层,通过用粘接材料粘接具有4μm或更小粒径的金刚石磨粒形成所述研磨部件。
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JP2004135714A JP4878738B2 (ja) | 2004-04-30 | 2004-04-30 | 半導体デバイスの加工方法 |
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JP (1) | JP4878738B2 (zh) |
KR (1) | KR101126651B1 (zh) |
CN (1) | CN100550313C (zh) |
DE (1) | DE102005019357A1 (zh) |
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CN103123913A (zh) * | 2012-07-03 | 2013-05-29 | 上海华力微电子有限公司 | 一种打薄晶圆降低分裂闪存单元失败率的工艺方法 |
CN111487260A (zh) * | 2019-01-25 | 2020-08-04 | 株式会社迪思科 | 检查装置 |
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TWI398915B (zh) | 2013-06-11 |
CN100550313C (zh) | 2009-10-14 |
DE102005019357A1 (de) | 2005-12-01 |
US7459767B2 (en) | 2008-12-02 |
JP2005317846A (ja) | 2005-11-10 |
KR101126651B1 (ko) | 2012-03-26 |
US7592235B2 (en) | 2009-09-22 |
SG116654A1 (en) | 2005-11-28 |
US20050255674A1 (en) | 2005-11-17 |
TW200539339A (en) | 2005-12-01 |
JP4878738B2 (ja) | 2012-02-15 |
KR20060047521A (ko) | 2006-05-18 |
US20060208329A1 (en) | 2006-09-21 |
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