CN108155174B - 包括堆叠芯片的半导体存储器件及具有其的存储模块 - Google Patents
包括堆叠芯片的半导体存储器件及具有其的存储模块 Download PDFInfo
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- CN108155174B CN108155174B CN201711274048.1A CN201711274048A CN108155174B CN 108155174 B CN108155174 B CN 108155174B CN 201711274048 A CN201711274048 A CN 201711274048A CN 108155174 B CN108155174 B CN 108155174B
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- H01L2225/06503—Stacked arrangements of devices
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- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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- H01L2225/06503—Stacked arrangements of devices
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Abstract
本发明构思涉及包括堆叠芯片的半导体存储器件及具有其的存储模块。一种半导体存储器件包括:存储结构,其包括一个堆叠在另一个上的第一集成电路芯片和多个第二集成电路芯片,第一集成电路芯片插置在所述多个第二集成电路芯片中的一对之间;接口单元,其设置在第一集成电路芯片上,存储结构通过接口单元连接到第三电路,并且接口单元将操作信号传输到第一集成电路芯片和所述多个第二集成电路芯片;至少一个芯片间互连器,其与接口单元以及第一集成电路芯片和所述多个第二集成电路芯片连接;以及与接口单元和第三电路连接的外部互连器。
Description
技术领域
本发明构思的示例性实施方式涉及半导体存储器件,更具体地,涉及包括堆叠芯片的半导体存储器件以及具有其的存储模块。
背景技术
半导体封装正被制造成小型且具有高容量。制造成本和工艺技术会限制半导体封装容量。半导体芯片(例如存储芯片)可以一个堆叠在另一个上以增加半导体封装的容量。
存储芯片的堆叠可以包括主芯片(master chip)和多个从芯片(slave chip),在主芯片中提供接口控制电路用于与其它电路通信,多个从芯片与主芯片连接。当外部存储信号被传输到主芯片的控制电路时,主芯片可以响应于存储信号通过芯片间连接器将控制信号传输到每个从芯片。
从芯片离主芯片越远,控制信号通过主芯片与从芯片之间的芯片间连接器的信号路径越长。长的信号路径会导致信号延迟和/或功耗增大。
存储器件中堆叠的从芯片越多,信号延迟会越长且功耗会越高。
发明内容
根据本发明构思的一示例性实施方式,一种半导体存储器件包括:存储结构,其包括一个堆叠在另一个上的第一集成电路芯片和多个第二集成电路芯片,其中第一集成电路芯片插置在所述多个第二集成电路芯片中的一对之间;接口单元,其设置在第一集成电路芯片上,其中存储结构通过接口单元连接到第三电路,以及其中接口单元将操作信号传输到第一集成电路芯片和所述多个第二集成电路芯片;至少一个芯片间互连器,其与接口单元以及第一集成电路芯片和所述多个第二集成电路芯片连接;以及与接口单元和第三电路连接的外部互连器。
根据本发明构思的一示例性实施方式,一种存储模块包括:电路板,其包括内部电路图案和连接到外部电路的接触端子;半导体存储器件,其设置在电路板上,半导体存储器件包括堆叠在电路板上的多个集成电路芯片;以及存储控制器,其设置在电路板上并控制半导体存储器件的操作。半导体存储器件包括:存储结构,其包括所述多个集成电路芯片,其中所述多个集成电路芯片包括一个堆叠在另一个上的第一集成电路芯片和多个第二集成电路芯片,其中第一集成电路芯片插置在所述多个第二集成电路芯片中的一对之间;接口单元,其设置在第一集成电路芯片上,其中存储结构通过接口单元连接到外部电路,以及其中接口单元将操作信号传输到第一集成电路芯片和所述多个第二集成电路芯片;至少一个芯片间互连器,其与接口单元以及第一集成电路芯片和所述多个第二集成电路芯片连接,使得第一集成电路芯片与所述多个第二集成电路芯片之间的操作信号通过所述至少一个芯片间互连器;以及板连接器,其与接口单元和电路板连接,使得存储结构与电路板之间的操作信号通过板连接器。
根据本发明构思的一示例性实施方式,一种存储模块包括:电路板,其包括第一表面、与第一表面相反的第二表面、在第一表面与第二表面之间穿透电路板的至少一个导电图案、以及设置在第二表面上的接触端子,其中接触端子连接到外部电路并连接到所述至少一个导电图案;半导体存储器件,其设置在电路板的第一表面上,半导体存储器件包括多个集成电路芯片;以及存储控制器,其设置在电路板上并控制半导体存储器件的操作。半导体存储器件包括:存储结构,其包括所述多个集成电路芯片,其中所述多个集成电路芯片包括一个堆叠在另一个上的第一集成电路芯片和多个第二集成电路芯片,其中第一集成电路芯片插置在所述多个第二集成电路芯片中的一对之间;接口单元,其设置在第一集成电路芯片上,其中存储结构通过接口单元连接到外部电路,以及其中接口单元将操作信号传输到第一集成电路芯片和所述多个第二集成电路芯片;至少一个芯片间互连器,其与接口单元以及第一集成电路芯片和第二集成电路芯片连接;以及板连接器,其与接口单元和电路板连接,使得存储结构与电路板之间的操作信号通过板连接器。
附图说明
通过参照附图详细描述本发明构思的示例性实施方式,本发明构思的以上及另外的特征将变得更加明显,附图中:
图1是示出根据本发明构思的一示例性实施方式的半导体存储器件的图;
图2是示出根据本发明构思的一示例性实施方式的图1的半导体存储器件的透视图;
图3是示出根据本发明构思的一示例性实施方式的包括图1和2的半导体存储器件的存储模块的剖视图;
图4是示出根据本发明构思的一示例性实施方式的包括图1和2的半导体存储器件的存储模块的剖视图;
图5是示出根据本发明构思的一示例性实施方式的包括图1和2的半导体存储器件的存储模块的剖视图;
图6是示出根据本发明构思的一示例性实施方式的包括图1和2的半导体存储器件的存储模块的剖视图。
具体实施方式
现在将参照附图更全面地描述本发明构思的示例性实施方式。在整个说明书中,相同的附图标记可以指代相同的元件。
图1是示出根据本发明构思的一示例性实施方式的半导体存储器件的图。图2是示出根据本发明构思的一示例性实施方式的图1的半导体存储器件的透视图。
参照图1和2,根据本发明构思的一示例性实施方式的半导体存储器件500可以包括:具有单个第一集成电路芯片110和多个第二集成电路芯片150的堆叠存储结构100、在第一集成电路芯片110上的接口单元200、与接口单元200以及第一集成电路芯片110和第二集成电路芯片150连接的至少一个芯片间互连器300、以及至少一个外部互连器400。所述多个第二集成电路芯片150可以垂直地堆叠,使得第一集成电路芯片110插置在第二集成电路芯片150之间。接口单元200可以用于在堆叠存储结构100与另外的电路之间传输信号。此外,接口单元200可以用于在第一集成电路芯片110与第二集成电路芯片150之间传输信号。至少一个芯片间互连器300可以与接口单元200以及第一集成电路芯片110和第二集成电路芯片150连接,并且可以用于在接口单元200与第一集成电路芯片110和第二集成电路芯片150之间传输信号。至少一个芯片间互连器300可以用作堆叠存储结构100的操作信号的内部信号路径输送器。至少一个外部互连器400可以与接口单元200和另外的电路连接,使得操作信号可以在堆叠存储结构100与另外的电路之间交换。
堆叠存储结构100可以包括可堆叠或布置在预定方向上的多个集成电路芯片。在本发明构思的一示例性实施方式中,一个第一集成电路芯片110可以插置在多个第二集成电路芯片150之间。因此,第二集成电路芯片150可以包括:第一存储器组152,其可以布置在第一集成电路芯片110的第一侧;以及第二存储器组154,其可以布置在第一集成电路芯片110的第二侧。
第二集成电路芯片150可以包括:上存储器组,其可以布置在第一集成电路芯片110的上侧上;以及下存储器组,其可以布置在第一集成电路芯片110的下侧下方。然而,第二集成电路芯片150可以包括可分别布置在第一集成电路芯片110的左侧和右侧的左存储器组和右存储器组。
第一集成电路芯片110可以包括其中可提供接口单元200的主芯片MC。每个第二集成电路芯片150可以包括可通过芯片间互连器300连接到第一集成电路芯片110的从芯片SC。因此,第一集成电路芯片110和第二集成电路芯片150可以像单个芯片组件那样通过芯片间互连器300彼此电连接。
第一集成电路芯片110可以包括接口区域I和存储区域M,在接口区域I中可以布置接口单元200,并且在存储区域M中可以存储数字数据。
具有接口控制电路的接口单元200可以布置在接口区域I中。来自另外的电路的操作信号可以通过使用接口单元200而被控制并传输到堆叠存储结构100。
多个集成电路芯片可以布置在存储区域M中,并且二进制数据可以被存储在集成电路芯片的单元中。第一集成电路芯片110可以包括诸如动态随机存取存储(DRAM)器件的易失性存储器件和/或诸如闪速存储器件的非易失性存储器件。
存储区域M可以选择性地设置在第一集成电路芯片110中。因此,当没有存储区域M设置在第一集成电路芯片110中时,第一集成电路芯片110可以是缓冲主芯片,二进制数据可以不被存储在该缓冲主芯片中。在这种情况下,操作信号可以通过接口单元200被传输到第二集成电路芯片150。缓冲主芯片可以包括具有用于控制堆叠存储结构100的接口控制电路和/或逻辑芯片的接口单元200。
第二集成电路芯片150可以包括至少存储区域M,并且可以包括诸如DRAM器件的易失性存储器件和/或诸如闪速存储器件的非易失性存储器件。
接口单元200可以布置在第一集成电路芯片110上,并且可以控制操作信号并将操作信号从外部电路器件EC传输到堆叠存储结构100。外部电路器件EC可以是例如存储控制器。
接口单元200可以包括可布置在第一集成电路芯片110的焊盘区域上的控制电路、以及用于操作控制电路的操作器件。接口单元200可以通过第一集成电路芯片110的焊盘区域与另外的电路通信。此外,第二集成电路芯片150的每个可以包括焊盘区域。
用于堆叠存储结构100的操作信号可以被施加到接口单元200并且可以由接口单元200的控制电路处理。然后,操作信号可以通过芯片间互连器300由接口单元200单独地传输到第一集成电路芯片110和第二集成电路芯片150。用于堆叠存储结构100的操作信号可以包括到第一集成电路芯片110和第二集成电路芯片150的每个的地址信号、数据呼叫信号、数据传输信号和各种指令信号。
芯片间互连器300可以连接接口单元200与第一集成电路芯片110和第二集成电路芯片150,并且可以用于在堆叠存储结构100内传输信号。
芯片间互连器300可以包括可连接到堆叠存储结构100的相邻集成电路芯片的穿透电极和键合线。因此,芯片间互连器300的配置和结构可以根据堆叠存储结构100的配置和结构而变化。
由于接口单元200可以设置在第一集成电路芯片110的焊盘区域上,并且芯片间互连器300可以连接到第一集成电路芯片110和第二集成电路芯片150的每个的焊盘区域,所以第一集成电路芯片110和第二集成电路芯片150可以通过芯片间互连器300顺序地连接到接口单元200。
半导体存储器件500中的内部信号以及用于与另外的电路(例如外部系统)通信的外部信号可以由接口单元200控制。用于访问堆叠存储结构100中的二进制数据的数据参考信号以及用于将数据从堆叠存储结构100传输到另外的电路的数据传输信号可以由接口单元200系统地控制。
由于接口单元200可以设置在第一集成电路芯片110上,并且由于第一集成电路芯片110插置在一对第二集成电路芯片150之间,所以芯片间互连器300可以包括第一互连器组310和第二互连器组320。第一互连器组310可以与第一集成电路芯片110和第一存储器组152连接,第二互连器组320可以与第一集成电路芯片110和第二存储器组154连接。由于第二集成电路芯片150可以顺序地垂直堆叠或者水平地布置,所以第一集成电路芯片110和第一存储器组152的第二集成电路芯片152a、152b和152c可以通过第一互连器组310彼此顺序地连接,并且可以连接到第一集成电路芯片110。此外,第二存储器组154的第二集成电路芯片154a、154b和154c可以通过第二互连器组320彼此顺序地连接,并且可以连接到第一集成电路芯片110。
因此,用于操作第一存储器组152的第一操作信号S1可以通过第一互连器组310传输,用于操作第二存储器组154的第二操作信号S2可以独立于第一操作信号S1地通过第二互连器组320传输。因此,从主芯片MC到从芯片SC的最大信号路径的长度可以减小至常规信号路径的长度的一半。因此,可以减小半导体存储器件500中的芯片间互连器300的传输负载。
相邻的主芯片MC与从芯片SC之间或相邻的从芯片SC之间的芯片间互连器300的数量和分布可以根据堆叠存储结构100的配置而变化。设置在相邻的芯片之间的芯片间互连器300的数量越大,自主芯片MC到从芯片SC的信号路径的长度越短。因此,连接到主芯片MC的从芯片SC的数量越多,芯片间互连器300的传输负载可以被减小得越多。例如,在高容量半导体存储器件500(例如具有多个从芯片SC的半导体存储器件500)中,芯片间互连器300的传输负载的减小可以较大。因此,当集成电路芯片的堆叠数量相对较大时,可以增大半导体存储器件500的操作可靠性。
虽然图1和2示出了三个从芯片SC设置在主芯片MC的两个相反侧的每个上,但是在主芯片MC的两个相反侧的每个上的从芯片SC的数量可以根据需要而变化。例如,在主芯片MC的两个相反侧的每个上的从芯片SC的数量可以基于半导体存储器件500的存储容量而变化。
通过将主芯片MC放置在第二集成电路芯片150的中间,从主芯片MC到第一存储器组152中的最上面的从芯片152c的芯片间互连器300的信号路径的长度可以减小至其中主芯片MC位于堆叠存储结构的底部的常规半导体存储器件的信号路径的长度的一半。因此,芯片间互连器300的传输负载可以减小至常规芯片间互连器的传输负载的大约一半。如上所述,芯片间互连器300的数量越多并且从芯片SC的数量越多,芯片间互连器300的传输负载可以被减少得越多。
外部互连器400可以与接口单元200和外部电路器件EC连接。外部互连器400可以提供堆叠存储结构100与外部电路器件EC之间的信号路径。外部互连器400可以包括可与接口单元200和外部电路器件EC连接的键合线或凸块结构。
外部互连器400的结构和配置可以根据堆叠存储结构100的结构和配置而变化。因此,芯片间互连器300和外部互连器400的结构可以根据堆叠存储结构100的结构和配置被选择。
当堆叠存储结构100包括多个垂直堆叠的集成电路芯片时,芯片间互连器300可以是诸如穿通硅通路(TSV)的穿透电极,外部互连器400可以是在接口单元200与外部电路器件EC之间的键合线。
在本发明构思的一示例性实施方式中,当堆叠存储结构100包括多个水平堆叠的集成电路芯片时,芯片间互连器300可以是诸如穿通硅通路(TSV)的穿透电极,外部互连器400可以是在接口单元200与外部电路器件EC之间的凸块结构。
在本发明构思的一示例性实施方式中,当堆叠存储结构100包括多个堆叠的且偏移的集成电路芯片(例如集成电路芯片的台阶状堆叠)时,芯片间互连器300可以是可与相邻芯片的焊盘区域连接的芯片间键合线,外部互连器400可以包括在接口单元200与外部电路器件EC之间的板键合线。
根据本发明构思的一示例性实施方式,在半导体存储器件500中,具有接口单元200的主芯片MC可以插置在从芯片SC之间,并且芯片间互连器300的信号路径的长度可以被缩短。因此,可以减小芯片间互连器300的信号传输负载,并且可以增大半导体存储器件500的操作可靠性。
半导体存储器件500可以以各种配置和结构安装在电路板上以制造各种存储模块。
图3是示出根据本发明构思的一示例性实施方式的包括图1和2的半导体存储器件的存储模块的剖视图。
参照图3,根据本发明构思的一示例性实施方式的存储模块1000可以包括:具有内部电路图案620和接触端子630的电路板600、设置在电路板600上的至少一个半导体存储器件500、以及设置在电路板600上的存储控制器700。接触端子630将存储模块1000与另外的电路电连接。电路板600可以包括可堆叠在电路板600上的多个集成电路芯片。存储控制器700可以控制半导体存储器件500的操作。
图3的半导体存储器件500可以具有与图1和2的半导体存储器件500基本相同的结构和配置。将理解,在没有提供对任何附图中的元件的描述的情况下,未描述的元件可以与说明书中其它地方描述的对应元件相似或相同。
在本发明构思的一示例性实施方式中,第一集成电路芯片110和第二集成电路芯片150可以以倒装芯片结构安装在电路板600上,并且外部互连器400可以连接到电路板600的接合焊盘B。
可以是半导体存储器件500的主芯片MC的第一集成电路芯片110可以例如在第一集成电路芯片110的中央部分处包括接口单元200。接口单元200可以连接到第一集成电路芯片110的接触焊盘C。芯片间互连器300可以在第一集成电路芯片110的中央部分处接触接口单元200。芯片间互连器300可以包括诸如TSV的穿透电极。
在本发明构思的一示例性实施方式中,第一集成电路芯片110和第二集成电路芯片150可以堆叠在电路板600上。例如,第一集成电路芯片110和第二集成电路芯片150可以垂直地堆叠,所以第一集成电路芯片110和第二集成电路芯片150的边缘可以在基本上垂直于电路板600的其上设置接合焊盘B的表面的方向上彼此对准。因此,第二集成电路芯片150可以包括布置在第一集成电路芯片110的上侧上的上存储器组152'、以及布置在第一集成电路芯片110的下侧上的下存储器组154'。芯片间互连器300可以包括可与第一集成电路芯片110和上存储器组152'连接的上穿透电极310'、以及可与第一集成电路芯片110和下存储器组154'连接的下穿透电极320'。
操作信号可以从接口单元200被单独地传输到上存储器组152'和下存储器组154',因此,可以减小从主芯片MC到最上面/最下面的从芯片SC的信号路径。
外部互连器400可以包括可连接到第一集成电路芯片110的接触焊盘C并且可连接到电路板600的接合焊盘B的板键合线(例如板连接器)。因此,用于操作半导体存储器件500的操作信号可以从另外的电路施加到电路板600,并且可以在存储控制器700的控制下到达接口单元200。
电路板600可以包括具有电绝缘材料和耐热材料的主体610。电路板600可以是柔性的或刚性的。多个内部电路图案620设置在主体610中,并且多个接触端子630可以布置在主体610的后表面上用于与另外的电路通信。
电路板600的主体610可以包括例如热固性塑料,诸如环氧树脂或聚酰亚胺。或者,电路板600的主体610可以是用诸如液晶聚酯膜和聚酰胺膜的耐热有机膜涂布的板。内部电路图案620可以是设置在主体610中的导电线或布线。内部电路图案620可以包括用于供应电力的电力线、用于与半导体存储器件500通信数据信号的多个信号线、以及用于将信号线和电力线电接地的地线。内部电路图案620中包括的导电线或布线可以通过绝缘层彼此电绝缘。电路板600可以包括其中内部电路图案620可以通过印刷工艺形成的印刷电路板(PCB)。
内部电路图案620可以连接到主体610的接合焊盘B,使得半导体存储器件500可以通过接合焊盘B和内部电路图案620电连接到另外的电路。
在电路板600的上表面上的接合焊盘B可以连接到第一集成电路芯片110的可连接到接口单元200的接触焊盘C。在电路板600的后表面上的接合焊盘B可以连接到可与另外的电路连接的接触端子630。接触端子630可以包括多个焊料球。因此,存储模块1000可以具有用于电连接到另外的电路的球栅阵列(BGA)结构。
存储控制器700可以包括可安装在电路板600上的另外的芯片。此外,存储控制器700可以包括可通过印刷工艺印刷在主体610中的内部控制电路图案。
因此,用于操作半导体存储器件500的操作信号可以从另外的电路施加到接触端子630,并且可以经由内部电路图案620处于存储控制器700的控制之下。然后,操作信号可以经由内部电路图案620、接合焊盘B、其为板键合线的外部互连器400和第一集成电路芯片110的接触焊盘C被传输到接口单元200。
操作信号可以根据存储控制器700的控制特性包括可传输到上存储器组152'的上操作信号SU以及可传输到下存储器组154'的下操作信号SD。上操作信号SU和下操作信号SD可以通过接口单元200被单独地传输到上存储器组152'和下存储器组154'。
用于传输半导体存储器件500的二进制数据的数据信号可以通过其为穿透电极的芯片间互连器300被传输到接口单元200,并且可以被调制成可通过接口单元200与另外的电路通信的公共数据信号。然后,公共数据信号可以通过接口单元200被传输到存储控制器700。
存储控制器700可以包括用于基于芯片地址映射(chip address map)从堆叠存储结构100中选择芯片的芯片选择器、用于响应于刷新指令而顺序地生成刷新信号的刷新信号发生器、以及信号分析器,其分析信号并在其为穿透电极的芯片间互连器300与其为板键合线的外部互连器400之间选择信号传输模式。
因此,存储控制器700可以控制可施加于半导体存储器件500的操作信号以及可从半导体存储器件500传输的数据信号,以这样的方式使得存储模块1000可以与另外的电路系统地通信。
虽然在图3中示出了单个半导体存储器件500设置在电路板600上,但要理解的是,多个半导体存储器件500可以取决于存储模块1000的存储容量和/或操作性能而设置在电路板600上。
根据本发明构思的一示例性实施方式,在存储模块1000中,主芯片MC可以插置在从芯片SC之间,因而可以缩短其为穿透电极的芯片间互连器300的信号路径的长度。因此,可以减小存储模块1000中的其为穿透电极的芯片间互连器300的信号传输负载,并且可以增大存储模块1000的操作可靠性。
其为穿透电极的芯片间互连器300的数量可以取决于芯片间互连器300与外部互连器400之间的信号传输模式、芯片间互连器300的数据传输速率、以及堆叠在堆叠存储结构100中的集成电路芯片的数量而增加。芯片间互连器300的数量越多,芯片间互连器300的信号传输负载越低。因此,当存储模块1000的存储容量增大时,信号传输负载的减小可以在存储模块1000中增加。
图4是示出根据本发明构思的一示例性实施方式的包括图1和2的半导体存储器件的存储模块的剖视图。在图4中,除了主芯片MC包括接口单元200而没有存储单元M之外,存储模块1001具有与图3中所示的存储模块1000基本相同的结构。
参照图4,存储模块1001可以包括安装在电路板600上的半导体存储器件501,其包括一个第一集成电路芯片111和多个第二集成电路芯片150。第一集成电路芯片111可以在其中央部分处包括接口单元200,并且可以不包括存储区域M。第二集成电路芯片150可以包括存储区域M,并且可以不包括接口单元200。第一集成电路芯片111可以在半导体存储器件501中插置在第二集成电路芯片150之间。因此,第一集成电路芯片111可以是缓冲主芯片MC,并且多个第二集成电路芯片150的每个可以是半导体存储器件501中的从芯片SC。
因此,第一集成电路芯片111可以具有各种配置和结构,只要仅接口单元200可以设置在第一集成电路芯片111上而没有存储区域M,并且第一集成电路芯片111可以插置在第二集成电路芯片150之间。
当第一集成电路芯片111具有与第二集成电路芯片150相同的尺寸并且接口区域I占据第一集成电路芯片111的整个区域时,增加数量的各种控制电路可以设置在第一集成电路芯片111上。例如,额外数量的电路可以设置在接口单元200中。因此,接口单元200可以进行增加数量的操作。在本发明构思的一示例性实施方式中,接口单元200还可以包括存储控制器700的一些元件,诸如刷新信号发生器和信号分析器。
此外,用于控制半导体存储器件501的操作的另外的控制芯片可以与第一集成电路芯片111组合(例如添加到第一集成电路芯片111)。例如,用于控制第二集成电路芯片150的操作的另外的逻辑芯片可以进一步设置在第一集成电路芯片111上。当第二集成电路芯片150包括诸如动态随机存取存储(DRAM)器件和/或闪速存储器件的存储器件时,具有逻辑芯片的第一集成电路芯片111可以是用于控制存储器件的逻辑器件。例如,逻辑器件可以补充存储控制器700。
虽然图4公开了缓冲主芯片111可以具有与从芯片SC相同的尺寸,但是将理解,缓冲主芯片111的尺寸可以小于从芯片SC的尺寸,只要所需电路能与接口单元200的面积相适应。
图5是示出根据本发明构思的一示例性实施方式的包括图1和2的半导体存储器件的存储模块的剖视图。在图5中,除了主芯片MC和从芯片SC可以在电路板上偏移成阶梯结构(例如成台阶状堆叠)之外,存储模块1002具有与图3中所示的存储模块1000基本相同的结构。因此,键合线被提供为芯片间互连器300。因此,在图5中,相同的附图标记可以表示与参照图3描述的相同的元件,并且可以省略其任何另外的详细描述。
参照图5,存储模块1002可以包括半导体存储器件502,其中单个第一集成电路芯片110和多个第二集成电路芯片150可以垂直地堆叠在电路板600上。第一集成电路芯片110和第二集成电路芯片150可以以这样的配置安装在电路板上:每个芯片110和150的有源面可以面朝上(例如远离电路板600),并且每个芯片可以沿着电路板600的上表面相对于相邻的芯片偏移相同的偏移距离d。因此,堆叠存储结构100可以成形为阶梯结构,并且一对相邻的芯片可以构成其中可暴露芯片110和150的有源面的边缘部分的台阶。
在本发明构思的一示例性实施方式中,第一集成电路芯片110和第二集成电路芯片150可以包括一边缘,其中接触焊盘C和接口单元200可以以接口单元200可与每个芯片110和150的接触焊盘C接触的这样的方式设置。
第一集成电路芯片110和第二集成电路芯片150的每个可以在电路板600上垂直地堆叠成阶梯结构,使得每个芯片110和150的接触焊盘C可以被暴露并且通过芯片间键合线302彼此连接。因此,上存储器组152'的第二集成电路芯片152'a至152'c的接触焊盘C可以通过上芯片间键合线312彼此连接,下存储器组154'的第二集成电路芯片154'a至154'c的接触焊盘C可以通过下芯片间键合线322彼此连接。上芯片间键合线312和下芯片间键合线322可以单独地连接到第一集成电路芯片110的接触焊盘C。
因此,操作信号可以被分成上操作信号SU和下操作信号SD,其可以分别通过上芯片间键合线312和下芯片间键合线322单独传输到上存储器组152'和下存储器组154'。例如,操作信号可以包括上操作信号SU和下操作信号SD,并且可以通过相应芯片间键合线312和322彼此独立地被单独地传输,从而最小化从接口单元200到最上面/最下面的从芯片SC的信号路径的长度。
外部互连器400可以包括板键合线,其可以与第一集成电路芯片110的接触焊盘C和电路板600的接合焊盘B连接。因此,操作信号可以通过另外的电路被施加到电路板600,然后可以在存储控制器700的控制下通过其为板键合线的外部互连器400传输到接口单元200。
外部互连器400、电路板600和存储控制器700可以具有与图3中所示的存储模块1000的那些基本相同的结构。对准引导件可以进一步设置在存储模块1002中以防止第一集成电路芯片110和第二集成电路芯片150的未对准以及上芯片间键合线312和下芯片间键合线322的切断(例如断开)。
图6是示出根据本发明构思的一示例性实施方式的包括图1和2的半导体存储器件的存储模块的剖视图。在图6中,除了主芯片MC和从芯片SC可以基本上垂直地布置在电路板600上之外,存储模块1003具有与图3中所示的存储模块1000基本相同的结构,如图6中所示。主芯片MC和从芯片SC可以沿着电路板600的上表面彼此间隔开。因此,凸块结构可以被提供成外部互连器400。
参照图6,存储模块1003可以包括半导体存储器件503,其中单个第一集成电路芯片110和多个第二集成电路芯片150可以沿着电路板600的上表面并且基本垂直于电路板600的上表面彼此平行地布置在电路板600上。因此,第一集成电路芯片110和第二集成电路芯片150可以以用作主芯片MC的第一集成电路芯片110可插置在用作从芯片SC的第二集成电路芯片150之间的这样的方式布置在电路板600上。
接口单元200可以布置在第一集成电路芯片110和相邻的第二集成电路芯片150上,并且接口单元200和第二集成电路芯片150可以通过其为穿透电极的芯片间互连器300彼此连接。接口单元200可以通过外部互连器400连接到内部电路图案620或接合焊盘B。
第二集成电路芯片150可以包括可布置在第一集成电路芯片110的左侧的左存储器组156以及可布置在第一集成电路芯片110的右侧的右存储器组158。此外,其为穿透电极的芯片间互连器300可以包括可与第一集成电路芯片110和左存储器组156连接的左穿透电极350以及可与第一集成电路芯片110和右存储器组158连接的右穿透电极360。
因此,操作信号可以根据存储控制器700的控制特性包括可传输到左存储器组156的左操作信号SL以及可传输到右存储器组158的右操作信号SR。左操作信号SL和右操作信号SR可以通过接口单元200被单独地传输到左存储器组156和右存储器组158,因而最小化从接口单元200到最右/最左的从芯片SC的芯片间互连器的信号路径的长度。
可与接口单元200和电路板600连接的外部互连器400可以包括凸块结构403,其可以与电路板600的接合焊盘B及第一集成电路芯片110的接触焊盘C连接。凸块结构403也可以与第一集成电路芯片110的接触焊盘C一起或者代替第一集成电路芯片110的接触焊盘C连接到接口单元200。凸块结构403可以设置在第一集成电路芯片110的左侧和/或右侧。
凸块结构403可以包括凸块焊盘403a以及可插置在凸块焊盘403a与电路板600的接合焊盘B之间的导电凸块403b。凸块焊盘403a可以设置在第一集成电路芯片110的有源面和/或背面上,使得凸块焊盘403a可以与第一集成电路芯片110的接触焊盘C接触,并且可以与左穿透电极350和右穿透电极360绝缘。主接触区域可以被提供在电路板600上,并且半导体存储器件503可以以凸块结构403可与主接触区域对准的这样的方式安装在电路板600上。
因此,操作信号可以通过另外的电路被施加到电路板600,然后可以在存储控制器700的控制下通过凸块结构403被传输到接口单元200。
所公开的存储模块1000至1003可以安装在各种电子系统的主板上,并且可以是电子系统的存储构件。存储模块1000至1003可以被提供成用于台式计算机、笔记本计算机、服务器系统、诸如智能电话的移动系统等的存储系统。
在半导体存储器件500和包括其的存储模块1000至1003中,具有接口单元200的主芯片MC可以插置在半导体存储器件中的从芯片SC之间。因此,可以缩短芯片间互连器300的信号路径的长度。因此,在堆叠存储结构中可以减小芯片间连接器300的信号传输负载。因此,可以增大半导体存储器件500的操作可靠性。
虽然已经参照本发明构思的示例性实施方式具体示出和描述了本发明构思,但是对本领域普通技术人员将明显的是,可以在此进行在形式和细节上的各种改变而不背离本发明构思的精神和范围。
本申请要求享有2016年12月6日在韩国知识产权局提交的韩国专利申请第10-2016-0164946号的优先权,其公开通过引用全文合并于此。
Claims (20)
1.一种半导体存储器件,包括:
存储结构,其包括一个堆叠在另一个上的第一集成电路芯片和多个第二集成电路芯片,其中所述第一集成电路芯片插置在所述多个第二集成电路芯片的一对之间;
接口单元,其设置在所述第一集成电路芯片上,其中所述存储结构通过所述接口单元连接到第三电路,以及其中所述接口单元将操作信号传输到所述第一集成电路芯片和所述多个第二集成电路芯片;
至少一个芯片间互连器,所述至少一个芯片间互连器与所述接口单元以及所述第一集成电路芯片和所述多个第二集成电路芯片连接;以及
外部互连器,其与所述接口单元和所述第三电路连接。
2.根据权利要求1所述的半导体存储器件,还包括多个芯片间互连器,
其中所述多个第二集成电路芯片包括布置在所述第一集成电路芯片的第一侧处的第一存储器组及布置在所述第一集成电路芯片的第二侧处的第二存储器组,以及
其中所述多个芯片间互连器包括将所述第一集成电路芯片与所述第一存储器组连接的第一互连器组及将所述第一集成电路芯片与所述第二存储器组连接的第二互连器组。
3.根据权利要求2所述的半导体存储器件,其中所述多个芯片间互连器包括穿透电极,以及
其中所述外部互连器包括连接到所述接口单元的键合线。
4.根据权利要求2所述的半导体存储器件,其中所述多个芯片间互连器包括穿透电极,以及
其中所述外部互连器包括连接到所述接口单元的凸块结构。
5.根据权利要求2所述的半导体存储器件,其中所述多个芯片间互连器包括芯片间键合线,以及
其中所述外部互连器包括连接到所述接口单元的板键合线。
6.根据权利要求1所述的半导体存储器件,其中所述第一集成电路芯片包括主芯片,所述主芯片包括所述接口单元和用于存储数据的存储单元,以及
其中所述多个第二集成电路芯片的每个包括从芯片,所述从芯片包括用于存储数据的存储单元。
7.根据权利要求1所述的半导体存储器件,其中所述第一集成电路芯片包括缓冲主芯片,所述缓冲主芯片在其中包括所述接口单元,其中所述第一集成电路芯片不包括存储单元,以及
其中所述多个第二集成电路芯片的每个包括从芯片,所述从芯片包括用于存储数据的存储单元。
8.一种存储模块,包括:
电路板,其包括内部电路图案和连接到外部电路的接触端子;
半导体存储器件,其设置在所述电路板上,所述半导体存储器件包括堆叠在所述电路板上的多个集成电路芯片;以及
存储控制器,其设置在所述电路板上并控制所述半导体存储器件的操作;
其中所述半导体存储器件包括:
存储结构,其包括所述多个集成电路芯片,其中所述多个集成电路芯片包括一个堆叠在另一个上的第一集成电路芯片和多个第二集成电路芯片,其中所述第一集成电路芯片插置在所述多个第二集成电路芯片的一对之间;
接口单元,其设置在所述第一集成电路芯片上,其中所述存储结构通过所述接口单元连接到所述外部电路,以及其中所述接口单元将操作信号传输到所述第一集成电路芯片和所述多个第二集成电路芯片;
至少一个芯片间互连器,所述至少一个芯片间互连器与所述接口单元以及所述第一集成电路芯片和所述多个第二集成电路芯片连接,使得所述第一集成电路芯片与所述多个第二集成电路芯片之间的操作信号通过所述至少一个芯片间互连器;以及
板连接器,其与所述接口单元和所述电路板连接,使得所述存储结构与所述电路板之间的操作信号通过所述板连接器。
9.根据权利要求8所述的存储模块,其中所述第一集成电路芯片和所述多个第二集成电路芯片中的至少一个第二集成电路芯片沿其延伸的平面基本上平行于所述电路板沿其延伸的平面。
10.根据权利要求9所述的存储模块,还包括多个芯片间互连器,
其中所述多个第二集成电路芯片包括设置在所述第一集成电路芯片的第一侧上的上存储器组及设置在所述第一集成电路芯片的第二侧上的下存储器组,所述第一侧和所述第二侧彼此相反,
其中所述多个芯片间互连器包括将所述第一集成电路芯片与所述上存储器组连接的上穿透电极和将所述第一集成电路芯片与所述下存储器组连接的下穿透电极,以及
其中所述板连接器包括将所述电路板与所述接口单元连接的板键合线。
11.根据权利要求8所述的存储模块,其中所述第一集成电路芯片和所述多个第二集成电路芯片布置成台阶状结构。
12.根据权利要求11所述的存储模块,还包括多个芯片间互连器,
其中所述多个第二集成电路芯片包括设置在所述第一集成电路芯片的第一侧上的上存储器组和设置在所述第一集成电路芯片的第二侧上的下存储器组,所述第一侧和所述第二侧彼此相反,
其中所述多个芯片间互连器包括将所述第一集成电路芯片与所述上存储器组连接的上键合线和将所述第一集成电路芯片与所述下存储器组连接的下键合线,以及
其中所述板连接器包括板键合线,所述板键合线将所述电路板与所述接口单元连接。
13.根据权利要求8所述的存储模块,其中所述第一集成电路芯片和所述多个第二集成电路芯片中的至少一个第二集成电路芯片沿其延伸的平面交叉所述电路板沿其延伸的平面。
14.根据权利要求13所述的存储模块,还包括多个芯片间互连器,
其中所述多个第二集成电路芯片包括设置在所述第一集成电路芯片的第一侧上的左存储器组和设置在所述第一集成电路芯片的第二侧上的右存储器组,
其中所述多个芯片间互连器包括将所述第一集成电路芯片与所述左存储器组连接的第一穿透电极和将所述第一集成电路芯片与所述右存储器组连接的第二穿透电极,以及
其中所述板连接器包括凸块结构,所述凸块结构将所述电路板与所述接口单元连接。
15.根据权利要求14所述的存储模块,其中所述凸块结构包括凸块焊盘和连接到所述凸块焊盘的导电凸块,
其中所述凸块结构插置在所述第一集成电路芯片与所述多个第二集成电路芯片之间,以及
其中所述凸块结构连接到所述接口单元。
16.一种存储模块,包括:
电路板,其包括第一表面、与所述第一表面相反的第二表面、在所述第一表面与所述第二表面之间穿透所述电路板的至少一个导电图案、以及设置在所述第二表面上的接触端子,其中所述接触端子连接到外部电路和所述至少一个导电图案;
半导体存储器件,其设置在所述电路板的所述第一表面上,所述半导体存储器件包括多个集成电路芯片;以及
存储控制器,其设置在所述电路板上并控制所述半导体存储器件的操作,
其中所述半导体存储器件包括:
存储结构,其包括所述多个集成电路芯片,其中所述多个集成电路芯片包括一个堆叠在另一个上的第一集成电路芯片和多个第二集成电路芯片,其中所述第一集成电路芯片插置在所述多个第二集成电路芯片的一对之间;
接口单元,其设置在所述第一集成电路芯片上,其中所述存储结构通过所述接口单元连接到所述外部电路,以及其中所述接口单元将操作信号传输到所述第一集成电路芯片和所述多个第二集成电路芯片;
至少一个芯片间互连器,所述至少一个芯片间互连器与所述接口单元以及所述第一集成电路芯片和所述第二集成电路芯片连接;以及
板连接器,其与所述接口单元和所述电路板连接,使得所述存储结构与所述电路板之间的操作信号通过所述板连接器。
17.根据权利要求16所述的存储模块,还包括设置在所述第一集成电路芯片上的第一焊盘和设置在所述电路板的所述第一表面上的第二焊盘,
其中所述板连接器包括连接到所述第一焊盘和所述第二焊盘的导线。
18.根据权利要求17所述的存储模块,其中所述第一焊盘设置在所述第一集成电路芯片的边缘处。
19.根据权利要求16所述的存储模块,还包括多个芯片间互连器,
其中,当所述第一集成电路芯片包括第一侧以及与所述第一侧相反的第二侧时,所述多个第二集成电路芯片包括设置在所述第一集成电路芯片的所述第一侧上的第一组芯片和设置在所述第一集成电路芯片的所述第二侧上的第二组芯片,
其中所述第一组芯片通过所述多个芯片间互连器中的第一芯片间互连器连接到所述第一集成电路芯片,以及
其中所述第二组芯片通过所述多个芯片间互连器中的第二芯片间互连器连接到所述第一集成电路芯片。
20.根据权利要求19所述的存储模块,其中所述第一芯片间互连器穿透所述第一组芯片,所述第二芯片间互连器穿透所述第二组芯片。
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