SIGMICRO

A processor architecture is presented which enables the constructs typical of HLLs to be mapped into the constructs typical of microcode. This mapping is provided only for selected HLL primitives and HLL statements with a relatively small number of ...

This paper describes the architecture and microcode organization of an Interprocessor Communications Controller (ICC) for a multi-microcomputer system employing a fully parallel crossbar switch. The communications controller provides fast data ...

The design of a host machine architecture for implementing an existing image machine architecture is considered. The proposed microarchitecture uses a microprogrammed control unit to emulate the Motorola MC6809 microprocessor architecture.

The detailed ...

This paper describes the architecture of a microprogrammed processor currently under development that addresses specific program objectives. These objectives include system throughput, ISA flexibility and software transportability. The design project is ...

It has been found that pipelining at the firmware level of machine organization can provide significant execution time benefits for certain types of instructions. The essential concept involved with this approach is the pipelining of operations within ...

Fast virtual-address translation and instruction parsing are two hard problems of implementing many modern architectures, including the VAX computer architecture. Meeting the additional constraint of fitting a VAX 11/780-computer-speed implementation ...

This paper presents an overview of the software tools used in the development of the microcode for Digital's VLSI VAX Microcomputers. The software tools effort consisted of five basic areas: assembly, simulation, verification, and statistical analysis.

Design verification as part of development provides an opportunity to correct design errors, improve performance characteristics, and optimize hardware. This paper presents the strategy and an overview of the verification performed in the development of ...

A custom test system was developed to assist in the integration of the microcode and components of a VLSI VAX Microcomputer prototype system. Microcode debugging ease (on the hardware) and leverage is gained by hierarchical accumulation of access and ...

A VLSI VAX microcomputer, which implements the native VAX computer architecture and instruction set, uses 16K by 40 bits of ROM control store. To decrease the cost of making changes to released microcode, the hardware supports a patching mechanism ...

Fisher's trace scheduling procedure for global compaction has proven to be able to produce significant reduction in execution time of compacted microcode, however extra space may be sometimes required during bookkeeping, and the efficacy of compaction ...

This paper presents new techniques for generating PLA microcode with the overall goal of implementing functions or algorithms in VLSI. The microcode is appropriate for PLA-based microarchitectures with powerful sequencing capabilities already proposed. ...

An optimizing loader has been designed and developed for two-level microprograms of a multiprocessor computer. In the computer, a microinstruction activates nanoprograms in multiprocessors, specifying nanoprogram start address and the processors to be ...

An algorithm has been developed to compact the micro-operations of horizontal microcode into optimal segments of straight-line microinstructions. The Quine modified (QM) algorithm generates solutions for 24 micro-operations in 2 sec. of VAX processing ...

The work described in this paper is directed at the structure and construction of simulator-based systems for the development and testing of microcode. While the value of such software tools is widely recognised, their availability in the early stages ...

TDL is an interpreter for a high level test language used in the development of hardware and microcode. A user can supply commands interactively at a terminal, or from a prepared command file to facilitate automated testing. TDL can communicate to ...

In a computer design project where software and hardware development proceed in parallel, it is essential that some form of simulation is available early so that the software can be breadboarded before the hardware is stable. The simulator must be ...

The NP-Completeness of the selection problem of vertical migration candidates is shown by reducing it to the NP-complete knapsack problem. Based on approximation algorithms for the latter problem a new algorithm is presented, which takes into account ...

Implementing vertical migrations involves synthesizing new microcoded instructions from selected parts of HLL programs and loading the microcode into the computer's control memory. Ideally, both of these tasks are done automatically so that programs can ...

The aim of this work is to construct an automated migration system from software into firmware for functions or algorithms with complex logical structure. The approach is based on an already developed structured microcontrol scheme endowed with compound ...

Migration of functionality into microcode for the purposes of performance improvement and increased security may be oriented toward the migration of abstract data types. This provides a model of migration consistent with current models of machine ...

This paper describes a case study in the implementation of a special purpose architecture on a particular microprogrammable engine. The host engine used is the VAX-11/780; the target architecture is one tailored for implementing recursive descent ...

Prolog has become a subject of much discussion of late. It has been suggested as the logical language for programming expert systems. A parallel variant is said to be the language of the Japanese 5th Generation Project. In this paper the standard ...

A modified version of D. Warren's sequential Prolog machine architecture is described. Data and instruction formats are given. A microcoded host architecture is also described, with formats and examples presented.

The PLM-1 is the first step in the hardware implementation of a heterogeneous MIMD processor for logic programming. This paper describes its ISP architecture, and discusses in detail some of the design decisions relative to its microarchitecture.

This paper describes SDVS (State Delta Verification System), its application to microcode verification, and the verification of a particular example referred to as the H-machine example. The example illustrates how particular microcode that interprets a ...

This paper is a progress report on an experimental system, the state delta verification system (SDVS), for verifying microcode correctness. The goal of this project is to solve some of the problems, both theoretical and engineering, obstructing the ...

Following the software crisis, a firmware crisis has occurred.

Since too much man-power and time is needed to develop microprograms, the ones already produced like software have to be used as long as possible.

This paper describes a general purpose ...

A compiler for the generation of microcode for a high-level microprogramming language is presented. The compiler is target machine independent. The input to the compiler consists of a hardware description, a high-level microprogram and a set of program ...

We have reported on local retargetable microcode generation methods based on the flow graph model in previous papers. In this paper, we consider the extension of these methods to global retargetable microcode generation. This includes intermediate ...