Issue Downloads
Architecting for Artificial Intelligence with Emerging Nanotechnology
Artificial Intelligence is becoming ubiquitous in products and services that we use daily. Although the domain of AI has seen substantial improvements over recent years, its effectiveness is limited by the capabilities of current computing technology. ...
A Survey Describing Beyond Si Transistors and Exploring Their Implications for Future Processors
The advancement of Silicon CMOS technology has led information technology innovation for decades. However, scaling transistors down according to Moore’s law is almost reaching its limitations. To improve system performance, cost, and energy efficiency, ...
Temporal State Machines: Using Temporal Memory to Stitch Time-based Graph Computations
Race logic, an arrival-time-coded logic family, has demonstrated energy and performance improvements for applications ranging from dynamic programming to machine learning. However, the various ad hoc mappings of algorithms into hardware rely on researcher ...
Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach
- Dominik Sisejkovic,
- Farhad Merchant,
- Lennart M. Reimann,
- Harshit Srivastava,
- Ahmed Hallawa,
- Rainer Leupers
Logic locking is a prominent technique to protect the integrity of hardware designs throughout the integrated circuit design and fabrication flow. However, in recent years, the security of locking schemes has been thoroughly challenged by the introduction ...
Attack Mitigation of Hardware Trojans for Thermal Sensing via Micro-ring Resonator in Optical NoCs
As an emerging role in new-generation on-chip communication, optical networks-on-chip (ONoCs) provide ultra-high bandwidth, low latency, and low power dissipation for data transfers. However, the thermo-optic effects of the photonic devices have a great ...
DTA-PUF: Dynamic Timing-aware Physical Unclonable Function for Resource-constrained Devices
In recent years, physical unclonable functions (PUFs) have gained a lot of attention as mechanisms for hardware-rooted device authentication. While the majority of the previously proposed PUFs derive entropy using dedicated circuitry, software PUFs ...
Hardware Trojan Horse Detection through Improved Switching of Dormant Nets
Covert Hardware Trojan Horses (HTH) introduced by malicious attackers during the fabless manufacturing process of integrated circuits (IC) have the potential to cause malignant functions within the circuit. This article employs a Design-for-Security ...
Improving the Quality of FPGA RO-PUF by Principal Component Analysis (PCA)
Ring Oscillator Physical Unclonable Functions (RO-PUFs) exploit the inherent manufacturing process variations, such as systematic and stochastic variations, to generate secret PUF responses that are unique to the device. Stochastic variations are random, ...
Timing-Optimized Hardware Implementation to Accelerate Polynomial Multiplication in the NTRU Algorithm
Post-quantum cryptographic algorithms have emerged to secure communication channels between electronic devices faced with the advent of quantum computers. The performance of post-quantum cryptographic algorithms on embedded systems has to be evaluated to ...
Robust and Attack Resilient Logic Locking with a High Application-Level Impact
Logic locking is a hardware security technique aimed at protecting intellectual property against security threats in the IC supply chain, especially those posed by untrusted fabrication facilities. Such techniques incorporate additional locking circuitry ...
Bridging the Gap between RTL and Software Fault Injection
Protecting programs against hardware fault injection requires accurate software fault models. However, typical models, such as the instruction skip, do not take into account the microarchitecture specificities of a processor. We propose in this article an ...
CONCEALING-Gate: Optical Contactless Probing Resilient Design
- M. Tanjidur Rahman,
- Nusrat Farzana Dipu,
- Dhwani Mehta,
- Shahin Tajik,
- Mark Tehranipoor,
- Navid Asadizanjani
Optical probing, though developed as silicon debugging tools from the chip backside, has shown its capability of extracting secret data, such as cryptographic keys and user identifications, from modern system-on-chip devices. Existing optical probing ...
Improving Deep Learning Networks for Profiled Side-channel Analysis Using Performance Improvement Techniques
The use of deep learning techniques to perform side-channel analysis attracted the attention of many researchers as they obtained good performances with them. Unfortunately, the understanding of the neural networks used to perform side-channel attacks is ...
Software-driven Security Attacks: From Vulnerability Sources to Durable Hardware Defenses
- Lauren Biernacki,
- Mark Gallagher,
- Zhixing Xu,
- Misiker Tadesse Aga,
- Austin Harris,
- Shijia Wei,
- Mohit Tiwari,
- Baris Kasikci,
- Sharad Malik,
- Todd Austin
There is an increasing body of work in the area of hardware defenses for software-driven security attacks. A significant challenge in developing these defenses is that the space of security vulnerabilities and exploits is large and not fully understood. ...
A Lightweight Architecture for Hardware-Based Security in the Emerging Era of Systems of Systems
- Nico Mexis,
- Nikolaos Athanasios Anagnostopoulos,
- Shuai Chen,
- Jan Bambach,
- Tolga Arul,
- Stefan Katzenbeisser
In recent years, a new generation of the Internet of Things (IoT 2.0) is emerging, based on artificial intelligence, the blockchain technology, machine learning, and the constant consolidation of pre-existing systems and subsystems into larger systems. In ...
SILVerIn: Systematic Integrity Verification of Printed Circuit Board Using JTAG Infrastructure
A printed circuit board (PCB) provides necessary mechanical support to an electronic system and acts as a platform for connecting electronic components. Counterfeiting and in-field tampering of PCBs have become significant security concerns in the ...