IEEE Transactions on Very Large Scale Integration (VLSI) Systems

H.264/AVC intra-frame encoding contains several computation-intensive coding tools that form a long data dependency loop that is difficult to speed up. In this paper, we present a low-power and high-performance H.264/AVC intra-frame encoder. We propose ...

This paper presents a novel pixel design for active matrix organic light emitting diode (AM-OLED) displays using nanocrystalline silicon thin-film transistors (TFTs). The proposed pixel design can effectively reduce the variation of its stored display ...

This paper presents an on-chip system with digital serial peripheral interface (SPI) interface that enables accurate programming of floating gate arrays at a high speed. The main component allowing this speedup is a floating point current measuring ...

An internet protocol (IP) router determines the next hop for a packet by finding the longest prefix match. This lookup often occurs in ternary content addressable memory (TCAM), which allows bit masking of the IP address. In this paper, an internet ...

Synchronous clock distribution continues to be the dominant timing methodology for VLSI circuit designs. As processes shrink, clock speeds increase, and die sizes grow, an increasingly larger percentage of the clock period is being lost to skew and ...

The threshold voltage (V_th) of a nanoscale transistor is severely affected by random dopant fluctuations and line-edge roughness. The analysis of these effects usually requires atomistic simulations which are too expensive in computation for statistical ...

Reducing memory accesses is particularly important for digital signal processing (DSP) applications since they are widely used in embedded systems and need to be executed with high performance and low power consumption. In this paper, we propose a ...

On-chip monitoring of environmental information, such as temperature, voltage, and error data, is becoming increasingly important. To address this need, a low-overhead architectural approach to monitor data collection and use in multicore systems is ...

We present a high-speed wide-range parallel counter that achieves high operating frequencies through a novel pipeline partitioning methodology (a counting path and state look-ahead path), using only three simple repeated CMOS-logic module types: an ...

Real-time object detection is becoming necessary for a wide number of applications related to computer vision and image processing, security, bioinformatics, and several other areas. Existing software implementations of object detection algorithms are ...

In partially reconfigurable architectures, system components can be dynamically loaded and unloaded allowing resources to be shared over time. Dynamic system components are represented by partial reconfiguration (PR) modules. In comparison to a static ...

Reconfigurable arrays combine the benefit of spatial execution, typical of hardware solutions, with that of programmability, present in microprocessors. When mapping software applications (or parts of them) onto hardware, however, fine-grain arrays, ...

A design methodology for distributing a buck converter filter for application to 3-D circuits is described. The 3-D filter exploits transmission line properties, permitting the generation and distribution of power supplies to different planes. As ...

A novel two-phase RZ delay-insensitive asynchronous handshaking protocol for on-chip communication has been developed along with an efficient and robust dual-rail circuit implementation (Transmitter/Receiver). Performance was verified using SPICE ...

We propose a new scheme for reducing the test application time in accumulator-based test-pattern generation. Within this framework, we reduce the problem of efficiently generating test-patterns to that of finding the shortest Hamiltonian path in an ...

Functional broadside tests were defined as broadside tests where the scan-in state is a reachable state. This ensures that during the functional capture cycles of the test, the circuit visits states that it can also visit during functional operation. As ...

A reduced-complexity low density parity check (LDPC) layered decoding architecture is proposed using an offset permutation scheme in the switch networks. This method requires only one shuffle network, rather than the two shuffle networks which are used ...

Functional broadside tests were defined to address overtesting that may occur due to the detection of delay faults under nonfunctional operation conditions. Such conditions are made possible by scanning in unreachable states. Functional broadside tests ...

Both test compaction and test data compression methods provide an opportunity for a tester to apply modified versions of each test, in addition to the original test. We take advantage of this opportunity to achieve additional test data volume ...

In this paper, a novel portable and all-digital spread spectrum clock generator (ADSSCG) suitable for system-on-chip (SoC) applications with low-power consumption is presented. The proposed ADSSCG can provide flexible spreading ratios by the proposed ...

A 1.2-V piecewise curvature-corrected CMOS bandgap reference (BGR) is proposed. It features in utilizing piecewise nonlinear curvature-corrected current and rail-to-rail operational amplifier to a conventional first-order current-mode BGR. The corrected ...