Signal Acquisition of High-Speed Periodic Signals Using Incoherent Sub-Sampling and Back-End Signal Reconstruction Algorithms
This paper presents a high-speed periodic signal acquisition technique using incoherent sub-sampling and back-end signal reconstruction algorithms. The signal reconstruction algorithms employ a frequency domain analysis for frequency estimation, and ...
Systematic Design of RSA Processors Based on High-Radix Montgomery Multipliers
This paper presents a systematic design approach to provide the optimized Rivest-Shamir-Adleman (RSA) processors based on high-radix Montgomery multipliers satisfying various user requirements, such as circuit area, operating time, and resistance ...
Delay-Based Dual-Rail Precharge Logic
This paper investigates the design of a dual-rail precharge logic family whose power consumption is insensitive to unbalanced load conditions thus allowing adopting a semi-custom design flow (automatic place and route) without any constraint on the ...
Prediction and Comparison of High-Performance On-Chip Global Interconnection
As process technology scales, numerous interconnect schemes have been proposed to mitigate the performance degradation caused by the scaling of on-chip global wires. In this paper, we review current on-chip global interconnect structures and develop ...
Adaptive Power Control Technique on Power-Gated Circuitries
An adaptive power control (APC) system on power-gated circuitries is proposed. The core technique is a switching state determination mechanism as an alternative of critical path replicas. It is intrinsically tolerant of process, voltage, and temperature ...
IR-Drop Aware Clustering Technique for Robust Power Grid in FPGAs
IR-drop management in the power supply network of a chip is one of the critical design challenges in nanometer VLSI circuits. Techniques developed for application-specific integrated circuits cannot be directly applied for IR drop management in field-...
Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High- \kappa Metal-Gate Devices
The threshold voltage (VTH) drifts induced by negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) weaken PFETs and high-k metal-gate NFETs, respectively. These long-term VTH drifts degrade SRAM cell stability, ...
Electrical Model of Microcontrollers for the Prediction of Electromagnetic Emissions
This work presents a new methodology to derive the equivalent circuit of the parasitic paths that propagate switching noise in mixed-signals integrated circuits and that usually lead to unintended crosstalk and electromagnetic emission issues. The ...
A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit
This study proposes a high precision fast locking arbitrary duty cycle clock synchronization (HPCS) circuit. This HPCS is capable of synchronizing the external clock and the internal clock in three clock cycles. By using three innovative techniques, the ...
Reduced-Complexity Decoder Architecture for Non-Binary LDPC Codes
Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than binary LDPC codes when the code length is moderate at the cost of higher decoding complexity. The high complexity is mainly caused by the ...
An Efficient Adaptive High Speed Manipulation Architecture for Fast Variable Padding Frequency Domain Motion Estimation
Motion estimation (ME) consumes up to 70% of the entire video encoder's computations and is, therefore, the main encoding-time consuming process. Discrete cosine transform (DCT)-based phase correlation along with dynamic padding (DP) are the recently ...
Buffer Controller-Based Multiple Processing Element Utilization for Dataflow Synthesis
This paper presents an effective design methodology which maps a complex system represented as a dataflow graph to a reconfigurable target architecture having multi-core processors and programmable logics. In order to synchronize data transfers between ...
A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems
New generation embedded systems demand high performance, efficiency, and flexibility. Reconfigurable hardware can provide all these features. However, the costly reconfiguration process and the lack of management support have prevented a broader use of ...
Discretized Network Flow Techniques for Timing and Wire-Length Driven Incremental Placement With White-Space Satisfaction
We present a novel incremental placement methodology called FlowPlace for significantly reducing critical path delays of placed standard-cell circuits without appreciable increase in wire length (WL). FlowPlace includes: 1) a timing-driven (TD) ...
A Provably High-Probability White-Space Satisfaction Algorithm With Good Performance for Standard-Cell Detailed Placement
In this paper, we propose an effective white-space (i.e., row length) constraint satisfaction technique embedded in a network flow based detailed placer for standard cell designs that is suitable for both incremental as well as full detailed placement. ...
A Sub-1 V, 26 \mu W, Low-Output-Impedance CMOS Bandgap Reference With a Low Dropout or Source Follower Mode
We present a low-power bandgap reference (BGR), functional from sub-1 V to 5 V supply voltage with either a low dropout (LDO) regulator or source follower (SF) output stage, denoted as the LDO or SF mode, in a 0.5-μm standard digital CMOS process with V...
A 140 Mb/s to 1.96 Gb/s Referenceless Transceiver With 7.2 \mu s Frequency Acquisition Time
This paper presents a design of a wide-range transceiver without an external reference clock. The self-biased and multi-band PLL with self-initialization technique is used for the wide-operating range of 140 Mb/s to 1.96 Gb/s and fast frequency ...
Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS
Deep sub-micrometer/nano CMOS circuits are more sensitive to externally induced radiation phenomena that are likely to cause the occurrence of so-called soft errors. Therefore, the tolerance of the circuit to the soft errors is a strict requirement in ...
Aggressive Runtime Leakage Control Through Adaptive Light-Weight V_{\rm th} Hopping With Temperature and Process Variation
The increasing leakage power consumption and stringent thermal constraint necessitate more aggressive leakage control techniques. Power gating and body biasing are widely used for standby leakage control. Their large energy overhead for performing mode ...