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research-article

An Accumulator—Based Test-Per-Clock Scheme

Published: 01 June 2011 Publication History

Abstract

We propose a new scheme for reducing the test application time in accumulator-based test-pattern generation. Within this framework, we reduce the problem of efficiently generating test-patterns to that of finding the shortest Hamiltonian path in an associated directed graph. The resulting scheme exhibits extremely low demand for hardware based on a combination of decoders whose inputs are driven by a very slow external tester. Experimental results on ISCAS benchmarks substantiate the superiority of the proposed scheme over the previously-published test-set embedding approaches for accumulator-based test generation.

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  • (2015)Accumulator-based generation for serial TPGProceedings of the 19th Panhellenic Conference on Informatics10.1145/2801948.2801969(426-430)Online publication date: 1-Oct-2015

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Published In

cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems  Volume 19, Issue 6
June 2011
200 pages

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IEEE Educational Activities Department

United States

Publication History

Published: 01 June 2011

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Cited By

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  • (2015)Accumulator-based generation for serial TPGProceedings of the 19th Panhellenic Conference on Informatics10.1145/2801948.2801969(426-430)Online publication date: 1-Oct-2015

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