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GateLock: Input-Dependent Key-Based Locked Gates for SAT Resistant Logic Locking

Authors:

Vijaypal Singh Rathor,

Kshira Sagar Sahoo,

Saraju P. MohantyAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 32, Issue 2

Pages 361 - 371

https://doi.org/10.1109/TVLSI.2023.3340350

Published: 01 February 2024 Publication History

Abstract

Logic locking has become a robust method for reducing the risk of intellectual property (IP) piracy, overbuilding, and hardware Trojan threats throughout the lifespan of integrated circuits (ICs). Nevertheless, the majority of reported logic locking approaches are susceptible to satisfiability (SAT)-based attacks. The existing SAT-resistant logic locking methods provide a tradeoff between security and effectiveness and require a significant design overhead. In this article, a novel gate replacement-based input-dependent key-based logic locking (IDKLL) technique is proposed. We first introduce the concept of IDKLL, and how the IDKLL can mitigate the SAT attacks completely. Unlike conventional logic locking, the IDKLL approach uses multiple key sequences (KSs) (instead of a single KS) as the correct key to lock/unlock the design functionality for all inputs. Based on this IDKLL concept, we developed several locked gates. Further, we propose a lightweight gate replacement-based IDKLL called GateLock that locks the design by replacing exciting gates with their respective IDKLL-based locked gates. The security analysis of the proposed method shows that it prevents the SAT attack completely and forces the attacker to apply a significantly large number of brute-force attempts to decipher the key. The experimental evaluation on International Symposium on Circuits and Systems (ISCAS) and International Test Conference (ITC) benchmarks shows that the proposed GateLock method completely prevents the SAT-based attacks and requires an average of 56.7%, 72.7%, and 87.8% reduced area, power, and delay compared to cascaded locking (CAS-Lock) and strong Anti-SAT (SAS) approaches.

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Cited By

Lopez KRezaei ANakamura YWang Y(2025)K-Gate Lock: Multi-Key Logic Locking Using Input Encoding Against Oracle-Guided AttacksProceedings of the 30th Asia and South Pacific Design Automation Conference10.1145/3658617.3697764(794-800)Online publication date: 20-Jan-2025
https://dl.acm.org/doi/10.1145/3658617.3697764
Amutha MKavitha K(2024)Enhancing security in QCA-based circuits using optimal key gate placementInternational Journal of Information Security10.1007/s10207-024-00842-y23:3(2395-2405)Online publication date: 1-Jun-2024
https://dl.acm.org/doi/10.1007/s10207-024-00842-y

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GateLock: Input-Dependent Key-Based Locked Gates for SAT Resistant Logic Locking

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cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 32, Issue 2

Feb. 2024

196 pages

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1063-8210 © 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See https://www.ieee.org/publications/rights/index.html for more information.

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IEEE Educational Activities Department

United States

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Published: 01 February 2024

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Cited By

Lopez KRezaei ANakamura YWang Y(2025)K-Gate Lock: Multi-Key Logic Locking Using Input Encoding Against Oracle-Guided AttacksProceedings of the 30th Asia and South Pacific Design Automation Conference10.1145/3658617.3697764(794-800)Online publication date: 20-Jan-2025
https://dl.acm.org/doi/10.1145/3658617.3697764
Amutha MKavitha K(2024)Enhancing security in QCA-based circuits using optimal key gate placementInternational Journal of Information Security10.1007/s10207-024-00842-y23:3(2395-2405)Online publication date: 1-Jun-2024
https://dl.acm.org/doi/10.1007/s10207-024-00842-y

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