Variable Conversion Approach for Design Optimization of Low-Voltage Low-Pass Filters
- Lucas Compassi-Severo,
- Tailize C. De-Oliveira,
- Paulo César C. de Aguirre,
- Wilhelmus Van Noije,
- Alessandro G. Girardi
This article describes a design optimization method based on variable conversion applied to low-voltage (LV) CMOS analog integrated circuits. For supply voltages in the range of 0.3 to 0.6 V, traditional design variables (e.g., transistor channel width <...
Enabling Voltage Over-Scaling in Multiplierless DSP Architectures via Algorithm-Hardware Co-Design
The design of low-power digital signal processing (DSP) architectures have gained a lot of attention due to their use in a variety of smart edge applications and portable devices. Recent efforts have focused on the replacement of power-hungry multipliers ...
A Masked Hardware Accelerator for Feed-Forward Neural Networks With Fixed-Point Arithmetic
Neural network (NN) execution on resource-constrained edge devices is increasing. Commonly, hardware accelerators are introduced in small devices to support the execution of NNs. However, an attacker can often gain physical access to edge devices. ...
Layout-Aware Area Optimization of Transposable STT-MRAM for a Processing-In-Memory System
This article presents a layout-aware area optimization methodology for transposable spin-transfer torque magnetic random access memory (STT-MRAM). Although transposable STT-MRAM achieves high performance in processing-in-memory (PIM) systems for a spiking ...
IPOCIM: Artificial Intelligent Architecture Design Space Exploration With Scalable Ping-Pong Computing-in-Memory Macro
Computing-in-memory (CIM) architecture has become a possible solution to designing an energy-efficient artificial intelligent processor. Various CIM demonstrators indicated the computing efficiency of CIM macro and CIM-based processors. However, previous ...
HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer
Self-attention-based transformers have outperformed recurrent and convolutional neural networks (RNN/ CNNs) in many applications. Despite the effectiveness, calculating self-attention is prohibitively costly due to quadratic computation and memory ...
Write–Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge
- Junjie An,
- Zhidao Zhou,
- Linfang Wang,
- Wang Ye,
- Weizeng Li,
- Hanghang Gao,
- Zhi Li,
- Jinghui Tian,
- Yan Wang,
- Hongyang Hu,
- Jinshan Yue,
- Lingyan Fan,
- Shibing Long,
- Qi Liu,
- Chunmeng Dou
High-density and reliable multilevel-cell (MLC) resistive random access memory (RRAM) is expected to meet the ever-increasing demand for on-chip weight storages in the intelligent edge devices. However, due to the device variations, many write-and-verify (...
Scalable and Parallel Optimization of the Number Theoretic Transform Based on FPGA
In lattice-based postquantum cryptography (PQC), polynomial multiplication is complex and time-consuming, which affects the overall computational efficiency. In addition, the parameters of different lattice-based algorithms require different number ...
SiPGuard: Run-Time System-in-Package Security Monitoring via Power Noise Variation
As Moore’s law comes to a crawl, advanced package and integration techniques become increasingly crucial by allowing for the combination of fabricated silicon dies, so-called chiplet, to constitute system-in-package (SiP) achieving a much better ...
TrustGuard: Standalone FPGA-Based Security Monitoring Through Power Side-Channel
The Internet-of-Thing (IoT) era inspires a surge of networked embedded devices in the real world. However, cyber-attacks such as malware intrusions pose severe concerns about the security of the entire IoT space by hijacking the devices, altering the ...
Practical Implementation of Robust State-Space Obfuscation for Hardware IP Protection
Hardware obfuscation is a design transformation technique that transforms a design to protect its confidentiality against untrusted parties. In particular, it aims at protecting proprietary hardware intellectual property (IP) blocks against reverse ...
IOLock: An Input/Output Locking Scheme for Protection Against Reverse Engineering Attacks
Reverse engineering (RE) of hardware designs poses a significant threat to the modern distributed electronics supply chain. RE can be performed at both chip and printed circuit board (PCB) levels by using structural, functional, or combined analysis ...
GateLock: Input-Dependent Key-Based Locked Gates for SAT Resistant Logic Locking
Logic locking has become a robust method for reducing the risk of intellectual property (IP) piracy, overbuilding, and hardware Trojan threats throughout the lifespan of integrated circuits (ICs). Nevertheless, the majority of reported logic locking ...
Improving Radiation Reliability of SRAM-Based Physical Unclonable Function With Self-Healing and Pre-Irradiation Masking Techniques
Physical unclonable function (PUF) is an innovative primitive used for key generation and device authentication, which has promising applications for resource-limited scenarios such as satellite communication. However, the reliability of traditional PUF ...
High-Performance ECC Scalar Multiplication Architecture Based on Comb Method and Low-Latency Window Recoding Algorithm
Elliptic curve scalar multiplication (ECSM) is the essential operation in elliptic curve cryptography (ECC) for achieving high performance and security. We introduce a novel high-performance ECSM architecture over binary fields to meet the growing demand ...
MPRTA: An Efficient Multilevel Parallel Mobile Accelerator for High-Performance Ray Tracing
Ray tracing has been regarded as the future of graphics rendering technology for a long time. However, interactive ray tracing still faces challenges, especially in mobile devices, such as high computational intensity and multiple branches. In this brief, ...