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research-article

Fault Analysis-Based Logic Encryption

Authors:

Jeyavijayan Rajendran,

Garrett S. Rose,

Ozgur Sinanoglu,

Ramesh KarriAuthors Info & Claims

IEEE Transactions on Computers, Volume 64, Issue 2

Pages 410 - 424

https://doi.org/10.1109/TC.2013.193

Published: 01 February 2015 Publication History

Abstract

Globalization of the integrated circuit (IC) design industry is making it easy for rogue elements in the supply chain to pirate ICs, overbuild ICs, and insert hardware Trojans. Due to supply chain attacks, the IC industry is losing approximately $4 billion annually. One way to protect ICs from these attacks is to encrypt the design by inserting additional gates such that correct outputs are produced only when specific inputs are applied to these gates. The state-of-the-art logic encryption technique inserts gates randomly into the design, but does not necessarily ensure that wrong keys corrupt the outputs. Our technique ensures that wrong keys corrupt the outputs. We relate logic encryption to fault propagation analysis in IC testing and develop a fault analysis-based logic encryption technique. This technique enables a designer to controllably corrupt the outputs. Specifically, to maximize the ambiguity for an attacker, this technique targets 50% Hamming distance between the correct and wrong outputs (ideal case) when a wrong key is applied. Furthermore, this 50% Hamming distance target is achieved using a smaller number of additional gates when compared to random logic encryption.

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Cited By

McDaniel IZuzak MSrivastava A(2024)Removal of SAT-Hard Instances in Logic Obfuscation Through Inference of FunctionalityACM Transactions on Design Automation of Electronic Systems10.1145/367490329:4(1-23)Online publication date: 25-Jun-2024
https://dl.acm.org/doi/10.1145/3674903
Ahmed BRahman SAzar KFarahmandi FRahman FTehranipoor M(2024)SeeMLess: Security Evaluation of Logic Locking using Machine Learning oriented EstimationProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3660382(489-494)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3660382
Madera JJuretus K(2024)Boolean Domain Attack on Corrupt and Correct Based Logic Locking TechniquesProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658710(415-420)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3658710
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cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 64, Issue 2

Feb. 2015

297 pages

ISSN:0018-9340

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Copyright © 2013.

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 February 2015

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Cited By

McDaniel IZuzak MSrivastava A(2024)Removal of SAT-Hard Instances in Logic Obfuscation Through Inference of FunctionalityACM Transactions on Design Automation of Electronic Systems10.1145/367490329:4(1-23)Online publication date: 25-Jun-2024
https://dl.acm.org/doi/10.1145/3674903
Ahmed BRahman SAzar KFarahmandi FRahman FTehranipoor M(2024)SeeMLess: Security Evaluation of Logic Locking using Machine Learning oriented EstimationProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3660382(489-494)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3660382
Madera JJuretus K(2024)Boolean Domain Attack on Corrupt and Correct Based Logic Locking TechniquesProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658710(415-420)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3658710
Talukdar JPaik WOrtega EChakrabarty K(2024)ALT-Lock: Logic and Timing Ambiguity-Based IP Obfuscation Against Reverse EngineeringIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.341103332:8(1535-1548)Online publication date: 1-Aug-2024
https://dl.acm.org/doi/10.1109/TVLSI.2024.3411033
Rathor VSingh MSahoo KMohanty S(2024)GateLock: Input-Dependent Key-Based Locked Gates for SAT Resistant Logic LockingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.334035032:2(361-371)Online publication date: 1-Feb-2024
https://dl.acm.org/doi/10.1109/TVLSI.2023.3340350
Azar KKamali HFarahmandi FTehranipoor M(2024)Improving Bounded Model Checkers Scalability for Circuit De-Obfuscation: An ExplorationIEEE Transactions on Information Forensics and Security10.1109/TIFS.2024.335728619(2771-2785)Online publication date: 1-Jan-2024
https://dl.acm.org/doi/10.1109/TIFS.2024.3357286
Han ZDixit APatnaik SRajendran J(2024)STATION: State Encoding-Based Attack-Resilient Sequential ObfuscationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.338787343:10(2888-2901)Online publication date: 1-Oct-2024
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Suemitsu KMatsuoka KSato THashimoto MKim T(2024)Logic Locking over TFHE for Securing User Data and AlgorithmsProceedings of the 29th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC58780.2024.10473831(600-605)Online publication date: 22-Jan-2024
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Rahman MZamiri Azar KFarahmandi FMardani Kamali HThapliyal HDeMara RPartin-Vaisband IKatkoori S(2023)Metrics-to-Methods: Decisive Reverse Engineering Metrics for Resilient Logic LockingProceedings of the Great Lakes Symposium on VLSI 202310.1145/3583781.3590273(685-690)Online publication date: 5-Jun-2023
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