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research-article

Characterization of In-Cone Logic Locking Resiliency Against the SAT Attack

Authors:

Ioannis SavidisAuthors Info & Claims

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 39, Issue 8

Pages 1607 - 1620

https://doi.org/10.1109/TCAD.2019.2925387

Published: 01 August 2020 Publication History

Abstract

The resiliency of in-cone logic locking techniques to the satisfiability (SAT) attack is characterized in this paper. An analysis of the parameters of the SAT solver that impact security and a characterization of the effect netlist topology has on the security of the circuit is presented. The analysis of SAT solver parameters and logic structure is used to develop three novel logic locking gate selection algorithms based on maximum fanout free cones (MFFCs) and gate controllability for circuits implementing XOR, look-up table (LUT), and <inline-formula> <tex-math notation="LaTeX">$2\times 1$ </tex-math></inline-formula> MUX-based logic obfuscation. The XOR, LUT, and MUX MFFC-based algorithms resulted in an average increase of, respectively, 61.8%, 123.6%, and 38.5% in the minimum number of iterations required to complete the SAT attack across 1,000 different variable orderings of the netlist while applying the locking techniques to 5% of the gates within the netlist. In addition, the SAT attack resiliency and output corruption of the developed algorithms are compared with out-of-cone locking techniques.

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Cited By

Abideen ZGokulanathan SJ. Aljafar MPagliarini S(2024)An Overview of FPGA-inspired Obfuscation TechniquesACM Computing Surveys10.1145/367711856:12(1-35)Online publication date: 9-Jul-2024
https://dl.acm.org/doi/10.1145/3677118
Halder DMerugu MRay S(2023)ObNoCs: Protecting Network-on-Chip Fabrics Against Reverse-Engineering AttacksACM Transactions on Embedded Computing Systems10.1145/360910722:5s(1-21)Online publication date: 31-Oct-2023
https://dl.acm.org/doi/10.1145/3609107
Leonhard JLimaye NTurk SSayed ARizo AAboushady HSinanoglu OStratigopoulos H(2022)Digitally Assisted Mixed-Signal Circuit SecurityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.311155041:8(2449-2462)Online publication date: 1-Aug-2022
https://dl.acm.org/doi/10.1109/TCAD.2021.3111550

Index Terms

Characterization of In-Cone Logic Locking Resiliency Against the SAT Attack
1. Hardware
2. Security and privacy

Index terms have been assigned to the content through auto-classification.

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cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume 39, Issue 8

Aug. 2020

200 pages

ISSN:0278-0070

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0278-0070 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See https://www.ieee.org/publications/rights/index.html for more information.

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IEEE Press

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Published: 01 August 2020

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Cited By

Abideen ZGokulanathan SJ. Aljafar MPagliarini S(2024)An Overview of FPGA-inspired Obfuscation TechniquesACM Computing Surveys10.1145/367711856:12(1-35)Online publication date: 9-Jul-2024
https://dl.acm.org/doi/10.1145/3677118
Halder DMerugu MRay S(2023)ObNoCs: Protecting Network-on-Chip Fabrics Against Reverse-Engineering AttacksACM Transactions on Embedded Computing Systems10.1145/360910722:5s(1-21)Online publication date: 31-Oct-2023
https://dl.acm.org/doi/10.1145/3609107
Leonhard JLimaye NTurk SSayed ARizo AAboushady HSinanoglu OStratigopoulos H(2022)Digitally Assisted Mixed-Signal Circuit SecurityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.311155041:8(2449-2462)Online publication date: 1-Aug-2022
https://dl.acm.org/doi/10.1109/TCAD.2021.3111550
Miketic ISalman E(2021)PhaseCamouflage: Leveraging Adiabatic Operation to Thwart Reverse EngineeringIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.307856729:7(1285-1296)Online publication date: 1-Jul-2021
https://dl.acm.org/doi/10.1109/TVLSI.2021.3078567

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