Abstract
3D IC extends interconnect technology across multiple chips, multiple domains (digital, custom/RF, memory) and multiple technology nodes. In addition to the heterogeneous system integration, 3D IC offers multiple types of configuration such as 3D IC vertical stack, and silicon interposer. Another dimension of 3D IC is the integration with package, that adds a large number of configuration such as "embedded wafer level package = e-WLP" and "3D wafer level package". All these types of 3D IC integration bring together multiple design system (digital design, custom/analog design, and package design). As such it will require a team of designers with different expertise to implement an integrated system of 3D IC.
The focus of this invited talk is to explore 3D IC physical modeling, physical design methodology and physical design tools. We have added infra-structure in the database, library interfaces and tools to allow the specification of 3D IC configuration and interconnect components. Both physical design tools and analysis tools have been enabled to support 3D IC design and analysis using the same modeling and infra-structure. We have developed design methodology with early 3D IC designers that allowed focusing on design flow that is optimized for popular stacking styles.
3D IC adds new physical components, which must be modeled and supported by physical design tools. TSV with backside metal layers and micro-bump (cupper pillars) are examples of these components. The new components have design rules associated with them as well as design constraints. The design constraints are added to avoid mechanical stress associated with TSV and substrate thinning. Physical design tools such as placement and routing have been enabled to allow the user to apply these components during the different stages of the physical design flow. These enhancements allow the designer to maintain the investment in IC tools that are being used and apply 3D IC features and design flow in an efficient manner.
Formal specification is developed to allow the description of 3D IC stack configuration and also to describe the types of signals/power that go through the stack. Both the vertical 3D IC stacks and silicon interposer are well supported. In addition to managing the stack, the designer has also the capability to do early planning for special signals and power that should traverse the stack in a shortest distance. High speed signals are examples of those special signals.
Early floorplanning is one of the strength of EDI system that allows the designer/design team to plan and implement any 3D IC connectivity with new patterns and/or pre-defined patterns (TSV and micro-bumps). We have developed several design methodologies to guide the designer during the planning, placement and routing stages. In every design tape-out we have done so far, there are usually several signals and power that must be pre-defined and put in special location on each chip. We have developed automated features allow the placement and routing of TSV and micro-bump in any user defined pattern. In many cases, the assignment of signals is usually dictated by package/board design and provides assignment constraints that must be propagated through the entire stack.
In summary, the talk will provide the basic modeling features of 3D IC to allow the specification and the integration of multiple chips in either vertical stack or silicon interposer. Then the second part of the talk is to focus on placement and routing of the 3D IC interconnect components and how those are integrated in a design flow.
