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- research-articleMay 2017
Neuromorphic 3D Integrated Circuit: A Hybrid, Reliable and Energy Efficient Approach for Next Generation Computing
GLSVLSI '17: Proceedings of the Great Lakes Symposium on VLSI 2017Pages 221–226https://doi.org/10.1145/3060403.3060470In this paper, we proposed to use 3D integration technology to create a neuromorphic hardware system that is compatible with current technology, provides high system speed, high density, massively parallel processing, low power consumption, and small ...
- research-articleMay 2015
Small-World Network Enabled Energy Efficient and Robust 3D NoC Architectures
GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSIPages 133–138https://doi.org/10.1145/2742060.2742085Three dimensional (3D) Network-on-Chip (NoC) architectures enable design of low power and high performance communication fabrics for multicore chips. In spite of achievable performance benefits, 3D NoCs are still bottlenecked by the planar ...
- invited-talkMarch 2015
From 2D to Monolithic 3D: Design Possibilities, Expectations and Challenges
- Olivier Billoint,
- Hossam Sarhan,
- Iyad Rayane,
- Maud Vinet,
- Perrine Batude,
- Claire Fenouillet-Beranger,
- Olivier Rozeau,
- Gerald Cibrario,
- Fabien Deprat,
- Ogun Turkyilmaz,
- Sebastien Thuries,
- Fabien Clermidy
ISPD '15: Proceedings of the 2015 Symposium on International Symposium on Physical DesignPage 127https://doi.org/10.1145/2717764.2723573Design of conventional 2D integrated circuits is becoming more and more challenging as we strive to keep on following Moore's law. Cost, thermal behavior, multiple patterning, increasing number of design rules, transistor characteristics, variability ...
- posterAugust 2014
Gated low-power clock tree synthesis for 3D-ICs
ISLPED '14: Proceedings of the 2014 international symposium on Low power electronics and designPages 319–322https://doi.org/10.1145/2627369.2627665In this paper, we minimize 3D clock power using shutdown gates to selectively turn off unnecessary clock activities. In 3D-IC, shutdown signals require large-sized Through-Silicon-Vias(TSVs), so we propose a simulated annealing(SA) based algorithm along ...
- posterMay 2013
Physical design exploration of 3D tree-based FPGA architecture
GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSIPages 335–336https://doi.org/10.1145/2483028.2483130An innovative 3D physical design exploration methodology for Tree-based FPGA architecture is presented in this paper. In a Tree-based FPGA architecture, the interconnects are arranged in a multidimensional network with the logic unites and switch blocks ...
- posterMay 2013
Power gating topologies in TSV based 3D integrated circuits
GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSIPages 327–328https://doi.org/10.1145/2483028.2483125Two topologies are proposed at the physical level to achieve reliable power gating in through silicon via (TSV) based three-dimensional (3D) integrated circuits (ICs). The proposed lumped and distributed power gating topologies address the unique ...
- research-articleMay 2013
Effect of TSV fabrication technology on power distribution in 3D ICs
GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSIPages 287–292https://doi.org/10.1145/2483028.2483111The design implications of two distinct through silicon via (TSV) fabrication methods (via-first and via-last) have been investigated for power delivery in a 3D system. Different geometry, connectivity, and filling materials have been considered to ...
- research-articleMay 2013
Thermal stress aware 3D-IC statistical static timing analysis
GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSIPages 281–286https://doi.org/10.1145/2483028.2483110It is widely known that fabrication and thermal variations influence circuit delay. In three dimensional circuits (3D-ICs), due to the incorporation of through-silicon-vias (TSVs), thermal stress also becomes an increasing contributor to gate delay. As ...
- research-articleMay 2013
Efficient characterization of TSV-to-transistor noise coupling in 3D ICs
GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSIPages 71–76https://doi.org/10.1145/2483028.2483064A methodology is proposed to characterize TSV induced noise coupling in three-dimensional (3D) integrated circuits. Different substrate biasing schemes (such as a single substrate contact versus regularly placed substrate contacts) and TSV fabrication ...
- research-articleMarch 2012
TSV-constrained micro-channel infrastructure design for cooling stacked 3D-ICs
ISPD '12: Proceedings of the 2012 ACM international symposium on International Symposium on Physical DesignPages 113–118https://doi.org/10.1145/2160916.2160941Micro-channel based liquid cooling has significant capability of removing high density heat in 3D-ICs. The conventional micro-channel structures investigated for cooling 3D-ICs use straight channels. However, the presence of TSVs which form obstacles to ...
- research-articleMarch 2012
Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph
ISPD '12: Proceedings of the 2012 ACM international symposium on International Symposium on Physical DesignPages 105–112https://doi.org/10.1145/2160916.2160940In this paper, we propose a new approach for gated bus synthesis [16] with minimum wire capacitance per transaction in three-dimensional (3D) ICs. The 3D IC technology connects different device layers with through-silicon vias (TSV), which need to be ...
- research-articleOctober 2011
Memory controllers for high-performance and real-time MPSoCs: requirements, architectures, and future trends
- Benny Akesson,
- Po-Chun Huang,
- Fabien Clermidy,
- Denis Dutoit,
- Kees Goossens,
- Yuan-Hao Chang,
- Tei-Wei Kuo,
- Pascal Vivet,
- Drew Wingard
CODES+ISSS '11: Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesisPages 3–12https://doi.org/10.1145/2039370.2039374Designing memory controllers for complex real-time and high-performance multi-processor systems-on-chip is challenging, since sufficient capacity and (real-time) performance must be provided in a reliable manner at low cost and with low power ...
- abstractMarch 2011
3DICs for tera-scale computing: a case study
ISPD '11: Proceedings of the 2011 international symposium on Physical designPages 77–78https://doi.org/10.1145/1960397.1960415TSV-based 3D chip stacking and integration technology was proposed more than twelve years ago. Since then the concept has gained tremendous traction with significant advances in the technology and planned system prototypes. The IP portfolio in 3D ...
- research-articleJune 2010
Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs
SLIP '10: Proceedings of the 12th ACM/IEEE international workshop on System level interconnect predictionPages 25–32https://doi.org/10.1145/1811100.1811108In this paper, we present a delay and power prediction model for buffered interconnects used in 3D ICs. The key idea is to model the impact of RC parasitics of Through-Silicon Vias (TSVs) used in 3D interconnects on delay and power consumption. Due to ...
- invited-talkMarch 2010
Physical design implementation for 3D IC: methodology and tools
ISPD '10: Proceedings of the 19th international symposium on Physical designPage 57https://doi.org/10.1145/1735023.17350423D IC extends interconnect technology across multiple chips, multiple domains (digital, custom/RF, memory) and multiple technology nodes. In addition to the heterogeneous system integration, 3D IC offers multiple types of configuration such as 3D IC ...
- research-articleJuly 2009
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs
SLIP '09: Proceedings of the 11th international workshop on System level interconnect predictionPages 85–92https://doi.org/10.1145/1572471.1572486Individual dies in 3D integrated circuits are connected using through-silicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power overhead. However, the effects of TSV overheads have not been studied ...